SN75970B SCSI DIFFERENTIAL CONVERTER-CONTROL SLLS323A – NOVEMBER 1999 – REVISED JANUARY 2000 D D D D D D D D D Provides High-Voltage Differential SCSI from Single-Ended Controller When Used With the SN75971B Data Transceiver Nine Transceivers Meet or Exceed the Requirements of ANSI Standard EIA-485 and ISO-8482 Standards ESD Protection on Bus Pins to 12 kV Packaged in Shrink Small-Outline Package with 25 mil Terminal Pitch and Thin Small-Package with 20 mil Terminal Pitch Low Disabled Supply Current 32 mA Typ Thermal Shutdown Protection Positive- and Negative-Current Limiting Power-Up/-Down Glitch Protection Open-Circuit Failsafe Receivers description The SN75970B SCSI differential convertercontrol, when used in conjunction with one or more of its companion data transceiver(s), provides the superior electrical performance of differential SCSI from a single-ended SCSI bus controller. A 16-bit, Fast-SCSI bus can be implemented with just three devices (two for data and one for control) in the space-efficient, 56-pin, shrink small-outline package (SSOP) as well as the even smaller TSSOP and a few external components. The SN75970B is available in a B2 (20 Mxfer) version and a B1 (10 Mxfer) version. DGG OR DL PACKAGE (TOP VIEW) RSTFLTR RESET DSENS CLK40 GND AATN – TEST AACK – TIMEOUT AREQ – AC/D – VCC GND GND GND GND GND VCC DRVBUS SDB AMSG – AI/O – ASEL– NC ABSY – NC ARST – NC 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 X2 X1/CLK20 NC BATN – BATN+ BACK – BACK+ BREQ – BREQ+ BC/D – BC/D+ VCC GND GND GND GND GND VCC BMSG – BMSG+ BI/O – BI/O+ BSEL+ BSEL – BBSY+ BBSY – BRST+ BRST – NC – No internal connection Terminals 13 through 17 and 40 through 44 are In a typical differential SCSI node, the SCSI connected together to the package lead frame and controller provides the enables for each external signal ground. RS-485 transceiver. This could require as many as 27 additional terminals for a 16-bit differential bus controller or relegate a 16-bit single-ended controller to only an 8-bit differential bus. Using the standard nine SCSI control signals, the SN75970B control transceiver decodes the state of the bus and enables the SN75971B data transceiver(s) to transmit the single-ended SCSI input signals differentially to the cable or receive the differential cable signals and drive the single-ended outputs to the controller. The single-ended SCSI bus interface consists of CMOS bidirectional inputs and outputs. The drivers are rated at ±16 mA of output current. The receiver inputs are pulled high with approximately 4 mA to eliminate the need for external pullup resistors for the open-drain outputs of most single-ended SCSI controllers. The single-ended side of the device is not intended to drive the SCSI bus directly. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN75970B SCSI DIFFERENTIAL CONVERTER-CONTROL SLLS323A – NOVEMBER 1999 – REVISED JANUARY 2000 logic diagram (positive logic) description (continued) The differential SCSI bus interface consists of bipolar bidirectional inputs and outputs that meet or exceed the requirements of EIA-485 and ISO 8482-1982/TIA TR30.2 referenced by the American National Standard of Information Systems (ANSI) X3.131-1994 Small Computer System Interface-2 (SCSI-2) and SCSI-3 Fast-20 Parallel Interface (Fast-20) X3.277:1996. The SN75970B is characterized for operation over the temperature range of 0°C to 70°C. The SN75970B consists of nine RS-485 differential transceivers, nine TTL- or CMOS-level compatible transceivers, a state machine and control logic block, a 20-MHz crystal-controlled oscillator, a timer, a power-up/-down glitch protection circuit, and a thermal-shutdown protection circuit. The single-ended or controller interface is designated as the A side and the differential port is the B side. Since the device uses the SCSI control signals to decode the state of the bus and data flow direction, the terminal assignments must be matched to the corresponding signal on the SCSI bus. The signal name followed by a a minus sign (–) indicates an active-low signal while a plus sign (+) indicates an active-high signal. A reset function, which disables all outputs and clears internal latches, can be accomplished from two external inputs and two internally generated signals. RESET (Reset) and DSENS (differential sense) are available to external circuits for a bus reset or to disable all outputs should a single-ended cable be inadvertently connected to a differential connector. The power-up and thermal-shutdown are internally generated signals that have the same effect when the supply voltage is below 3.5 V or the junction temperature exceeds approximately 175°C. This data sheet contains descriptions of the SN75970B input and output signals followed by the electrical characteristics. The parameter measurement information is followed by the theory of operation, a state flow chart, and a typical circuit in the application information section. AATN – AACK – AMSG – AC/D – AREQ – AI/O – 53 6 52 51 8 50 38 21 37 47 11 46 49 10 48 36 22 35 30 27 ARST – ABSY – ASEL – DSENS TEST RESET RSTFLTR CLK40 POST OFFICE BOX 655303 H 31 H 33 34 23 BATN + BACK – BACK + BMSG – BMSG + BC/D – BC/D + BREQ – BREQ + BI/O – BI/O + BRST + BRST – BBSY + BBSY – BSEL + BSEL – 19 DRVBUS State Machine and Control Logic 20 SDB 9 X1/CLK20 X2 55 Oscillator 56 Power-Up and Reset Logic 2 29 32 25 3 7 2 1 4 H BATN – • DALLAS, TEXAS 75265 TIMEOUT H Thermal Shutdown SN75970B SCSI DIFFERENTIAL CONVERTER-CONTROL SLLS323A – NOVEMBER 1999 – REVISED JANUARY 2000 Terminal Functions TERMINAL NO. LOGIC LEVEL I/O TERMINATION 8 TTL I/O strong pullup SCSI acknowledge (– ACK) signal to/from controller AATN – 6 TTL I/O strong pullup SCSI attention (– ATN) signal to/from controller ABSY – 25 TTL I/O strong pullup SCSI busy (– BSY) signal to/from the controller AC/D – 11 TTL I/O strong pullup SCSI control/data (– C/D) signal to/from the controller AI/O – 22 TTL I/O strong pullup SCSI input/output (– I/O) signal to/from the controller AMSG – 21 TTL I/O strong pullup SCSI message (– MSG) signal to/from the controller AREQ – 10 TTL I/O strong pullup SCSI request (– REQ) signal to/from controller ARST – 27 TTL I/O strong pullup SCSI reset (– RST) signal to/from the controller ASEL – 23 TTL I/O strong pullup SCSI select (– SEL) signal to/from the controller BACK – 51 RS-485 I/O weak pullup SCSI acknowledge (– ACK) signal to/from the bus BACK+ 50 RS-485 I/O weak pulldown SCSI acknowledge (+ACK) signal to/from the bus BATN – 53 RS-485 I/O weak pullup SCSI attention (– ATN) signal to/from the bus BATN+ 52 RS-485 I/O weak pulldown SCSI attention (+ATN) signal to/from the bus BBSY – 31 RS-485 I/O weak pulldown SCSI busy (– BSY) signal to/from the bus BBSY+ 32 RS-485 I/O weak pullup SCSI busy (+BSY) signal to/from the bus BC/D – 47 RS-485 I/O weak pullup SCSI control/data (– C/D) signal to/from the bus BC/D+ 46 RS-485 I/O weak pulldown SCSI control/data (+C/D) signal to/from the bus BI/O – 36 RS-485 I/O weak pullup SCSI input/output (– I/O) signal to/from the bus BI/O+ 35 RS-485 I/O weak pulldown SCSI input/output (+I/O) signal to/from the bus BMSG – 38 RS-485 I/O weak pullup SCSI message (– MSG) signal to/from the bus BMSG+ 37 RS-485 I/O weak pulldown SCSI message (+MSG) signal to/from the bus BREQ – 49 RS-485 I/O weak pullup SCSI request (– REQ) signal to/from the bus BREQ+ 48 RS-485 I/O weak pulldown SCSI request (+REQ) signal to/from the bus BRST – 29 RS-485 I/O weak pulldown SCSI reset (– RST) signal to/from the bus BRST+ 30 RS-485 I/O weak pullup SCSI reset (+RST) signal to/from the bus BSEL – 33 RS-485 I/O weak pulldown SCSI select (– SEL) signal to/from the bus BSEL+ 34 RS-485 I/O weak pullup SCSI select (+SEL) signal to/from the bus CLK40 4 CMOS I strong pulldown 40-MHz clock input DRVBUS 19 TTL O N/A Driver bus. A high-level logic signal that indicates the SCSI bus is in one of the information transfer phases. weak pullup A low-level input initializes the internal latches and disables all drivers. N/A Supply common NAME AACK – DSENS DESCRIPTION 3 TTL I 5, 13–17, 40–44 N/A N/A RESET 2 TTL I weak pullup Reset. A low-level input initializes the internal latches and disables all drivers. RSTFLTR 1 TTL I weak pullup Reset filter. Filtered input from the SCSI bus for a system reset. RSTFLTR differs from RESET by keeping the ARST and BRST drivers enabled. SDB 20 TTL O N/A A high-level logic signal that indicates a differential to single-ended data flow. TEST 7 TTL I weak pulldown Test. A high-level input that places the device in a test mode (see Table 1). It is grounded during normal operation. TIMEOUT 9 Analog I/O N/A Time out. This signal connects to an external RC time constant for a time out during bus arbitration. VCC X1 /CLK20 12, 18, 39, 45 N/A N/A N/A 5-V supply voltage 55 CMOS I none 20-MHz crystal oscillator or clock input 56 Analog O none 20-MHz crystal oscillator feedback GND X2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN75970B SCSI DIFFERENTIAL CONVERTER-CONTROL SLLS323A – NOVEMBER 1999 – REVISED JANUARY 2000 schematics of inputs and outputs RSTFLTR, RESET, AND DSENS TEST TIMEOUT VCC 22 k VCC VCC 200 Ω 200 Ω Input Input Input 200 Ω 50 kΩ CLK40 A B + AND B – Inputs VCC VCC VCC 100 kΩ B – Pin Only 4 mA 200 Ω Input Input Input 200 Ω 18 kΩ 100 kΩ B + Pin Only X1/CLK20, X2 VCC 3 kΩ A, SDB, DRVBUS VCC 12 kΩ 1 kΩ B + AND B – Outputs VCC 200 Ω X1/CLK20 Output B– 18 kΩ 100 kΩ Output VCC X2 4 B+ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN75970B SCSI DIFFERENTIAL CONVERTER-CONTROL SLLS323A – NOVEMBER 1999 – REVISED JANUARY 2000 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 6 V Differential bus voltage range (B side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –10 V to 15 V Signal-ended bus voltage range (A side and control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Electrostatic discharge: B side (see Note 2): Class 3, A: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 kV Class 3, B: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 V All terminals: Class 2, A: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 kV Class 2, B: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 V Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to the GND terminals. 2. This absolute maximum rating is tested in accordance with MIL-STD-883C, Method 3015.7. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING OPERATING FACTOR‡ ABOVE TA = 25°C DGG 3333 mW 26.7 mW/°C DL 3709 mW 29.7 mW/°C TA = 70°C POWER RATING 2133 mW 2374 mW ‡ This is the inverse of the traditional junction-to-case thermal resistance (RθJA) for High-K (per JEDEC) PCB installations. recommended operating conditions Supply voltage, VCC High level input voltage, voltage VIH High-level Low level input voltage, Low-level voltage VIL Input voltage g at any y bus terminal ((separately y or common-mode), VI High level output current, High-level current IOH Low level output current Low-level current, IOL frequency fCLK Clock frequency, A side, DSENS, TEST, RESET, AND RSTFLTR CLK40 AND X1/CLK20 MIN NOM MAX UNIT 4.75 5 5.25 V 2 V 0.7 VCC A side, DENS, TEST, RESET, and RSTFLTR 0.8 CLK40 AND X1/CLK20 0.2 VCC 12 B side –7 A side, DRVBUS, SDB, TIMEOUT – 16 V V mA X2 –4 A side, DRVBUS, and SDB 16 mA 4 mA X2 CLK20 20 CLK40 40 MHz Operating case temperature, TC 0 125 °C Operating free-air temperature, TA 0 70 °C POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN75970B SCSI DIFFERENTIAL CONVERTER-CONTROL SLLS323A – NOVEMBER 1999 – REVISED JANUARY 2000 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) MIN TYP† –0.8 –2.2 V 1 1.8 V VID = – 200 V, IOH = – 16 mA 2.5 4.3 IOH = – 16 mA Test and RESET at 0.8 V, All others open, IOH = – 16 mA 2.5 4.4 2.5 4.5 PARAMETER VOD(H) VOD(L) TEST CONDITIONS Driver differential high-level output voltage B side except BBSY, BRST, and BSEL Driver differential low-level output voltage B side AACK –, AATN –, AC/D –, AI/O –, AMSG –, AREQ – DRVBUS, SDB VOH Hi h l High-level l output t t voltage lt TIMEOUT V 3.4 X2 Low level output voltage Low-level DRVBUS, SDB IOH = - 4 mA IOL = 16 mA A side VID = 200 mV, IOL = 16 mA B side VIT IT– Receiver negative-going g g g input threshold voltage TIMEOUT Vh hys Receiver input hysteresis y (VIT+ – VIT– ) TIMEOUT B side 0.2 2.6 IOL = 16 mA, See Figure 2 – 0.2‡ 0.32 VCC B side 0.4 VCC 45 B side 0.6 1 VI = 12 V, VCC = 0, All other inputs at 0 V 0.7 1 VI = –7 V, VCC = 5 V, All other inputs at 0 V – 0.5 – 0.8 VI = –7 V, VCC = 0, All other inputs at 0 V – 0.4 – 0.8 –6 –8 – 60 – 100 mA CLK40, X1/CLK20 ± 20 TEST 100 TIMEOUT TEST at 2 V, A side and other control inputs at 0.8 V, B side open, VIH = 2 V V V VI = 12 V, VCC = 5 V, All other inputs at 0 V VIH = 2 V V mV 0.5 – 2.0 DSENS, RESET, RSTFLTR V 0.8 TIMEOUT A side High-level input in ut current 0.8 IOL = 4 mA IOH = – 16 mA, See Figure 2 Receiver positive-going g g input threshold voltage IIH 0.8 1.6 VIT IT+ Bus input current 3.2 B side X2 II UNIT See Figure 1 B side VOL MAX mA µA ± 25 † All typical values are at VCC = 5 V, TA = 25°C. ‡ The algebraic convention with the least positive (more negative) limit is designated minimum, is used in this data sheet for the differential input voltage only. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN75970B SCSI DIFFERENTIAL CONVERTER-CONTROL SLLS323A – NOVEMBER 1999 – REVISED JANUARY 2000 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (Continued) PARAMETER TEST CONDITIONS A side DSENS, RESET, RSTFLTR IIL Low-level in input ut current Short circuit output current Supply current MAX –6 –9 ± 30 ± 30 B side TEST at 2 V, A side and other control inputs at 0.8 V, B side open, VIL = 0.8 V VO = 5 V and 0 V RESET at 0.8 V, All others open ± 250 32 42 All A-side to B-side channels enabled 72 95 All B-side to A-side channels enabled TEST and B+ pins at 2 V, RESET, RSTFLTR, and B– pins at 0.8 V, All other inputs open, No load 51 72 B side to GND, VI = 0.6 sin(2π 106 t)+ 1.5 V 18 21 Bus output capacitance Cpd d Power dissipation capacitance (see Note 3) mA µA ± 25 TEST and RSTFLTR at 2 V RESET at 0.8 V, All other inputs open, No load Co UNIT – 100 VIL = 0.8 V TEST Disabled ICC TYP† CLK40, X1/CLK20 TIMEOUT IOS MIN mA mA B side to A side, one channel 40 A side to B side, one channel 100 pF pF pF † All typical values are at VCC = 5 V, TA = 25°C. NOTE 3: Cpd determines the no-load dynamic current consumption, IS = Cpd × VCC × f + ICC (ICC depends upon the output states and load circuits and is not necessarily the same ICC as specified in the electrical tables). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN75970B SCSI DIFFERENTIAL CONVERTER-CONTROL SLLS323A – NOVEMBER 1999 – REVISED JANUARY 2000 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) FROM (INPUT) TO (OUTPUT) AATN – AC/D – AI/O – AMSG – BATN ± BC/D ± BI/O ± BMSG ± AACK – AREQ – BACK ± BREQ ± AATN – AC/D – AI/O – AMSG – BATN ± BC/D ± BI/O ± BMSG ± AACK – AREQ – BACK ± BREQ ± ’B1 AACK – AREQ – BACK ± BREQ ± See Note 4 8 ’B2 AACK – AREQ – BACK ± BREQ ± See Note 4 4 ’B1 AACK – AREQ – BACK ± BREQ ± See Note 5 8 ’B2 AACK – AREQ – BACK ± BREQ ± See Note 5 4 BATN ± BC/D ± BI/O ± BMSG ± AATN – AC/D – AI/O – AMSG – See Figure 4 BACK ± BREQ ± AACK – AREQ – BATN ± BC/D ± BI/O ± BMSG ± AATN – AC/D – AI/O – AMSG – BACK ± BREQ ± AACK – AREQ – ’B1 BACK ± BREQ ± AACK – AREQ – See Note 4 9 ’B2 BACK ± BREQ ± AACK – AREQ – See Note 4 4.5 ’B1 BACK ± BREQ ± AACK – AREQ – See Note 5 8 ’B2 BACK ± BREQ ± AACK – AREQ – See Note 5 4 PARAMETER ’B1 B1 td1, td2 Delay time, A to B, high- to low-level low level or lowlow to high-levhigh lev el output ’B2 B2 tsk(pp) k( ) tsk(p) k( ) Skew part-to-part part to part Skew, Pulse skew ’B1 B1 td3, d3 td4 Delay time, B to A, high- to low level or lowlow-level low to high-levhigh lev el output ’B2 B2 tsk(pp) k( ) tsk(p) k( ) Skew part-to-part part to part Pulse skew TEST CONDITIONS See Figure 3 MIN TYP† MAX 35 3.5 17 7 17.7 3.1 15.3 VCC = 5 V, TA = 25°C VCC = 5 V, TA = 70°C 4.2 12.2 4.7 12.7 See Figure 3 55 5.5 15 7 15.7 4.5 13.3 6.2 10.2 6.7 10.7 VCC = 5 V, TA = 25°C VCC = 5 V, TA = 70°C UNIT ns ns ns 5.1 17.9 5.3 18 VCC = 5 V, TA = 25°C VCC = 5 V, TA = 70°C 6.3 15.2 6.7 15.6 See Figure 4 7.3 14.6 7.5 14.2 8.5 13 8.9 13.4 VCC = 5 V, TA = 25°C VCC = 5 V, TA = 70°C ns ns ns † All typical values are at VCC = 5 V, TA = 25°C. NOTES: 4. Part-to-part skew is the magnitude of the difference in propagation delay times between any two devices when both operate with the same supply voltages, the same temperature, and the same loads. 5. Pulse skew is the difference between the high-to-low and low-to-high propagation delay times of any single channel. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN75970B SCSI DIFFERENTIAL CONVERTER-CONTROL SLLS323A – NOVEMBER 1999 – REVISED JANUARY 2000 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) PARAMETER tPHL tPLH Delay time, high- to low-level tdis Disable time ten Delay time, low- to high-level Enable time FROM (INPUT) TO (OUTPUT) TIMEOUT DRVBUS ABSY – BBSY ± ARST – BRST ± ASEL – BSEL ± TEST CONDITIONS See Figure 5 MIN TYP† MAX UNIT 200 ns 200 ns 200 See Figure 6 200 ns 200 ABSY – BBSY ± ARST – BRST ± ASEL – BSEL ± 39 40 See Figure 6 55 ns tdis1 tdis2 Disable time BRST ± ARST – 93 ns Disable time BSEL ± ASEL – 55 ns tdis3 ten1 Disable time BBSY ± ABSY – 60 ns Enable time BRST ± ARST – 63 ns ten2 ten3 Enable time BSEL ± ASEL – 45 ns Enable time BBSY ± ABSY – 45 ns BSEL ± ASEL – 92 ns ten4 Enable time † All typical values are at VCC = 5 V, TA = 25°C. POST OFFICE BOX 655303 See Figure 7 • DALLAS, TEXAS 75265 9 SN75970B SCSI DIFFERENTIAL CONVERTER-CONTROL SLLS323A – NOVEMBER 1999 – REVISED JANUARY 2000 PARAMETER MEASUREMENT INFORMATION 5V 165 Ω BDBn – 2 V or 0.8 V A– 75 Ω VOD VOH, VOL BDBn + VIH, VIL 165 Ω VOH, VOL NOTES: A. The input pulse is supplied by a generator having the following characteristics: tr ≤ 3 ns, tf ≤ 3 ns, PRR ≤ 1 MHz, 45% < duty cycle < 50%, ZO = 50 Ω. B. Resistance values are with a tolerance of 5%. C. All input voltage levels are held to within 0.01 V. Figure 1. Differential Driver VOD, VOH, and VOL Test Circuit BDBn – ADBn – II VID or VIT VI BDBn + IOH, IOL VOH, VOL Figure 2. Single-Ended Driver VOD, VOH, and VOL Test Circuit 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN75970B SCSI DIFFERENTIAL CONVERTER-CONTROL SLLS323A – NOVEMBER 1999 – REVISED JANUARY 2000 PARAMETER MEASUREMENT INFORMATION GND A S1 B+ IO 15 pF II Input (see Note A) A 165 Ω B 165 Ω 375 Ω VO VI 375 Ω 75 Ω VOD IO B– S2 VO 15 pF 5V (see Note B) RSTFLTR DSENS TEST RESET Input Output VOD(H) 0V VOD(L) 3V 1.5 V 0V t0 or t0 A– delay delay VOD td1 td2 NOTES: A. The input pulse is supplied by a generator having the following characteristics: tr ≤ 1 ns, tf ≤ 1 ns, PRR ≤ 1 MHz, 45% < duty cycle < 50%, ZO = 50 Ω. B. Resistance values are with a tolerance of ± 5%. C. All input voltage levels are held to within 0.01 V. Figure 3. A-Side to B-Side Propagation Delay Time Test Circuit and Timing Definitions POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SN75970B SCSI DIFFERENTIAL CONVERTER-CONTROL SLLS323A – NOVEMBER 1999 – REVISED JANUARY 2000 PARAMETER MEASUREMENT INFORMATION B– A– RSTFLTR 1.5 V Input (see Note A) B+ 15 pF (see Note B) Output DSENS TEST RESET Input Output VOH 1.5 V VOL 3V 1.5 V 0V t0 or t0 B– delay delay A– td3 td4 NOTES: A. The input pulse is supplied by a generator having the following characteristics: tr ≤ 1 ns, tf ≤ 1 ns PRR ≤ 1 MHz, 45% < duty cycle < 50%, ZO = 50 Ω. B. Resistance values are with a tolerance of ± 5%. C. All input voltage levels are held to within 0.01 V. Figure 4. B-Side to A-Side Propagation Delay Time Test Circuit and Timing Definitions Table 1. Output Test Enabling (No Clock Input) SIGNAL BUS CONTROL INPUT(s) INPUT(s) OUTPUT TEST RSTFLTR RESET ATN, ACK, MSG, C/D, REQ, I/O A B H H L ATN, ACK, MSG, C/D, REQ, I/O B A H L RST A B RST B A SEL, BSY B A L H L→H B H H L SEL, BSY TIMEOUT DRVBUS† N/A H L BBSY –/ BBSY+, BSEL–/BSEL+, TIMEOUT DRVBUS H POST OFFICE BOX 655303 BBSY+ ABSY– DSENS L→H H L H H L→H H L H H L L L TIMEOUT N/A Z H † For these conditions, DRVBUS = BSEL or BBSY and TIMEOUT together. 12 BBSY – • DALLAS, TEXAS 75265 L L H SN75970B SCSI DIFFERENTIAL CONVERTER-CONTROL SLLS323A – NOVEMBER 1999 – REVISED JANUARY 2000 PARAMETER MEASUREMENT INFORMATION DRVBUS TIMEOUT 15 pF Input RSTFLTR Output DSENS, BSEL, BBSY TEST Input Output VCC 1.5 V 0V RESET VOH 1.5 V VOL t0 or t0 TIMEOUT tP tP DRVBUS tPHL tPLH Figure 5. TIMEOUT to DRVBUS Delay Time Test Circuit and Timing Definitions POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 SN75970B SCSI DIFFERENTIAL CONVERTER-CONTROL SLLS323A – NOVEMBER 1999 – REVISED JANUARY 2000 PARAMETER MEASUREMENT INFORMATION 5V 165 Ω B– 15 pF A– 75 Ω Output Input B+ 165 Ω Input 15 pF Output 3V 1.5 V 0V 0.5 V VOD(H) ≈ – 0.925 V t0 or t0 enable disable RSTFLTR DSENS TEST RESET CLK20 (see Note A) ARST – ABSY – or ASEL – ten BRST tdis ten BBSY or BSEL tdis NOTE A: These are asynchronous events and do not necessarily align with clock edges. Figure 6. A-Side to B-Side Enable and Disable Delay Time Test Circuit and Timing Definitions 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN75970B SCSI DIFFERENTIAL CONVERTER-CONTROL SLLS323A – NOVEMBER 1999 – REVISED JANUARY 2000 PARAMETER MEASUREMENT INFORMATION B– Input 3V 1.5 V Output A– 1.5 V Input 0V t0 or B+ 15 pF Output VOH 1.5 V VOL t0 delay Reset delay Arbitration to Select 1 Bus Free RSTFLTR DSENS TEST RESET CLK40 (See Note A) BRST – BBSY – BSEL – ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ten1 tdis1 ARST – ABSY – ASEL – ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ten3 tdis3 ten2 tdis2 ten4 NOTE A: These are asynchronous events and do not necessarily align with clock edges. Figure 7. B-Side to A-Side Enable and Disable Delay Time Test Circuit and Timing Definitions POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 SN75970B SCSI DIFFERENTIAL CONVERTER-CONTROL SLLS323A – NOVEMBER 1999 – REVISED JANUARY 2000 APPLICATION INFORMATION To correctly set the direction of the SCSI bus signals, the SN75970B must follow the activity on the bus. An asynchronous, 5-state controller watches the state of all the bus control signals, sets the direction of each control signal as needed, and generates the DRVBUS and SDB outputs to control one or two external SN75971B SCSI differential converter-data devices. The controller never generates the data driven on a bus signal; it only enables the drivers. The clock input implements a 400-ns timer that is not part of the controller itself. Controller-state transitions occur immediately when all the transition conditions are met. Note that the frequency of the supplied clock, either 20 MHz or 40 MHz, must be correct in order to meet the SCSI specifications. As shown in Figure 8, after reset, the controller begins in the bus free state. In case the controller was attached to an active differential bus, it waits for the SCSI bus free condition, defined as when BBSY and BSEL are deasserted for 400 ns. While waiting for the SCSI bus free condition, the state of BBSY and BSEL passes through to the A side. The A side bus device cannot take part in bus activity during this condition before the SCSI bus free condition. Once SCSI bus free is detected, the SCSI arbitration state is entered. Both ABSY and BBSY are enabled; thus when either signal asserts, both drivers turn on and both signals remain asserted until this state is left. Normally the SCSI arbitration state ends after the winner of arbitration asserts BSEL. This would cause the controller to go to the select 1 state. However, when BSEL is not asserted, a timeout would eventually be detected and cause a reset of the controller. In the select 1 state two latches are open, DSEL_LATCH and RESEL_LATCH. The first latch captures the state of BSEL so that following states can determine whether the arbitration winner was on the A side or B side. 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN75970B SCSI DIFFERENTIAL CONVERTER-CONTROL SLLS323A – NOVEMBER 1999 – REVISED JANUARY 2000 APPLICATION INFORMATION NO Bus Free State RESET 400 ns of BBSY = BSEL = 0? Enable ABSY and ASEL SCSI Bus Free Condition YES A YES SCSI Arbitration State ASEL or (DSEL_LATCH and BSEL)? Enable ABSY and BBSY Set DSEL_LATCH to BSEL Set RESEL_LATCH to AI/O NO NO NO Set RESEL_LATCH to AI/O BBSY? YES YES TIMEOUT? DSEL_LATCH = 1? RESET NO YES Enable A Side Select 1 State NO Enable B Side 400 ns of BBSY = 0? 400 ns of ABSY = 0? YES NO YES YES NO ASEL = 1? NO ABSY = 1 And BBSY = 0? Select 2 State YES Continued on Figure 9 Figure 8. Bus Free, SCSI Arbitration, and Select 1 State Flow Chart The second latch captures the state of AI/O, this is true during a reselection phase but not during the selection phase. When the bus is in the selection or reselection phase, the controller enters the select 1 state. There are three possible flows depending on bus events. The first flow is that the SCSI controller on the A side won the arbitration and asserted ASEL. In this event DSEL_LATCH would not be set. The controller passes all signals to the B side and waits for ABSY to deassert for 400 ns, indicating that the A side controller is selecting or reselecting a device on the B side. The object of the A side controller must be on the B side since only one device is allowed on the A side. The second possible flow is that DSEL_LATCH is set, indicating that the arbitration winner is on the B side, and the winner is selecting or reselecting the device on the A side. The controller passes all signals to the A side and waits for BBSY to deassert for 400 ns. When the A side controller responds by asserting ABSY, the controller detects ABSY asserted and BBSY deasserts and goes to the select 2 state. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 SN75970B SCSI DIFFERENTIAL CONVERTER-CONTROL SLLS323A – NOVEMBER 1999 – REVISED JANUARY 2000 APPLICATION INFORMATION The third possible flow is that a device on the B side won the arbitration and is selecting or reselecting another device on the B side. DSEL_LATCH is set, and 400 ns of BBSY is asserted first by the object of the selection or reselection. Since ASEL is still asserted, the controller remains in the select 1 state throughout the selection or reselection. If the BBSY deassertion is missed by the timer, again the controller remains in the select 1 state. Once the transfer state is entered, BBSY is asserted and BSEL is dropped. This again returns the controller to a select 1 state. At the end of the transfer both BBSY and BSEL are deasserted. After the timer limit is reached, the controller goes to the arbitration state for the next bus arbitration. The controller enters the select 2 state (see Figure 9) during the selection or reselection phases when the initiator and terminator are on the opposite side of SDCC. In this state the RESEL_LATCH is closed, capturing the value of the I/O. When RESEL_LATCH is one, reselection is indicated. When RESEL_LATCH equals zero, a selection is indicated. RESEL_LATCH, along with the DSEL_LATCH, now defines which side the initiator is on and therefore what direction to establish for all the bus signals. The target must be on the other side; if both target and initiator were on the B side, the select 2 state would never be entered. When the RESEL_LATCH is zero, indicating a selection, the connection is not made. When DSEL_LATCH is one, the initiator is on the B side and the control lines it drives have their A side drivers enabled. These terminals are the initiator group of ACK and ATN along with SEL. The other terminals are driven by the target and have the B side drivers enabled. They are the target group of REQ, MSG, C/D, and I/O, along with BSY. When DSEL_LATCH is zero the connection is reversed. Since transfer states are not started, DRVBUS is set to 1, indicating that the data transceiver chips should not take their direction control from SDB and should be actively negated. SDB is generated from I/O and is the bus signal that determines data transfer direction. In this case it indicates the selection phase, the controller immediately transfers to the transfer state, where exactly the same actions are done. When the RESEL_LATCH is 1 indicating a reselection, there are one or more actions before information states can be entered. When the target reselects the initiator, the initiator responds by asserting BSY. Once the connection is made, the assertion of BSY must be changed over to the target, and the controller must reverse the BSY driver direction. It does this when SEL deasserts by transferring to the transfer state where the BSY direction is reversed. In the select 2 state all the control line directions are set as appropriate, except that DRVBUS is not yet asserted. In the transfer state DRBVUS is set as well. The controller remains in the transfer state during all other SCSI states. When a bus free state is detected, it goes back to the arbitration state to wait for the next activity. Note that after BBSY and BSEL deassert, the controller continues to actively drive the control lines and the data lines through DRVBUS until 400 ns of continuous deassertion is detected. The drivers are turned off only when the state change occurs. Figure 10 shows a typical system configuration. The timeout function used in the arbitration state is implemented with a resistor and capacitor connected to the TIMEOUT terminal. During reset and whenever the timer is not in use, the terminal is driven to VCC. The timer starts when the driver turns off, allowing the capacitor to charge and the TIMEOUT terminal to drop to ground. When VIT- is reached, the driver turns on, discharging the capacitor and returning TIMEOUT to VCC. A timeout event is declared after the driver turns back on and TIMEOUT exceeds VIT+. RST can be asserted on either the A or B side, and is driven to the other side. The drive to the other side is controlled by a bidirectional latch. When one side asserts, the other side is asserted and a latch is set to that direction. When the first side deasserts, the driver turns off, but the direction is held until both sides are deasserted. Only then can the direction change. 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN75970B SCSI DIFFERENTIAL CONVERTER-CONTROL SLLS323A – NOVEMBER 1999 – REVISED JANUARY 2000 APPLICATION INFORMATION Continued From Figure 8 Select 1 State YES YES DSEL_LATCH = 1? RESEL_LATCH = 1? NO Select 2 State Enable BBSY, BINIT, ASEL, And ATARG NO Enable ABSY, AINIT, BSEL, And BTARG YES DSEL_LATCH = 1? NO DRVBUS = 1 SDB = AI/O Enable BBSY, BTARG, ASEL, And AINIT YES BSEL = 1? NO YES DRVBUS = 1 SDB = BI/O Enable ABSY, ATARG, BSEL, And BINIT ASEL = 1? NO YES RESEL_LATCH = 1? DSEL_LATCH = 1? YES YES NO RESEL_LATCH = 1? NO Transfer State NO DRVBUS = 1, SDB = AI/O Enable BBSY, BTARG, ASEL, And AINIT DRVBUS = 1, SDB = BI/O Enable ABSY, ATARG, BSEL, And BINIT NO 400 ns of BBSY = BSEL = 0? YES A (On Figure 8) Figure 9. SCSI Select 1, Select 2, and Transfer State Flow Chart POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 SN75970B SCSI DIFFERENTIAL CONVERTER-CONTROL SLLS323A – NOVEMBER 1999 – REVISED JANUARY 2000 APPLICATION INFORMATION The SCSI bus signal RST does not directly clear SDCC internal logic. Instead, the RSTFLTR terminal can be connected as ARST – so that a bus reset clears SDCC. RSTFLTR clears the internal controller but does not clear the RST bidirectional latch. By connecting these terminal externally through a RC filter as shown in Figure 8, noise pulses on the bus may be filtered as recommended by the SCSI-2 specification. SN75970B 3 DIFFSENS ± BSY ± SEL ± RST ± I/O ± MSG ± C/D ± REQ ± ATN ± ACK DSENS BBSY± BSEL± RST± 6 BI/O± B MSG± BC/D± BREQ± 8 4 SCSI Controller A BSY– ASEL– AI/O– AMSG– AC/D– AREQ– AATN– AACK– 20 kΩ 1 RSTFLTR Test 4 – RST ARST – BATN± BACK± 7 8 – BSY – SEL – I/O – MSG – C/D – REQ – ATN – ACK CLK40 (see Note A) 1000 pF 2 RESET 55 X1/CLK20 RESET (From System) 20 MHz (see Note A) Optional (see Note B) X2 VCC 0.022 µF TIMEOUT 205 kΩ DRVBUS ± DB(7 – 0) ± DBP(0) 16 SDB SN75971B 8 2 – DBP(0) RESET DIFFSENS DRVBUS ± DB(15 – 8) ± DBP(1) – DB(7 – 0) 16 SDB SN75971B 8 2 – DB(15 – 8) – DBP(1) RESET DIFFSENS NOTES: A. When using the 40 MHz clock input, X1 must be connected to VCC. B. The oscillator cell of the SN75970B is for a series-resonant crystal and needs approximately 10 pF (including fixture capacitance) from X1 and X2 to ground in order to function. Figure 10. Typical Application of the SN75970B and SN75971B 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN75970B SCSI DIFFERENTIAL CONVERTER-CONTROL SLLS323A – NOVEMBER 1999 – REVISED JANUARY 2000 MECHANICAL INFORMATION DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PIN SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 SN75970B SCSI DIFFERENTIAL CONVERTER-CONTROL SLLS323A – NOVEMBER 1999 – REVISED JANUARY 2000 MECHANICAL INFORMATION DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PIN SHOWN PINS ** 28 48 56 A MAX 0.380 (9,65) 0.630 (16,00) 0.730 (18,54) A MIN 0.370 (9,40) 0.620 (15,75) 0.720 (18,29) DIM 0.025 (0,635) 0.012 (0,305) 0.008 (0,203) 48 0.005 (0,13) M 25 0.006 (0,15) NOM 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 0°– 8° 24 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.008 (0,20) MIN 0.004 (0,10) 4040048 / B 02/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 2000, Texas Instruments Incorporated