SLLS183 − AUGUST 1994 • • • • • • • Industrial Temperature Version of the TFB2022A With an Operating Range of −20°C to 85°C Parallel-Protocol Support Is Fully Compliant to Futurebus+ Standard (IEEE Std 896.1−1991) Interfaces Easily to a Variety of Popular Microprocessors Such as SPARC, 680x0, 88xxx, 80x86, and Alpha AXP Can Be Used in Conjunction With the TFB2002A Futurebus+ I/O Controller or Standalone With a User-Defined Controller 64 Data Channels and 8 Parity Channels on Board • • • • Supports 32 or 36 Bits of Addressing On-Board Address Decoding Determines Whether Transaction Is to Host Memory, Extended Unit Space, Message-Passing Mailbox, or Other CSR Location Parallel-Protocol-Related CSR Locations Are Provided on Chip Provides Support for Module Live Insertion Handles Both Packet and Compelled Transfers Capable of Buffering up to 256 Bytes Per Transaction description The TFB2022AI data path unit (DPU) is a member of the Texas Instruments Futurebus+ (FB+) chip set. This chip set provides an integrated approach to the Futurebus+ interface that reduces new-product design time, allows more functionality per circuit board, improves overall interface reliability, and reduces end-user down time through built-in test capabilities. The Futurebus+ chip set is capable of supporting 32- or 64-bit data widths in any combination on both the host-bus interface (HIF) and Futurebus+. The address width is programmable to be 32 bits or 36 bits (with either data width). The TFB2022AI may be used with a TFB2002B Futurebus+ I/O controller to provide a complete 64-bit Profile-B interface. It allows great flexibility in the design of the system and in the host features that may be supported. It may also be used with a user-defined controller to provide a variety of performance features. When used together, the TFB2022AI and TFB2002B provide the Futurebus+ and host-bus protocol control for the first 64 bits of data and 36 bits of address. The TFB2022AI contains a bidirectional FIFO for high-speed transmission of data in either compelled or packet mode, address control for 36 bits of address, and related CSR locations. All Profile-A- and Profile-B-required CSRs are implemented either on this device or the TFB2002B. The TFB2022AI is optimized for Profile-B modules. Several processors may reside on a single module with the DPU as long as they do not require the DPU/IOC to understand cache-coherent operation. The module may contain memory or I/O units in addition to processors. The TFB2022AI is best suited for I/O or memory modules. The MS<1:0> signals provide a preaddress decode mechanism, enabling the user to implement simplified decode logic in the logic interface. These signals indicate whether an access is being made to host memory, extended units space, host CSR space, or to a message mailbox. The TFB2022AI is offered in a 240-pin metal quad flat package (MFP). The TFB2022AI is characterized for operation over the industrial temperature range of − 20°C to 85°C. NOTE: To maintain consistency with the notation used in the Futurebus+ standard (IEEE Std 896.1−1991), an active-low signal is denoted herein by use of the trailing asterisk (*) on the signal name. SPARC is a trademark of Sun Microsystems, Inc. Alpha AXP is a trademark of Digital Equipment Corporation. Copyright 1994, Texas Instruments Incorporated ! "#$ %!& % "! "! '! ! !( ! %% )*& % "!+ %! !!$* $%! !+ $$ "!!& • DALLAS, TEXAS 75265 • HOUSTON, TEXAS 77251−1443 POST OFFICE BOX 655303 POST OFFICE BOX 1443 1 SLLS183 − AUGUST 1994 terminal assignments 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 HA10 HA9 HA8 HA7 HA6 Vcc HA5 HA4 HA3 HA2 HA1 HA0 GND TSIZE1 TSIZE0 HSTRB* HMODE2 HMODE1 HMODE0 HADEC3 Vcc HADEC2 HADEC1 HADEC0 HAS* HIP* DMAMODE DATAAV* SPACEAV* REFCLK GND NEWADDR* TR/W* DL1 DL0 DSACK1* DSACK0* FADEC3 FADEC2 FADEC1 Vcc FADEC0 FMODE2 FMODE1 FMODE0 FRD* FSTRB FACK SELECTED* BSTRDY* GND AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 ADPO MFP PACKAGE (TOP VIEW) 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 HDP2 HD24 HD25 HD26 Vcc HD27 HD28 HD29 HD30 HD31 HDP3 GND BSTAT0* BSTAT1* GND NC UNALIGNED* HBADLD* FIFORST* Vcc ERROR1 ERROR0 SYSRESET* BINIT* RST* HBMASTER* TDO TDI CLK GND TCK TMS MS1 MS0 CM5 CM6 CM7 STI3 STI5 Vcc GA0* DSI GA1* ASI GA2* DII GA3* DKI GA4* GND ADP7 AD63 AD62 AD61 AD60 AD59 AD58 AD57 AD56 Vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 HA11 GND HA12 HA13 HA14 HA15 HA16 HA17 Vcc HA18 HA19 HA20 HA21 HA22 HA23 GND HA24 HA25 HA26 HA27 HA28 HA29 Vcc HA30 HA31 HAP0 HAP1 HAP2 HAP3 GND HD0 HD1 HD2 HD3 HD4 HD5 Vcc HD6 HD7 HDP0 HD8 HD9 HD10 GND HD11 HD12 HD13 HD14 HD15 HDP1 Vcc HD16 HD17 HD18 HD19 HD20 HD21 GND HD22 HD23 NC − No internal connection 2 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • Vcc AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 ADP1 GND AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 ADP2 Vcc AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 ADP3 GND AD32 AD33 AD34 AD35 AD36 AD37 AD38 AD39 ADP4 Vcc AD40 AD41 AD42 AD43 AD44 AD45 AD46 AD47 ADP5 GND AD48 AD49 AD50 AD51 AD52 AD53 AD54 AD55 ADP6 SLLS183 − AUGUST 1994 Terminal Functions host interface TERMINAL I/O FROM/TO 14, 13 I Host interface Host-interface status: HH Normal HL Reserved LH Bus error LL Backoff/retry BSTRDY* 131 I Host interface Burst ready CLK 29 I Host interface Clock input. CLK is the processor clock for synchronous transactions on the host side. Up to 25 MHz is recommended. DL<1:0> 147, 146 I Host interface Host-interface data length: LL 64 bytes LH 32 bytes HL 16 bytes HH 8 bytes DSACK<1:0>* 145, 144 I Host interface Data acknowledge: Single mode (TBST* = high): LL Complete cycle, data bus port 32 LH Reserved HL Reserved HH Insert wait state NAME NO. BSTAT<1:0>* DESCRIPTION Burst mode (TBST* = low): LL Low speed, 32-bit burst capable LH HL HH High speed, 32-bit burst capable Low speed, 64-bit burst capable High speed, 64-bit burst capable HA<31:0> 205 −204, 202 −197, 195 −190, 188 −183, 181 −176, 174 −169 I/O Host interface Host-interface address or upper quadlet of data HAP<3:0> 209−206 I/O Host interface Extended host-interface address or parity for upper quadlet of host interface data 156 I Host interface Host-interface address strobe HD<31:0> 10 −6, 4 −2, 240 −239, 237 −232, 229 −225, 223 −221, 219 −218, 216 −211 I/O Host interface Lower quadlet of host-interface data HDP<3:0> 11, 1, 230, 220 I/O Host interface Parity for lower quadlet of host-interface data HIP* 155 I Host interface Host-interface transaction in progress TR/W* 148 I Host interface Host-interface read or write 167, 166 I/O Host interface Host-interface transaction size: LL Word (32 bits or greater) LH Byte (8 bits) HL Half word (16 bits) HH Three bytes (24 bits) HAS* TSIZE<1:0> • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 3 SLLS183 − AUGUST 1994 Terminal Functions other module interface signals TERMINAL NAME NO. I/O FROM/TO DESCRIPTION MS<1:0> 33, 34 O Module Memory decode of the host address: LL Unselected LH Host memory HL Host-unit space HH CSR space REFCLK 151 I Module Clock input. A 25-MHz, 50% ± 5% duty-cycle signal is recommended; any frequency between 25 MHz and 33 MHz and duty cycle of 50% ± 5% can be tolerated. REFCLK determines packet-mode transfer speed. interface to TFB2002A TERMINAL NAME DATAAV* DMAMODE NO. 153 I/O FROM/TO DESCRIPTION O TFB2002B IOC Data available in FIFO. In compelled mode, DATAAV* indicates if any data is in the FIFO. In packet or burst mode, DATAAV* indicates if a packet or burst data of length encoded on Futurebus+ packet size or the DL<1:0> lines is available. 154 I TFB2002B IOC DMA operation is occurring. FMODE and HMODE are modified for this function. ERROR<1:0> 21, 22 O TFB2002B IOC Futurebus+ error indicators: LL No error LH Futurebus+ parity error HL Packet longitudinal error HH Host-interface-data parity error FADEC<3:0> 143, 142, 141, 139 O TFB2002B IOC Futurebus+ address decode: LLLL Unselected LLLH Host memory LLHL Host-extended-unit space LLHH Host CSR LHLL Broadcast mailbox LHLH Reserved LHHL Reserved LHHH Reserved HLLL Mailbox address HLLH Packet-mode-capable memory address HLHL Reserved HLHH Reserved HHLL Reserved HHLH DPU CSR HHHL Broadcast CSR (non-DPU) HHHH Broadcast CSR (DPU) FIFORST* 19 I TFB2002B IOC FIFO reset. FIFORST* resets the FIFO pointers FACK 133 O TFB2002B IOC Futurebus+ acknowledge. Futurebus+ event complete 138, 137, 136 I TFB2002B IOC Futurebus+ mode. FMODE<2:0> indicates to the TFB2022AI what action is to be taken in the Futurebus+ interface: LLL Compelled-mode Futurebus+ LLH Packet-mode Futurebus+ LHL Partial transfer LHH Disconnect data for master write HLL Reserved HLH Reserved HHL Disconnect data for split requestor HHH Reserved FMODE<2:0> 4 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • SLLS183 − AUGUST 1994 Terminal Functions interface to TFB2002A (continued) TERMINAL NAME NO. I/O FROM/TO DESCRIPTION FRD* 135 I TFB2002B IOC Futurebus+ read/write indicator: L = read (move data from Futurebus+ to FIFO); H = write (move data from FIFO to Futurebus+) FSTRB 134 I TFB2002B IOC Futurebus+ strobe: perform next Futurebus+ event HADEC<3:0> 161, 159, 158, 157 O TFB2002B IOC Host address decode. Address decoding for the host-interface address: Slave encoding: Master encoding: LLLL Unselected LLLL Unselected LLLH Host memory LLLH Memory address compelled LLHL Host-unit space LLHL Maximum burst capable or extended unit space LLHH Host CSR LLHH Memory address 64-byte burst LHLL Broadcast mailbox LHLL 32-byte-memory-address capable LHLH Reserved LHLH 16-byte-memory-address capable LHHL Split response hit LHHL 8-byte-memory-address capable LHHH Futurebus+ CSR address LHHH Reserved HLLL Reserved HLLL Reserved HLLH Broadcast CSR address HLLH Reserved HLHL Reserved HLHL Reserved HLHH Reserved HLHH Reserved HHLL Reserved HHLL Reserved HHLH DPU CSR HHLH Reserved HHHL Reserved HHHL Reserved HHHH Reserved HHHH Reserved HBADLD* 18 I TFB2002B IOC Host address load. Futurebus+ has been granted for the requested transaction HBMASTER* 26 I TFB2002B IOC Host master. Indicates host-interface mastership HMODE<2:0> 164, 163, 162 I TFB2002B IOC Host mode. HMODE<2:0> indicates to the TFB2022AI what action is to be taken in the host interface: LLL Reserved LLH Between FIFO and host interface (single transfer), between TFB2022AI resident CSR and host interface, or between TFB2022AI resident CSR and FIFO LHL From FIFO to TFB2022AI resident CSR LHH Reserved HLL Reserved HLH Between FIFO and host bus (burst mode) HHL Reserved HHH Reserved HSTRB* 165 I TFB2002B IOC Host strobe. Perform next host-interface request as indicated in HMODE<2:0> NEWADDR* 149 I TFB2002B IOC New address. Increment address in the TFB2022AI address register SELECTED* 132 I TFB2002B IOC Module selected. Futurebus+ transaction uses this module. The DPU is used as a slave of the Futurebus+ transaction. SPACEAV* 152 O TFB2002B IOC Space available in FIFO. In compelled mode, SPACEAV* indicates that space is available in the FIFO for another transfer. In packet or burst mode, SPACEAV* indicates that space is available in the FIFO for another packet or burst. UNALIGNED* 17 O TFB2002 IOC FB+ slaved partial unaligned operation • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 5 SLLS183 − AUGUST 1994 Terminal Functions JTAG test port TERMINAL NAME NO. I/O FROM/TO DESCRIPTION I Module JTAG test clock TCK 31 TDI 28 I Module JTAG test data in TDO 27 O Module JTAG test data out TMS 32 I Module JTAG test-mode select I/O FROM/TO reset port TERMINAL NAME NO. DESCRIPTION BINIT* 24 I Module Bus interface reset. Signal indicating that a bus-interface reset is required RST* 25 I Module Module power-up reset. RST* resets all logic; output signals go to their inactive states, and 3-state outputs and bidirectional signals take on the high-impedance state. SYSRESET* 23 I Module System reset required. Signal indicating that a system reset is required Futurebus+ Interface TERMINAL NAME NO. I/O FROM/TO Futurebus+ DESCRIPTION AD<63:0> 52−59, 62−69, 72−79, 82−89, 92−99, 102−109, 112−119, 122−129 I/O ADP<7:0> 51, 61, 71, 81, 91, 101, 111, 121 I/O 44 I Futurebus+ Futurebus+ address synchronization strobe CM<7:5> 37, 36, 35 I Futurebus+ Futurebus+ command bits DSI, DKI, DII 42, 48, 46 I Futurebus+ Futurebus+ data path synchronization signals in: data strobe (DSI), data acknowledge (DKI), data acknowledge inverse (DII) GA<4:0> 49, 47, 45, 43, 41 I Futurebus+ Geographical address 39, 38 I Futurebus+ Futurebus+ status ASI STI5, STI3 6 Multiplexed Futurebus+ address and data Futurebus+ parity • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • SLLS183 − AUGUST 1994 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (at any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 W Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20°C to 85°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C Case temperature for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C NOTE 1: All voltage values are with respect to GND. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING MFP 6250 mW 50 mW/°C 4000 mW recommended operating conditions Supply voltage, VCC High-level input voltage, VIH MIN NOM MAX UNIT 4.75 5 5.25 V −0.5 VCC 0.8 V Low-level input voltage, VIL 2 Operating free-air temperature range, TA −20 85 °C V electrical characteristics over recommend operating free-air temperature range (unless otherwise noted) PARAMETER VIT VOH Input threshold voltage VOL VOH Low-level output voltage VOL VOH Low-level output voltage VOL VOH Low-level output voltage VOL VOH Low-level output voltage VOL Low-level output voltage MACRO IPI04LK High-level output voltage OPI43LK High-level output voltage OPI83LK High-level output voltage OPIH3LK High-level output voltage High-level output voltage OPJ43LK OPJ83LK TEST CONDITIONS VI = VCC or 0 V, IOH = − 4 mA II = ± 1 µA, MIN CL = 7.4 pF IOL = 4 mA IOH = − 8 mA TYP MAX 1.3 V 3.7 V 0.5 3.7 IOL = 8 mA IOH = − 12 mA 3.7 3.7 IOL = 4 mA IOH = − 8 mA 3.7 • V V 0.5 • V V 0.5 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 V V 0.5 IOL = 8 mA V V 0.5 IOL = 12 mA IOH = − 4 mA UNIT V 7 SLLS183 − AUGUST 1994 macros Table 1 lists the internal and external buffer macros used in the TFB2022AI design. To use this table, find the pin of interest and note the macro name(s). If there is an entry only in the input macro column, the pin is an input. If there is an entry only in the output macro column, the pin is an output. If there is an entry in both columns, this is a 3-state bidirectional pin. The macro(s) are also listed in the electrical characteristics table. Table 1. TFB2022AI (DPU) Pin Names and Macro Numbers PIN NAME INPUT MACRO OUTPUT MACRO AD<63:0> IPI04LK OPJ43LK ADP<7:0> IPI04LK OPJ43LK ASI INPUT MACRO OUTPUT MACRO HAP<3:0> IPI04LK OPJ83LK HAS* IPI04LK IPI04LK HBADLD* IPI04LK BINIT* IPI04LK HBMASTER* IPI04LK BSTAT<1:0>* IPI04LK HD<31:0> IPI04LK OPJ83LK BSTRDY* IPI04LK HDP<3:0> IPI04LK OPJ83LK CLK IPI04LK HIP* IPI04LK CM<7:5> IPI04LK HMODE<2:0> IPI04LK HSTRB* IPI04LK DATAAV* OPI43LK DII IPI04LK MS<1:0> DKI IPI04LK NEWADDR* IPI04LK DL<1:0> IPI04LK REFCLK IPI04LK DMAMODE IPI04LK RST* IPI04LK DSACK<1:0>* IPI04LK SELECTED* IPI04LK DSI OPI83LK IPI04LK SPACEAV* OPI43LK ERROR<1:0> OPI43LK STI<5,3> IPI04LK FACK OPI43LK SYSRESET* IPIO4LK OPI43LK FADEC<3:0> TCK IPI04LK FIFORST* IPI04LK TDI IPI04LK FMODE<2:0> IPI04LK TDO FRD* IPI04LK TMS IPI04LK FSTRB IPI04LK TR/ W* IPI04LK GA<4:0>* IPI04LK TSIZE<1:0> IPI04LK HA<31:0> IPI04LK HADEC<3:0> 8 PIN NAME OPJ83LK UNALIGNED* OPI43LK • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • OPI43LK OPIH3LK OPI43LK SLLS183 − AUGUST 1994 MECHANICAL DATA METAL QUAD (MQUAD ) CAVITY-UP FLATPACK MFP/S-MQFP-G240 180 121 120 181 0,23 TYP 0,50 TYP 3,30 TYP 0,13 TYP 61 240 0°−7° 0,25 MIN 1 60 0,60 0,40 29,50 TYP 31,72 SQ 31,56 34,80 SQ 34,40 Seating Plane 0,08 4,20 MAX NOTES: A. B. C. D. 4040007/A−10/93 All linear dimensions are in millimeters. This drawing is subject to change without notice. MQUAD is a registered trademark of Olin Corporation. This quad flat package consists of a circuit mounted on a leadframe and encased within an anodized aluminum shell. The package is intended for parts requiring either a lower stress environment or higher thermal dissipation capabilities than can be supplied by plastic. Ultrasonic cleaning of this package or boards with this package is not permitted. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 9 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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