ONSEMI NB3U23CMNTBG

NB3U23C
1.2 V Dual Channel CMOS
Buffer / Translator
Description
The NB3U23C is a 2−input, 2−output buffer/voltage translator for
UFS (Universal Flash Storage) in portable consumer applications such
as mobile phones, tablets, cameras, etc. This dual channel CMOS
buffer accepts 1.8 V CMOS input and translates it to 1.2 V CMOS
output. The device is powered using single supply of 1.2 V ±5%.
The NB3U23C is packaged in 2 ultra−small 6−pin packages: the 6
pin SC70 and a 6 pin thin DFN package.
Features
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MARKING
DIAGRAMS
6
SC−70
SQ SUFFIX
CASE 419B
1
Operating Frequency: 52 MHz (Max)
Propagation Delay: 5 ns (Max)
Low Standby Current: < 10 mA at 1.2 V VDD
Low Phase Noise Floor: −150 dBc/Hz (Typ)
Rise/Fall Times (tr/tf): 2 ns (Max)
ESD Protection Exceeds JEDEC Standards
♦ 2000 V Human−Body Model (JS−001−2012)
♦ 200 V Machine Model (JESD22−A115C)
♦ 1000 V Charged−Device Model (JESDC101E)
Operating Supply Voltage Range (VDD): 1.2 V ±5%
Operating Temperature Range (Industrial): −40°C to 85°C
This is a Pb−Free Device
23C M G
G
1
1
UDFN−6
MN SUFFIX
PRELIMINARY
23C
M
G
TBD M G
G
= Device Code
= Date Code*
= Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation and/or position may vary
depending upon manufacturing location.
VDD
5
IN1
1
IN2
3
1
2
6
OUT1
4
OUT2
2
GND
Figure 1. Simplified Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information on page 4 of
this data sheet.
© Semiconductor Components Industries, LLC, 2013
December, 2013 − Rev. 3
1
Publication Order Number:
NB3U23C/D
NB3U23C
IN1
GND
IN2
1
2
3
1
6
OUT1
GND
2
5
VDD
IN2
3
4
OUT2
VDD
5
SC70−6
Package
IN1
OUT1
6
OUT2
4
UDFN−6
Package
Figure 2. Pinout Diagram (Top Views)
Table 1. PIN DESCRIPTION
Number
Name
1
IN1
2
GND
Description
Input Clock Signal − Channel 1
Power Supply Ground (0 V)
3
IN2
4
OUT2
Input Clock Signal − Channel 2
Output − Channel 2
5
VDD
Power Supply Voltage
6
OUT1
Output − Channel 1
Table 2. ATTRIBUTES
Characteristic
ESD Protection
Value
Human Body Model
Machine Model
Charge Device Model
Moisture Sensitivity (Note 1)
Flammability Rating
2 kV min
200 V min
1 kV min
Level 1
Oxygen Index: 28 to 34
Transistor Count
UL 94 V−0 @ 0.125 in
120
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test II
1. For additional information, see Application Note AND8003/D.
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2
NB3U23C
Table 3. MAXIMUM RATINGS (Note 2)
Symbol
Parameter
Rating
Unit
3.6
V
–0.5 ≤ VI ≤ 2.5
V
25
mA
Operating Temperature Range, Industrial
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
°C/W
UDFN−6
210
126
TBD
SC70−6
UDFN−6
100
TBD
°C/W
260
°C
VDD
Supply Voltage
Vin
Input Voltage
ID
Output Current
TA
qJC
Thermal Resistance (Junction−to−Case)
Tsol
Wave Solder
Condition 1
0 lfpm
500 lfpm (Note 3)
(Note 3)
Condition 2
SC70−6
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simultaneously. If
stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected.
3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power).
Table 4. ELECTRICAL CHARACTERISTICS (VDD = 1.2 ±5% V, GND = 0 V, TA = −40°C to +85°C)
Symbol
Characteristic
Conditions
DIDD
Power Supply Current
(Single Channel Switching @ 52 MHz)
CL = 20 pF
CL = 5 pF
CL = 1 pF
2.5
1.5
1
Power Supply Current
(Both Channels Switching @ 52 MHz)
CL = 20 pF
CL = 5 pF
CL = 1 pF
5
3
2
Ioff
Standby Current
VIH
Input High Voltage
Min
Typ
Vi = VIH Max or GND;
VDD = 1.2 V, No Output Load
Max
Unit
mA
mA
10
mA
0.65 * VDD
1.98
V
VIL
Input Low Voltage
0
0.35 * VDD
V
VOH
Output High Voltage
CL = 20 pF
RL = 100 kW
0.75 * VDD
VDD
V
VOL
Output Low Voltage
CL = 20 pF
RL = 100 kW
0
0.25 * VDD
V
5
pF
0
52
MHz
5
ns
Cin
Input Capacitance
Fclk
Operating Frequency Range
tPD
Propagation Delay
INx to OUTx
CL = 20 pF, RL = 100 kW
Phase Noise Floor Density
(Notes 4 and 5)
CL = 20 pF
RL = 100 kW
−150
Additive RMS Phase Jitter
(Notes 5 and 6)
CL = 20 pF
RL = 100 kW
Offset Frequency Range:
50 kHz to 10 MHz
0.15
DC
Output Duty Cycle (Note 7)
Input Duty Cycle = 50%,
Min Input Slew Rate = 1 V/ns
tr/tf
Output Rise/Fall Times
0.2 * VDD to 0.8 * VDD
CL = 20 pF
RL = 100 kW
45
dBc/Hz
0.25
ps
55
%
2
ns
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. White noise floor.
5. This parameter refers to the random jitter only.
6. The output RMS phase jitter can be calculated using the following equation:
(Output RMS Phase Jitter)2 = (Input RMS Phase Jitter)2 + (Additive RMS Phase Jitter)2
7. Measured with input voltage swing from 0 V to 1.8 V.
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3
NB3U23C
INx
CL = 20 pF
OUTx
RL = 100 kW
GND
Figure 3. Typical Test Setup for Evaluation
0
−20
POWER (dBc/Hz)
−40
−60
−80
−100
−120
−140
−160
−180
1.00E+02 1.00E+03 1.00E+04 1.00E+05 1.00E+06 1.00E+07
OFFSET FREQUENCY (Hz)
Figure 4. Typical Phase Noise Plot at 50 MHz Carrier Frequency
ORDERING INFORMATION
Package
Shipping†
NB3U23CSQTCG
SC−70−6
(Pb−Free)
3000 / Tape & Reel
NB3U23CMNTBG
UDFN−6
(Pb−Free)
3000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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4
NB3U23C
PACKAGE DIMENSIONS
UDFN−6, 1.4 x 1.2, 0.5
CASE TBD
ISSUE O
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5
NB3U23C
PACKAGE DIMENSIONS
SC−88/SC70−6/SOT−363
CASE 419B−02
ISSUE Y
2X
aaa H D
D
A
D
6
5
GAGE
PLANE
4
2
L
L2
E1
E
1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.20 PER END.
4. DIMENSIONS D AND E1 AT THE OUTERMOST EXTREMES OF
THE PLASTIC BODY AND DATUM H.
5. DATUMS A AND B ARE DETERMINED AT DATUM H.
6. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE
LEAD BETWEEN 0.08 AND 0.15 FROM THE TIP.
7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN
EXCESS OF DIMENSION b AT MAXIMUM MATERIAL CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OF THE FOOT.
H
DETAIL A
3
aaa C
2X
bbb H D
2X 3 TIPS
e
B
6X
ddd
TOP VIEW
M
A2
A
6X
ccc C
DIM
A
A1
A2
b
C
D
E
E1
e
L
L2
aaa
bbb
ccc
ddd
b
A1
SIDE VIEW
C
C A-B D
DETAIL A
SEATING
PLANE
END VIEW
c
MILLIMETERS
MIN
NOM MAX
−−−
−−−
1.10
0.00
−−−
0.10
0.70
0.90
1.00
0.15
0.20
0.25
0.08
0.15
0.22
1.80
2.00
2.20
2.00
2.10
2.20
1.15
1.25
1.35
0.65 BSC
0.26
0.36
0.46
0.15 BSC
0.15
0.30
0.10
0.10
INCHES
MIN
NOM MAX
−−−
−−− 0.043
0.000
−−− 0.004
0.027 0.035 0.039
0.006 0.008 0.010
0.003 0.006 0.009
0.070 0.078 0.086
0.078 0.082 0.086
0.045 0.049 0.053
0.026 BSC
0.010 0.014 0.018
0.006 BSC
0.006
0.012
0.004
0.004
RECOMMENDED
SOLDERING FOOTPRINT*
6X
6X
0.30
0.66
2.50
0.65
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
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any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
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PUBLICATION ORDERING INFORMATION
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ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NB3U23C/D