ONSEMI NCP51190

NCP51190
1.5A DDR Memory
Termination Regulator
The NCP51190 is a simple, cost−effective, high−speed linear
regulator designed to generate the VTT termination voltage rail for
DDR−I, DDR−II and DDR−III memory. The regulator is capable of
actively sourcing or sinking up to ±1.5 A for DDR−I, or up to ±0.5 A
for DDR−II /−III while regulating the output voltage to within
±30 mV.
The output termination voltage is tightly regulated to track VTT =
(VDDQ / 2) over the entire current range.
The NCP51190 incorporates a high−speed differential amplifier to
provide ultra−fast response to line and load transients. Other features
include extremely low initial offset voltage, excellent load regulation,
source/sink soft−start and on−chip thermal shut−down protection.
The NCP51190 features the power−saving Suspend To Ram (STR)
function which will tri−state the regulator output and lower the
quiescent current drawn when the /SS pin is pulled low.
The NCP51190 is available in a DFN8 package.
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MARKING
DIAGRAM
DFN8
MN SUFFIX
CASE 506AA
Generate DDR Memory Termination Voltage (VTT)
For DDR−I, DDR−II, DDR−III Source / Sink Currents
Supports DDR−I to ±1.5 A, DDR−II, DDR−III to ±0.5 A (peak)
Integrated Power MOSFETs with Thermal Protection
Stable with 10 mF Ceramic VTT Capacitor
High Accuracy Output Voltage at Full−Load
Minimal External Component Count
Shutdown for Standby or Suspend to RAM (STR) mode
Built−in Soft Start
These are Pb−Free Devices
Appications
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A5
M
G
May, 2013 − Rev. 0
= Specific Device Code
= Date Code
= Pb−Free Device
(Note: Microdot may be in either location)
PIN CONNECTION
ORDERING INFORMATION
Device
NCP51190MNTAG
Package
Shipping†
DFN8
3000 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Desktop PC’s, Notebooks, and Workstations
Graphics Card DDR Memory Termination
Set Top Boxes, Digital TV’s, Printers
Embedded Systems
Active Bus Termination
© Semiconductor Components Industries, LLC, 2013
A5MG
G
1
Features
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1
1
Publication Order Number:
NCP51190/D
NCP51190
1.5 A, DDR−I /−II /−III TERMINATION REGULATOR
Figure 1. Typical Application Schematic
PIN FUNCTION DESCRIPTION – NCP51190
Pin Number
Pin Name
Pin Function
1
PVCC
The PVCC pin provides the rail voltage from where the VTT pin draws load current. There is a limitation
between VCC and PVCC. The PVCC voltage must be less or equal to the VCC voltage to ensure the
correct output voltage regulation. The VTT source current capability is dependent on PVCC voltage. The
higher the voltage on PVCC, the higher the source current.
2
VTT
Regulator output voltage capable of sinking and sourcing current while regulating the output rail.
3
GND
Common Ground.
4
/SS
Suspend Shutdown supports Suspend To RAM function. CMOS compatible input sets VTT output to
high impedance state. Logic HI = Enable, Logic LO = Shutdown.
5
VTTS
VTTS is the VTT sense input.
6
VREF
VREF is an output pin that provides the buffered output of the internal reference voltage equal to half of
VDDQ. Two resistors dividing down the VDDQ voltage on the pin to create the regulated output voltage.
7
VDDQ
The VDDQ pin is an input pin for creating the internal reference voltage to regulate VTT. The VDDQ
voltage is connected to an internal resistor divider. The central tap of resistor divider (VDDQ /2) is connected to the internal voltage buffer, which output is connected to VREF pin and the non−inverting input
of the error amplifier as the reference voltage.
8
VCC
THERMAL
PAD
Power for the analog control circuitry.
Pad for thermal connection. The exposed pad must be connected to the ground plane using multiple
vias for maximum power dissipation performance.
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2
NCP51190
ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
Value
Unit
−0.3 to +6
V
Tstg
−65 to +150
°C
TJ
−40 to +125
°C
RqJA
TBD
°C/W
ESD Capability, Human Body Model (Note 2)
ESDHBM
2000
V
ESD Capability, Machine Model (Note 2)
ESDMM
150
V
VCC, PVCC ,VDDQ, /SS to GND (Note 1)
Storage Temperature
Operating Junction Temperature Range
Thermal Characteristics, SO8−EP Thermal Resistance, Junction−to−Air
Power Rating at 25°C ambient
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. No pin to exceed VCC. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection and is tested by the following method:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)
Latchup Current Maximum Rating tested per JEDEC standard: JESD78.
RECOMMENED OPERATING CONDITIONS
Rating
Symbol
Value
Unit
VCC
2.2 to 5.5
V
Bias Supply Voltage
PVCC
1.5 to 2.5
V
Reference Input Voltage
VDDQ
1.35 to 2.7
V
Input Voltage
ELECTRICAL CHARACTERISTICS
−40°C ≤ TJ ≤ 125°C; VCC = PVCC = VDDQ = 2.5 V; unless otherwise noted. Typical values are at TJ = +25°C
Parameter
Condition
Symbol
Min
Typ
Max
Unit
Reference Voltage (DDR I)
IREF = 0 mA (unloaded)
PVCC = VDDQ
= 2.3 V
= 2.5 V
= 2.7 V
VREF
(DDR−I)
1.125
1.225
1.325
1.151
1.251
1.351
1.175
1.275
1.375
V
Reference Voltage (DDR II)
IREF = 0 mA (unloaded)
PVCC = VDDQ
= 1.7 V
= 1.8 V
= 1.9 V
VREF
(DDR−II)
0.830
0.880
0.925
0.851
0.901
0.951
0.880
0.930
0.975
V
Reference Voltage (DDR III)
IREF = 0 mA (unloaded)
PVCC = VDDQ
= 1.35 V
= 1.5 V
= 1.6 V
VREF
(DDR−III)
0.660
0.735
0.785
0.676
0.751
0.801
0.695
0.770
0.820
V
VREF − Output Impedance
IREF = −30 mA to +30 mA
ZREF
VTT Output Voltage
(DDR−I)
IOUT = 0 A
PVCC = VDDQ = 2.3 V
PVCC = VDDQ = 2.5 V
PVCC = VDDQ = 2.7 V
VTT
(DDR−I)
−
1.112
1.202
1.312
−
1.150
1.250
1.350
−
1.182
1.282
1.382
IOUT = +1.5 A
PVCC = VDDQ = 2.3V
PVCC = VDDQ = 2.5V
PVCC = VDDQ = 2.7V
VTT
(DDR−I)
−
1.115
1.215
1.315
−
1.150
1.250
1.350
−
1.185
1.285
1.385
IOUT = −1.5 A
PVCC = VDDQ = 2.3V
PVCC = VDDQ = 2.5V
PVCC = VDDQ = 2.7V
VTT
(DDR−I)
−
1.117
1.217
1.317
−
1.150
1.250
1.350
−
1.182
1.282
1.382
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3
2.5
kW
V
NCP51190
ELECTRICAL CHARACTERISTICS
−40°C ≤ TJ ≤ 125°C; VCC = PVCC = VDDQ = 2.5 V; unless otherwise noted. Typical values are at TJ = +25°C
Parameter
VTT Output Voltage
(DDR−II)
VTT Output Voltage
(DDR−III)
VTT Output Offset Voltage
Quiescent Current
Condition
Symbol
Min
Typ
Max
IOUT = 0 A
PVCC = VDDQ = 1.7 V
PVCC = VDDQ = 1.8 V
PVCC = VDDQ = 1.9 V
VTT
(DDR−II)
−
0.816
0.866
0.916
−
0.850
0.900
0.950
−
0.881
0.931
0.981
IOUT = +0.5 A
PVCC = VDDQ = 1.7 V
PVCC = VDDQ = 1.8 V
PVCC = VDDQ = 1.9 V
VTT
(DDR−II)
−
0.815
0.863
0.914
−
0.851
0.900
0.950
−
0.885
0.933
0.984
IOUT = −0.5 A
PVCC = VDDQ = 1.7 V
PVCC = VDDQ = 1.8 V
PVCC = VDDQ = 1.9 V
VTT
(DDR−II)
−
0.814
0.862
0.913
−
0.850
0.900
0.950
−
0.884
0.932
0.983
IOUT = 0 A
PVCC = VDDQ = 1.35 V
PVCC = VDDQ = 1.5 V
PVCC = VDDQ = 1.6 V
VTT
(DDR−III)
−
0.650
0.725
0.775
−
0.675
0.750
0.800
−
0.700
0.775
0.825
IOUT = +0.2 A,
PVCC = VDDQ = 1.35 V
IOUT = −0.2 A,
PVCC = VDDQ = 1.35 V
VTT
(DDR−III)
−
0.649
−
0.640
−
0.675
−
0.675
−
0.700
−
0.700
IOUT = +0.4 A,
PVCC = VDDQ = 1.5 V
IOUT = −0.4 A,
PVCC = VDDQ = 1.5 V
VTT
(DDR−III)
−
0.722
−
0.725
−
0.751
−
0.750
−
0.776
−
0.774
IOUT = +0.5 A,
PVCC = VDDQ = 1.6 V
IOUT = −0.5 A,
PVCC = VDDQ = 1.6 V
VTT
(DDR−III)
−
0.773
−
0.775
−
0.801
−
0.800
−
0.827
−
0.824
IOUT = ±1.5 A,
PVCC = VDDQ = 2.5 V
VOS
(DDR−I)
−30
0
+30
IOUT = ±0.5A,
PVCC = VDDQ = 1.8V
VOS
(DDR−II)
−30
0
+30
IOUT = ±0.5A,
PVCC = VDDQ = 1.5V
VOS
(DDR−III)
−30
0
+30
IQ
380
500
ZVDDQ
100
IOUT = 0 A
VDDQ Input Impedance
Unit
V
V
mV
mA
kW
/SS Leakage Current
/SS = 0 V
IL_SS
2
5
mA
Quiescent Current in Suspend Shutdown
/SS = 0 V
IQ_SS
115
150
mA
Suspend Shutdown Threshold
VIH
1.9
VIL
VTT leakage Current in Suspend Shutdown
/SS = 0 V, VTT = 1.25 V
0.8
IL_VTT
1
VTTS Current
ITTS
13
nA
Thermal Shutdown Temperature
TSD
165
°C
Thermal Shutdown Hysteresis
TSH
10
°C
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4
10
V
mA
NCP51190
700
120
600
100
500
80
400
60
300
40
200
20
100
0
SS (V)
Iq (mA)
140
2
3
4
5
0
6
4
5
Figure 2. IqSD vs. VCC
Figure 3. Iq vs. VCC
3.0
3.0
2.5
2.5
2.0
2.0
1.0
1.0
0.5
3
4
5
0
6
0
1
2
3
4
5
VCC (V)
VDDQ (V)
Figure 4. VIH and VIL
Figure 5. VREF vs. VDDQ
3.0
6
1.5
1.5
2
3
VCC (V)
3.5
0.5
2
VCC (V)
VREF (V)
IqSD (mA)
TYPICAL PERFORMANCE CHARACTERISTICS
6
160
140
2.5
120
IqSD (mA)
VTT (V)
2.0
1.5
1.0
100
80
60
−40°C
25°C
85°C
125°C
40
0.5
0
20
0
1
2
3
4
5
0
6
2
3
4
5
VDDQ (V)
VCC (V)
Figure 6. VTT vs. VDDQ
Figure 7. IqSD vs. VCC over Temperature
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5
6
NCP51190
TYPICAL PERFORMANCE CHARACTERISTICS
800
700
600
Iq (mA)
500
400
300
−40°C
25°C
85°C
125°C
200
100
0
2
3
4
5
VCC (V)
Figure 8. Iq vs. VCC over Temperature
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6
6
NCP51190
General
NCP51190, then any long traces will generate a significant
IR drop resulting in a sagging termination voltage at one end
of the bus than the other. The VTTS pin can be used to
improve performance by connecting it to the middle of the
bus. This will provide better power distribution across the
entire termination bus. If remote load regulation is not used,
then the VTTS pin must still be connected to VTT. Care
should be taken when a long VTTS trace is implemented in
close proximity to the memory. Noise pickup in the VTTS
trace can cause problems with precise regulation of VTT. A
small 0.1 mF ceramic capacitor placed next to the VTTS pin
can help filter out any high frequency noise and thereby
keeping the VTT power rail in spec.
The NCP51190 is a bus termination, linear regulator
designed to meet the JEDEC requirements for DDR−I,
DDR−II and DDR−III memory termination. The NCP51190
is capable of sourcing and sinking current while accurately
tracking and regulating the VTT output voltage equal to
(VDDQ / 2). The output stage has been designed to maintain
excellent load regulation and preventing shoot−through.
The NCP51190 uses two distinct power rails to separate the
analog circuitry from the power output stage and decrease
internal power dissipation.
Supply Voltage Inputs
For added flexibility, separate input pins (VCC and PVCC)
are provided for each required supply input. VCC is used to
supply all the internal control circuitry and PVCC is used
exclusively to provide the rail voltage for the output stage
used to create VTT. These pins have the capability to work
off separate supplies with the condition that VCC is always
greater than or equal to PVCC, and should always be used
with either a 1.8 V or 2.5 V rail. If the junction temperature
exceeds the thermal shutdown threshold, the part will enter
a shutdown state identical to the manual shutdown where
VTT is tri−stated and VREF remains active. Lower voltage
rails, such as 1.5 V can be used but will reduce the maximum
available output current.
Regulator Shutdown Function
The NCP51190 contains an active low enable pin (/SS)
that can be used for suspend to RAM functionality. In this
condition the VTT output will tri−state, with the VREF
output remaining active in order to provide a constant
reference signal for the memory and chipset. During
shutdown, VTT should not be exposed to voltages that
exceed PVCC.
With the enable pin asserted low the quiescent current of
the NCP51190 will drop, however the VDDQ input pin will
always draw a constant current due to the integrated 100 kW
impedance used for generating the internal reference.
Therefore, to calculate the total power loss in shutdown,
both currents need to be considered. The enable pin also has
an internal pull−up current. Therefore, to turn the part on, the
enable pin can either be connected to VCC or left open.
Generation of Internal Voltage Reference
VDDQ is the input used to create the internal reference
voltage for regulating VTT. The reference voltage is
generated from a resistor divider of two internal 50 kW
resistors. This guarantees that VTT will precisely track
(VDDQ / 2). The optimal implementation of the VDDQ input
pin is as a remote sense. This can be achieved by connecting
VDDQ directly to the 1.8 V rail at the DIMM memory
module instead of connecting it to PVCC. This ensures that
the reference voltage precisely tracks the DDR memory
power rail without introducing a large voltage drop due to
power traces. For DDR−II applications the VDDQ input will
be 1.8 V, which will create a (VDDQ / 2) = 0.9 V termination
voltage at the VTT output.
VREF provides a buffered output of the internal reference
voltage (VDDQ / 2). For improved performance, an output
bypass capacitor can be placed, close to the pin, to help
reduce any potential stray noise. A ceramic capacitor in the
range of 0.01 mF to 0.1 mF is recommended. The VREF output
remains active during the shutdown state and thermal
shutdown events for the suspend to RAM functionality.
Termination Voltage Output Regulation
VTT is the regulated output that is used to terminate the
bus resistors. It is capable of sourcing and sinking current
while regulating the output precisely to VDDQ / 2. The
NCP51190 is designed to handle continuous currents of up
to ±1.5 A with excellent load regulation. If a transient is
expected to last above the maximum continuous current
rating for a significant amount of time, then the bulk output
capacitor should be sized large enough to prevent an
excessive voltage drop.
Thermal Shutdown with Hysteresis
If the NCP51190 is to operate in elevated temperatures for
long durations, care should be taken to ensure that the
maximum operating junction temperature is not exceeded.
To guarantee safe operation, the NCP51190 provides
on−chip thermal shutdown protection. When the chip
junction temperature exceeds 165°C (typical) the part will
shutdown. When the junction temperature falls back to
155°C (typical) the device resumes normal operation. If the
junction temperature exceeds the thermal shutdown
threshold, VTT will tri−state until the part returns below the
temperature hysteresis trip−point.
Remote Voltage Feedback Sensing
The purpose of the VTTS sense pin is to provide improved
remote load regulation. In most motherboard applications,
the termination resistors will connect to VTT in a long plane.
If the output voltage was regulated only at the output of the
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7
NCP51190
PACKAGE DIMENSIONS
DFN8 2x2, 0.5P
CASE 506AA
ISSUE E
D
0.10 C
2X
0.10 C
DETAIL A
E
OPTIONAL
CONSTRUCTIONS
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
ÉÉ
ÉÉ
EXPOSED Cu
TOP VIEW
A
DETAIL B
0.10 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994 .
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.20 MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L
L
L1
ÇÇ
ÇÇ
PIN ONE
REFERENCE
2X
A
B
MOLD CMPD
DETAIL B
OPTIONAL
CONSTRUCTION
0.08 C
(A3)
NOTE 4
SIDE VIEW
DETAIL A
A1
D2
1
4
C
8X
SEATING
PLANE
RECOMMENDED
SOLDERING FOOTPRINT*
L
8
5
e/2
e
8X
1.30
PACKAGE
OUTLINE
E2
K
0.90
b
8X
0.50
2.30
1
0.10 C A B
0.05 C
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.20
0.30
2.00 BSC
1.10
1.30
2.00 BSC
0.70
0.90
0.50 BSC
0.30 REF
0.25
0.35
−−−
0.10
8X
0.30
NOTE 3
BOTTOM VIEW
0.50
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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NCP51190/D