DDR Termination Regulator TJ2997 FEATURES z z z z z z z z Source and sink current Low output voltage offset No external resistors required Linear topology Suspend to Ram (STR) functionality Low external component count Thermal Shutdown Available in SOP8, SOP8-PP Packages SOP8 / SOP8-PP PKG ORDERING INFORMATION APPLICATION Device z DDR -II and -III Termination Voltage z SSTL Termination z HSTL Termination Package TJ2997GD SOP8 TJ2997GDP SOP8-PP DESCRIPSION The TJ2997 linear regulator is designed to meet the JEDEC SSTL specifications for termination of DDRSDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering up to 1.5A continuous current and transient peaks up to 3A with respect to PVIN operating condition in the application as required for DDRSDRAM termination. The TJ2997 also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DIMMs. An additional feature found on the TJ2997 is an active high enable (EN) pin that provides Suspend To RAM (STR) functionality. When EN is pulled low the VTT output will tri-state providing a high impedance output, but, VREF will remain active. A power savings advantage can be obtained in this mode through lower quiescent current. Absolute Maximum Ratings CHARACTERISTIC SYMBOL MIN. MAX. UNIT Supply Voltage to GND PVIN AVIN VDDQ -0.3 -0.3 -0.3 6.0 6.0 6.0 V Lead Temperature (Soldering, 10 sec) TSOL 260 ℃ Storage Temperature Range TSTG -65 150 ℃ Operating Junction Temperature Range TJOPR -40 125 ℃ SYMBOL MIN. MAX. UNIT AVIN 2.3 5.5 V PVIN & EN 0 AVIN V Recommended Operation Range CHARACTERISTIC AVIN to GND PVIN & EN to GND Ordering Information Package Order No. SOP8 TJ2997GD SOP8-PP TJ2997GDP Apr, 2011 - R1.0.1 Description Package Marking Supplied As DDR Termination Regulator TJ2997G Reel DDR Termination Regulator TJ2997G Reel 1/13 HTC DDR Termination Regulator TJ2997 PIN CONFIGURATION GND 1 8 VTT GND 1 EN 2 7 PVIN EN 2 VSENSE 3 6 AVIN VSENSE 3 VREF 4 5 VDDQ 8 VTT Exposed Thermal 7 PVIN PAD 6 AVIN VREF 4 5 VDDQ SOP8 SOP8-PP PIN DESCRIPTION Pin No. Pin Name Pin Function 1 GND Ground 2 EN Enable 3 VSENSE 4 VREF Buffered Internal Reference Voltage of VDDQ/2 5 VDDQ Input for Internal Reference Equal to VDDQ/2 6 AVIN Analog Bias Input Pin 7 PVIN Power Input Pin 8 VTT Output Voltage for Connection to Termination Resistors Feedback Pin for Regulating VTT Exposed Thermal PAD Exposed Thermal Connection. Connect to Ground. (SOP8-PP Only) TYPICAL APPLICATION EN VEN VREF = 0.9V VREF + VDDQ = 1.8V VDDQ VAVIN = 2.5V AVIN PVIN 47uF Apr, 2011 - R1.0.1 + 0.1uF VSENSE GND 2/13 VTT VTT = 0.9V + 220uF HTC DDR Termination Regulator TJ2997 ELECTRICAL CHARACTERISTICS (1) (1), (2), (3) Specifications with standard typeface are for TJ = 25˚. Unless otherwise specified, AVIN = 2.5V, PVIN = VDDQ = 1.8V (1), (2), (3) DDRⅡ. AVIN = 2.5V, PVIN = VDDQ = 1.5V for DDRⅢ. PARAMETER SYMBOL TEST CONDITION for MIN. TYP. MAX. UNIT VREF Voltage VREF VDDQ = 1.8V 0.882 0.90 0.918 V VREF Voltage VREF VDDQ = 1.5V 0.735 0.75 0.765 V 0.86 0.90 0.94 0.86 0.90 0.94 0.71 0.75 0.79 0.71 0.75 0.79 0.71 0.75 0.79 -25 -25 -25 0 0 0 25 25 25 mV - 250 500 uA - 100 - kΩ VTT Output Voltage VTT VTT Output Voltage VTT IOUT = 0 A VDDQ = 1.8V, PVIN = 1.8V IOUT = 0 A @ VDDQ = 1.5V, PVIN = 1.5V IOUT = ± 0.5 A (6) @ VDDQ = 1.5V, PVIN = 1.5V (6) IOUT = ± 0.9A @ VDDQ = 1.5V, PVIN = 1.8V IOUT = 0 A VTT Output Voltage Offset VOSVTT (6) IOUT = ± 0.5 A IOUT = ± 0.9 A (6) (if applicable) Quiescent Current (4) IQ VDDQ Input Impedance IOUT = 0A ZVDDQ Quiescent Current in Shutdown(4) V (6) IOUT = ± 0.9 A VDDQ = 1.8V, PVIN = 1.8V V ISD EN = 0V 150 300 uA Shutdown Leakage Current IQ_SD EN = 0V 0.1 0.5 uA Minimum Enable High Level VIH 1.9 (7) - - V Maximum Enable Low Level VIL - - 0.6 V VTT Leakage Current in Shutdown IV 1 10 uA EN= 0V, VTT = 1.25V VSENSE Input Current ISENSE - - 0.1 uA Thermal Shutdown(5) TSD - 165 - ℃ Note 1. Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating range indicates conditions for which the device is intended to be functional, but does not guarantee specific performance limits. For guaranteed specifications and test conditions see Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2. At elevated temperatures, devices must be derated based on thermal resistance. The device in the SOP8 package must be derated at θJA = 165˚ C/W junction to ambient with no heat sink. Note 3. Limits are 100% production tested at 25˚C. Limits over the operating temperature range are guaranteed through correlation. Note 4. Quiescent current defined as the current flow into AVIN. Note 5. The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(MAX), the junction to ambient thermal resistance, θJA, and the ambient temperature, TA. Exceeding the maximum allowable power dissipation will cause excessive die temperature and the regulator will go into thermal shutdown. Note 6. VTT load regulation is tested by using a 10 ms current pulse and measuring VTT. Note 7. In the case of AVIN > 2.5V, minimum enable high level is AVIN * 0.7. Apr, 2011 - R1.0.1 3/13 HTC DDR Termination Regulator TJ2997 TYPICAL OPERATING CHARACTERISTICS T.B.D. Apr, 2011 - R1.0.1 4/13 HTC DDR Termination Regulator TJ2997 DESCRIPTION The TJ2997 is a linear bus termination regulator designed for DDR II and DDR III memories. The output, VTT is capable of sinking and sourcing current while regulating the output voltage equal to VDDQ / 2. The output stage has been designed to maintain excellent load regulation while preventing shoot through. The TJ2997 also incorporates two distinct power rails that separate the analog circuitry from the power output stage. This allows a split rail approach to be utilized to decrease internal power dissipation. It also permits the TJ2997 to provide a termination solution for the next generation of DDR-SDRAM memory.. Series Stub Termination Logic (SSTL) was created to improve signal integrity of the data transmission across the memory bus. This termination scheme is essential to prevent data error from signal reflections while transmitting at high frequencies encountered with DDR-SDRAM. The most common form of termination is Class II single parallel termination. This involves one RS series resistor from the chipset to the memory and one RT termination resistor. Typical values for RS and RT are 25 Ohms, although these can be changed to scale the current requirements from the TJ2997. This implementation can be seen below in Figure 1. FIGURE 1. SSTL-Termination Scheme PIN DESCRIPTION AVIN AND PVIN AVIN and PVIN are the input supply pins for the TJ2997. AVIN is used to supply all the internal control circuitry. PVIN, however, is used exclusively to provide the rail voltage for the output stage used to create VTT. These pins have the capability to work off separate supplies depending on the application. Higher voltages on PVIN will increase the maximum continuous output current because of output RDSON limitations at voltages close to VTT. The disadvantage of high values of PVIN is that the internal power loss will also increase, thermally limiting the design. The limitation on input voltage selection is that PVIN must be equal to or lower than AVIN. It is recommended to connect PVIN to voltage rails equal to or less than 3.3V to prevent the thermal limit from tripping because of excessive internal power dissipation. If the junction temperature exceeds the thermal shutdown then the part will enter a shutdown state where both VTT and VREF are tri-stated. VDDQ VDDQ is the input used to create the internal reference voltage for regulating VTT. The reference voltage is generated from a resistor divider of two internal 50kΩ resistors. This guarantees that VTT will track VDDQ / 2 precisely. The optimal implementation of VDDQ is as a remote sense. This can be Apr, 2011 - R1.0.1 5/13 HTC DDR Termination Regulator TJ2997 achieved by connecting VDDQ directly to the 2.5V rail at the DIMM instead of AVIN and PVIN. This ensures that the reference voltage tracks the DDR memory rails precisely without a large voltage drop from the power lines. VSENSE The purpose of the sense pin is to provide improved remote load regulation. In most motherboard applications the termination resistors will connect to VTT in a long plane. If the output voltage was regulated only at the output of the TJ2997 then the long trace will cause a significant IR drop resulting in a termination voltage lower at one end of the bus than the other. The VSENSE pin can be used to improve this performance, by connecting it to the middle of the bus. This will provide a better distribution across the entire termination bus. If remote load regulation is not used then the VSENSE pin must still be connected to VTT. Care should be taken when a long VSENSE trace is implemented in close proximity to the memory. Noise pickup in the VSENSE trace can cause problems with precise regulation of VTT. A small 0.1uF ceramic capacitor placed next to the VSENSE pin can help filter any high frequency signals and preventing errors. ENABLE The TJ2997 contains an active high enable pin that can be used to tri-state VTT. During shutdown VTT should not be exposed to voltages that exceed AVIN. With the enable pin asserted low the quiescent current of the TJ2997 will drop, however, VDDQ will always maintain its constant impedance of 100kΩ for generating the internal reference. Therefore to calculate the total power loss in shutdown both currents need to be considered. For more information refer to the Thermal Dissipation section. VREF VREF provides the buffered output of the internal reference voltage VDDQ / 2. This output should be used to provide the reference voltage for the Northbridge chipset and memory. Since these inputs are typically extremely high impedance, there should be little current drawn from VREF. For improved performance, an output bypass capacitor can be used, located close to the pin, to help with noise. A ceramic capacitor in the range of 0.1 µF to 0.01 µF is recommended. This output remains active during the shutdown state for the suspend to RAM functionality. VTT VTT is the regulated output that is used to terminate the bus resistors. It is capable of sinking and sourcing current while regulating the output precisely to VDDQ / 2. The TJ2997 is designed to handle peak transient currents of up to ± 3A with a fast transient response at a certain operating condition. If a transient is expected to last above the maximum continuous current rating for a significant amount of time then the output capacitor should be sized large enough to prevent an excessive voltage drop. Despite the fact that the TJ2997 is designed to handle large transient output currents it is not capable of handling these for long durations, under all conditions. The reason for this is the standard packages are not able to thermally dissipate the heat as a result of the internal power loss. If large currents are required for longer durations, then care should be taken to ensure that the maximum junction temperature is not exceeded. Proper thermal derating should always be used (please refer to the Thermal Dissipation section). If the junction temperature exceeds the thermal shutdown point than VTT will tri-state until the part returns below the hysteretic trip-point. Apr, 2011 - R1.0.1 6/13 HTC DDR Termination Regulator TJ2997 THERMAL DISSIPATION Since the TJ2997 is a linear regulator any current flow from VTT will result in internal power dissipation generating heat. To prevent damaging the part from exceeding the maximum allowable junction temperature, care should be taken to derate the part dependent on the maximum expected ambient temperature and power dissipation. The maximum allowable internal temperature rise, TRmax can be calculated given the maximum ambient temperature, TAmax of the application and the maximum allowable junction temperature, TJmax. TRmax = TJmax − TAmax From this equation, the maximum allowable power dissipation, PDmax of the part can be calculated: PDmax = TRmax / θ JA The maximum allowable value for junction-to-ambient thermal resistance, θJA, can be calculated using the formula: θJA = TRmax / PD = (TJmax – TAmax) / PD The θJA of the TJ2997 will be dependent on several variables: the package used; the thickness of copper; the number of vias and the airflow. For instance, the θJA of the SOP8 is 165°C/W with the package mounted to a standard 8x4 2-layer board with 1oz. copper, no airflow, and 0.5W dissipation at room temperature. This value can be reduced to 152°C/W by changing to a 3x4 board with 2 oz. copper that is the JEDEC standard. Additional improvements can be made by the judicious use of vias to connect the part and dissipate heat to an internal ground plane. Using larger traces and more copper on the top side of the board can also help. With careful layout it is possible to reduce the θJA further than the nominal values. Additional improvements in lowering the θ JA can also be achieved with a constant airflow across the package. Optimizing the θJA and placing the TJ2997 in a section of a board exposed to lower ambient temperature allows the part to operate with higher power dissipation. The internal power dissipation can be calculated by summing the three main sources of loss: output current at VTT, either sinking or sourcing, and quiescent current at AVIN and VDDQ. During the active state (when enable is not held low) the total internal power dissipation can be calculated from the following equations: PD = PAVIN + PVDDQ + PVTT Where, PAVIN = PVDDQ = IAVIN x VVDDQ VAVIN x IVDDQ = VVDDQ2 x RVDDQ To calculate the maximum power dissipation at VTT both conditions at VTT need to be examined, Apr, 2011 - R1.0.1 7/13 HTC DDR Termination Regulator TJ2997 sinking and sourcing current. Although only one equation will add into the total, VTT cannot source and sink current simultaneously. PVTT = VVTT x ILOAD (Sinking) or PVTT = ( VPVIN - VVTT) x ILOAD (Sourcing) The power dissipation of the TJ2997 can also be calculated during the shutdown state. During this condition the output VTT will tri-state, therefore that term in the power equation will disappear as it cannot sink or source any current (leakage is negligible). The only losses during shutdown will be the reduced quiescent current at AVIN and the constant impedance that is seen at the VDDQ pin. PD = PAVIN + PVDDQ , Where, PAVIN = IAVIN x VAVIN PVDDQ Apr, 2011 - R1.0.1 = VVDDQ x IVDDQ = VVDDQ2 8/13 x RVDDQ HTC DDR Termination Regulator TJ2997 TYPICAL APPLICATION INFORMATION Several different application circuits have been shown in Figure 2 through Figure 11 to illustrate some of the options that are possible in configuring the TJ2997. SSTL-2 APPLICATIONS For the majority of applications that implement the SSTL-2 termination scheme it is recommended to connect all the input rails to the 2.5V rail. This provides an optimal trade-off between power dissipation and component count and selection. An example of this circuit can be seen in Figure 2. FIGURE 2. Recommended SSTL-2 Implementation If power dissipation or efficiency is a major concern then the TJ2997 has the ability to operate on split power rails. The output stage (PVIN) can be operated on a lower rail such as 1.8V and the analog circuitry (AVIN) can be connected to a higher rail such as 2.5V, 3.3V or 5V. This allows the internal power dissipation to be lowered when sourcing current from VTT. The disadvantage of this circuit is that the maximum continuous current is reduced because of the lower rail voltage, although it is adequate for all motherboard SSTL-2 applications. Increasing the output capacitance can also help if periods of large load transients will be encountered. FIGURE 3. Lower Power Dissipation SSTL-2 Implementation The third option for SSTL-2 applications in the situation that a 1.8V rail is not available and it is not desirable to use 2.5V is to connect the TJ2997 power rail to 3.3V. In this situation AVIN will be limited to operation on the 3.3V or 5V rail as PVIN can never exceed AVIN. This configuration has the ability to provide the maximum continuous output current at the downside of higher thermal dissipation. Care should be taken to prevent the TJ2997 from experiencing large current levels which cause the junction temperature to exceed the maximum. Because of this risk it is not recommended to supply the output stage with a voltage higher than a nominal 3.3V rail. Apr, 2011 - R1.0.1 9/13 HTC DDR Termination Regulator TJ2997 FIGURE 4. SSTL-2 Implementation with higher voltage rails DDR-II APPLICATIONS With the separate VDDQ pin and an internal resistor divider it is possible to use the TJ2997 in applications utilizing DDR-II memory. Figure 3 and Figure 4 show several implementations of recommended circuits. Figure 3 shows the recommended circuit configuration for DDR-II applications. The output stage is connected to the 1.8V rail and the AVIN pin can be connected to either a 3.3V or 5V rail. FIGURE 5. Recommended DDR-II Termination If it is not desirable to use the 1.8V rail it is possible to connect the output stage to a 3.3V rail. Care should be taken to do not exceed the maximum junction temperature as the thermal dissipation increases with lower VTT output voltages. For this reason it is not recommended to power PVIN off a rail higher than the nominal 3.3V. The advantage of this configuration is that it has the ability to source and sink a higher maximum continuous current. FIGURE 6. DDR-II Termination with higher voltage rails Apr, 2011 - R1.0.1 10/13 HTC DDR Termination Regulator TJ2997 LEVEL SHIFTING If standards other than SSTL-2 are required, such as SSTL-3, it may be necessary to use a different scaling factor than 0.5 times VDDQ for regulating the output voltage. Several options are available to scale the output to any voltage required. One method is to level shift the output by using feedback resistors from VTT to the VSENSE pin. This has been illustrated in Figures 7 and 8. Figure 7 shows how to use two resistors to level shift VTT above the internal reference voltage of VDDQ / 2. To calculate the exact voltage at VTT the following equation can be used VTT = VDDQ / 2 ( 1 + R1 / R2 ) FIGURE 7. Increasing VTT by Level Shifting Conversely, the R2 resistor can be placed between VSENSE and VDDQ to shift the VTT output lower than the internal reference voltage of VDDQ / 2. The equations relating VTT and the resistors can be seen below: VTT = VDDQ / 2 (1 - R1 / R2) FIGURE 8. Decreasing VTT by Level Shifting HSTL APPLICATIONS The TJ2997 can be easily adapted for HSTL applications by connecting VDDQ to the 1.5V rail. This will produce a VTT and VREF voltage of approximately 0.75V for the termination resistors. It is possible to connect PVIN to higher than a 2.5V rail for higher source/sink current. Care should be taken to do not exceed the maximum junction temperature as the thermal dissipation increases with lower VTT output voltages (For more information, refer to the Thermal Dissipation section.). The advantage of this Apr, 2011 - R1.0.1 11/13 HTC DDR Termination Regulator TJ2997 configuration is that it has the ability to source and sink a higher maximum continuous current. PVIN can be also connected to a 1.8V rail and it has a limitation of maximum continuous current. PVIN should be connected to a voltage higher than a 1.5V rail. The source/sink current for each power rail, refer to Electrical Characteristics Section. At any power rail, care should be taken to do not exceed the maximum junction temperature as the thermal dissipation increases with lower VTT output voltages as described at the Thermal Dissipation Section. FIGURE 9. HSTL Application QDR APPLICATIONS Quad data rate (QDR) applications utilize multiple channels for improved memory performance. However, this increase in bus lines has the effect of increasing the current levels required for termination. The recommended approach in terminating multiple channels is to use a dedicated TJ2997 for each channel. This simplifies layout and reduces the internal power dissipation for each regulator. Separate VREF signals can be used for each DIMM bank from the corresponding regulator with the chipset reference provided by a local resistor divider or one of the TJ2997 signals. Because VREF and VTT are expected to track and the part to part variations are minor, there should be little difference between the reference signals of each TJ2997. FIGURE 10. Typical SSTL-2 Application Circuit OUTPUT CAPACITOR SELECTION For applications utilizing the TJ2997 to terminate SSTL-2 I/O signals the typical application circuit shown in Figure 8 can be implemented. This circuit permits termination in a minimum amount of board space and component count. Capacitor selection can be varied depending on the number of lines terminated and the maximum load transient. However, with motherboards and other applications where Apr, 2011 - R1.0.1 12/13 HTC DDR Termination Regulator TJ2997 VTT is distributed across a long plane it is advisable to use multiple bulk capacitors and addition to high frequency decoupling. Figure 9 shown below depicts an example circuit where 2 bulk output capacitors could be situated at both ends of the VTT plane for optimal placement. Large aluminum electrolytic capacitors are used for their low ESR and low cost. FIGURE 11. Typical SSTL-2 Application Circuit for Motherboards In most PC applications an extensive amount of decoupling is required because of the long interconnects encountered with the DDR-SDRAM DIMMs mounted on modules. As a result bulk aluminum electrolytic capacitors in the range of 1000uF are typically used. PCB LAYOUT CONSIDERATIONS 1. The input capacitor for the power rail should be placed as close as possible to the PVIN pin. 2. VSENSE should be connected to the VTT termination bus at the point where regulation is required. For mother- board applications an ideal location would be at the center of the termination bus. 3. VDDQ can be connected remotely to the VDDQ rail input at either the DIMM or the Chipset. This provides the most accurate point for creating the reference voltage. 4. For improved thermal performance excessive top side copper should be used to dissipate heat from the package. Numerous vias from the ground connection to the internal ground plane will help. Additionally these can be located underneath the package if manufacturing standards permit. 5. Care should be taken when routing the VSENSE trace to avoid noise pickup from switching I/O signals. A 0.1uF ceramic capacitor located close to the SENSE can also be used to filter any unwanted high frequency signal. This can be an issue especially if long SENSE traces are used. 6. VREF should be bypassed with a 0.01µF or 0.1µF ceramic capacitor for improved performance. This capacitor should be located as close as possible to the VREF pin. Apr, 2011 - R1.0.1 13/13 HTC