CYPRESS STK11C68

STK11C68-5 (SMD5962-92324)
64 Kbit (8K x 8) SoftStore nvSRAM
Features
Functional Description
■
35 ns, 45 ns, and 55 ns access times
■
Pin compatible with industry standard SRAMs
■
Software initiated nonvolatile STORE
■
Unlimited Read and Write endurance
■
Automatic RECALL to SRAM on power up
■
Unlimited RECALL cycles
■
1,000,000 STORE cycles
The Cypress STK11C68-5 is a 64 Kb fast static RAM with a
nonvolatile element in each memory cell. The embedded
nonvolatile elements incorporate QuantumTrap technology to
produce the world’s most reliable nonvolatile memory. The
SRAM provides unlimited read and write cycles, while
independent nonvolatile data resides in the highly reliable
QuantumTrap cell. Data transfers under software control from
SRAM to the nonvolatile elements (the STORE operation). On
power up, data is automatically restored to the SRAM (the
RECALL operation) from the nonvolatile memory. RECALL
operations are also available under software control.
■
100 year data retention
■
Single 5V ± 10% operation
■
Military temperature
■
28-pin (300 mil) CDIP and 28-pad LCC packages
Logic Block Diagram
A5
A7
A8
A9
A 11
STATIC RAM
ARRAY
128 X 512
RECALL
STORE/
RECALL
CONTROL
DQ 0
DQ 4
DQ 5
DQ 6
A0
- A12
COLUMN I/O
COLUMN DEC
INPUT BUFFERS
DQ 2
DQ 3
HSB
SOFTWARE
DETECT
A 12
DQ 1
VCAP
POWER
CONTROL
STORE
ROW DECODER
A6
VCC
Quantum Trap
128 X 512
A 0 A 1 A 2 A 3 A 4 A 10
DQ 7
OE
CE
WE
Cypress Semiconductor Corporation
Document Number: 001-51001 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 07, 2009
[+] Feedback
STK11C68-5 (SMD5962-92324)
Pinouts
Figure 1. Pin Diagram - 28-Pin DIP
1&
9&&
$
$
:(
1&
$
$
$
$
$
$ $
$
$
2(
$ $
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'4 '4
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966
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723
Figure 2. Pin Diagram - 28-Pin LLC
Pin Definitions
Pin Name
Alt
A0–A12
I/O Type
Input
DQ0-DQ7
Description
Address Inputs. Used to select one of the 8,192 bytes of the nvSRAM.
Input/Output Bidirectional Data I/O Lines. Used as input or output lines depending on operation.
WE
W
Input
Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O
pins is written to the specific address location.
CE
E
Input
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the
chip.
OE
G
Input
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during
read cycles. Deasserting OE HIGH causes the I/O pins to tristate.
VSS
VCC
Ground
Ground for the Device. The device is connected to ground of the system.
Power Supply Power Supply Inputs to the Device.
Document Number: 001-51001 Rev. *A
Page 2 of 15
[+] Feedback
STK11C68-5 (SMD5962-92324)
Device Operation
The STK11C68-5 is a versatile memory chip that provides
several modes of operation. The STK11C68-5 can operate as a
standard 8K x 8 SRAM. It has an 8K x 8 Nonvolatile Elements
shadow to which the SRAM information can be copied or from
which the SRAM can be updated in nonvolatile mode.
The software sequence is clocked with CE controlled Reads.
When the sixth address in the sequence is entered, the STORE
cycle commences and the chip is disabled. It is important that
Read cycles and not Write cycles are used in the sequence. It is
not necessary that OE is LOW for a valid sequence. After the
tSTORE cycle time is fulfilled, the SRAM is again activated for
Read and Write operation.
SRAM Read
Software RECALL
The STK11C68-5 performs a Read cycle whenever CE and OE
are LOW while WE is HIGH. The address specified on pins A0–12
determines the 8,192 data bytes accessed. When the Read is
initiated by an address transition, the outputs are valid after a
delay of tAA (Read cycle 1). If the Read is initiated by CE or OE,
the outputs are valid at tACE or at tDOE, whichever is later (Read
cycle 2). The data outputs repeatedly respond to address
changes within the tAA access time without the need for
transitions on any control input pins. They remain valid until
another address change or until CE or OE is brought HIGH, or
WE is brought LOW.
Data is transferred from the nonvolatile memory to the SRAM by
a software address sequence. A software RECALL cycle is
initiated with a sequence of Read operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE controlled Read operations is
performed:
1. Read address 0x0000, Valid READ
2. Read address 0x1555, Valid READ
3. Read address 0x0AAA, Valid READ
4. Read address 0x1FFF, Valid READ
5. Read address 0x10F0, Valid READ
6. Read address 0x0F0E, Initiate RECALL cycle
SRAM Write
A Write cycle is performed whenever CE and WE are LOW. The
address inputs must be stable before entering the Write cycle
and must remain stable until either CE or WE goes HIGH at the
end of the cycle. The data on the common I/O pins DQ0–7 are
written into the memory if it has valid tSD. This is done before the
end of a WE controlled Write or before the end of an CE
controlled Write. Keep OE HIGH during the entire Write cycle to
avoid data bus contention on common I/O lines. If OE is left LOW,
internal circuitry turns off the output buffers tHZWE after WE goes
LOW.
Software STORE
Data is transferred from the SRAM to the nonvolatile memory by
a software address sequence. The STK11C68-5 software
STORE cycle is initiated by executing sequential CE controlled
Read cycles from six specific address locations in exact order.
During the STORE cycle, an erase of the previous nonvolatile
data is first performed followed by a program of the nonvolatile
elements. When a STORE cycle is initiated, input and output are
disabled until the cycle is completed.
Because a sequence of Reads from specific addresses is used
for STORE initiation, it is important that no other Read or Write
accesses intervene in the sequence. If they intervene, the
sequence is aborted and no STORE or RECALL takes place.
To initiate the software STORE cycle, the following Read
sequence is performed:
1. Read address 0x0000, Valid READ
2. Read address 0x1555, Valid READ
3. Read address 0x0AAA, Valid READ
4. Read address 0x1FFF, Valid READ
5. Read address 0x10F0, Valid READ
6. Read address 0x0F0F, Initiate STORE cycle
Document Number: 001-51001 Rev. *A
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared; then, the nonvolatile information is transferred into the
SRAM cells. After the tRECALL cycle time, the SRAM is again
ready for Read and Write operations. The RECALL operation
does not alter the data in the nonvolatile elements. The
nonvolatile data can be recalled an unlimited number of times.
Hardware RECALL (Power Up)
During power up or after any low power condition (VCC <
VRESET), an internal RECALL request is latched. When VCC
once again exceeds the sense voltage of VSWITCH, a RECALL
cycle is automatically initiated and takes tHRECALL to complete.
If the STK11C68-5 is in a Write state at the end of power up
RECALL, the SRAM data is corrupted. To help avoid this
situation, a 10 Kohm resistor is connected either between WE
and system VCC or between CE and system VCC.
Hardware Protect
The STK11C68-5 offers hardware protection against inadvertent
STORE operation and SRAM Writes during low voltage
conditions. When VCAP < VSWITCH, all externally initiated STORE
operations and SRAM Writes are inhibited.
Noise Considerations
The STK11C68-5 is a high speed memory. It must have a high
frequency bypass capacitor of approximately 0.1 µF connected
between VCC and VSS, using leads and traces that are as short
as possible. As with all high speed CMOS ICs, careful routing of
power, ground, and signals reduce circuit noise.
Page 3 of 15
[+] Feedback
STK11C68-5 (SMD5962-92324)
Low Average Active Power
Figure 4. Current Versus Cycle Time (Write)
CMOS technology provides the STK11C68-5 the benefit of
drawing significantly less current when it is cycled at times longer
than 50 ns. Figure 3 and Figure 4 shows the relationship
between ICC and Read or Write cycle time. Worst case current
consumption is shown for both CMOS and TTL input levels
(commercial temperature range, VCC = 5.5V, 100% duty cycle
on chip enable). Only standby current is drawn when the chip is
disabled. The overall average current drawn by the STK11C68-5
depends on the following items:
■
Duty cycle of chip enable
■
Overall cycle rate for accesses
■
Ratio of Reads to Writes
■
CMOS versus TTL input levels
■
Operating temperature
■
VCC level
Best Practices
Cypress nvSRAM products have been used effectively for over
15 years. While ease of use is one of the product’s main system
values, the experience gained from working with hundreds of
applications has resulted in the following suggestions as best
practices:
■
I/O loading
Figure 3. Current Versus Cycle Time (Read)
■
The nonvolatile cells in an nvSRAM are programmed on the
test floor during final test and quality assurance. Incoming
inspection routines at customer or contract manufacturer’s
sites sometimes reprograms these values. Final NV patterns
are typically repeating patterns of AA, 55, 00, FF, A5, or 5A.
The end product’s firmware must not assume that an NV array
is in a set programmed state. Routines that check memory
content values to determine first time system configuration.
■
Cold or warm boot status, and so on must always program a
unique NV pattern (for example, complex 4-byte pattern of 46
E6 49 53 hex or more random bytes) as part of the final system
manufacturing test. This is to ensure these system routines
work consistently.
Table 1. Hardware Mode Selection
CE
WE
A12–A0
Mode
I/O
Notes
L
H
0x0000
0x1555
0x0AAA
0x1FFF
0x10F0
0x0F0F
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile STORE
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
[1]
L
H
0x0000
0x1555
0x0AAA
0x1FFF
0x10F0
0x0F0E
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile RECALL
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
[1]
Note
1. The six consecutive addresses must be in the order listed. WE must be high during all six consecutive CE controlled cycles to enable a nonvolatile cycle.
Document Number: 001-51001 Rev. *A
Page 4 of 15
[+] Feedback
STK11C68-5 (SMD5962-92324)
Maximum Ratings
Voltage on DQ0-7 ...................................–0.5V to Vcc + 0.5V
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Power Dissipation ......................................................... 1.0W
DC Output Current (1 output at a time, 1s duration).... 15 mA
Operating Range
Temperature under bias.............................. –55°C to +125°C
Supply Voltage on VCC Relative to GND ..........–0.5V to 7.0V
Range
Voltage on Input Relative to Vss............ –0.6V to VCC + 0.5V
Military
Ambient
Temperature
VCC
-55°C to +125°C
4.5V to 5.5V
DC Electrical Characteristics
Over the operating range (VCC = 4.5V to 5.5V)
Max
Unit
ICC1
Parameter
Average VCC Current
Description
tRC = 35 ns
tRC = 45 ns
tRC = 55 ns
Dependent on output loading and cycle rate. Values obtained
without output loads. IOUT = 0 mA
Test Conditions
Min
75
65
55
mA
mA
mA
ICC2
Average VCC Current
during STORE
All Inputs Do Not Care, VCC = Max
Average current for duration tSTORE
3
mA
ICC3
Average VCC Current at WE > (VCC – 0.2V). All other inputs cycling.
tRC= 200 ns, 5V, 25°C Dependent on output loading and cycle rate. Values obtained
Typical
without output loads.
10
mA
ISB1[2]
VCC Standby Current
(Standby, Cycling TTL
Input Levels)
tRC = 35 ns, CE > VIH
tRC = 45 ns, CE > VIH
tRC = 55 ns, CE > VIH
24
21
20
mA
mA
mA
ISB2 [2]
VCC Standby Current
CE > (VCC – 0.2V). All others VIN < 0.2V or > (VCC – 0.2V).
Standby current level after nonvolatile cycle is complete.
Inputs are static. f = 0 MHz
1500
μA
IIX
Input Leakage Current
VCC = Max, VSS < VIN < VCC
-1
+1
μA
IOZ
Off State Output
Leakage Current
VCC = Max, VSS < VIN < VCC, CE or OE > VIH or WE < VIL
-5
+5
μA
VIH
Input HIGH Voltage
2.2
VCC + 0.5
V
VIL
Input LOW Voltage
VSS – 0.5
0.8
V
VOH
Output HIGH Voltage
IOUT = –4 mA
VOL
Output LOW Voltage
IOUT = 8 mA
2.4
V
0.4
V
Data Retention and Endurance
Parameter
Description
DATAR
Data Retention
NVC
Nonvolatile STORE Operations
Min
Unit
100
Years
1,000
K
Max
Unit
8
pF
7
pF
Capacitance
In this table, the capacitance parameters are listed.[3]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 0 to 3.0V
Note
2. CE > VIH does not produce standby current levels until any nonvolatile cycle in progress has timed out.
3. These parameters are guaranteed by design and are not tested.
Document Number: 001-51001 Rev. *A
Page 5 of 15
[+] Feedback
STK11C68-5 (SMD5962-92324)
Thermal Resistance
In this table, the thermal resistance parameters are listed.[3]
Parameter
ΘJA
ΘJC
Description
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Test Conditions
28-CDIP
28-LCC
Unit
Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA /
JESD51.
TBD
TBD
°C/W
TBD
TBD
°C/W
Figure 5. AC Test Loads
R1 480Ω
5.0V
Output
30 pF
R2
255Ω
AC Test Conditions
Input Pulse Levels .................................................... 0V to 3V
Input Rise and Fall Times (10% to 90%) ...................... <5 ns
Input and Output Timing Reference Levels .................... 1.5V
Document Number: 001-51001 Rev. *A
Page 6 of 15
[+] Feedback
STK11C68-5 (SMD5962-92324)
AC Switching Characteristics
SRAM Read Cycle
Parameter
Cypress
Alt
Parameter
tELQV
tACE
[4]
tAVAV,
tRC
tELEH
tAVQV
tAA [5]
35 ns
Description
Min
Chip Enable Access Time
Read Cycle Time
45 ns
Max
Min
35
35
55 ns
Max
Min
45
45
Max
Unit
55
ns
ns
55
Address Access Time
35
45
55
ns
tGLQV
tAXQX
Output Enable to Data Valid
Output Hold After Address Change
15
20
35
5
5
5
ns
ns
tLZCE
[6]
tELQX
Chip Enable to Output Active
5
5
5
ns
tHZCE
[6]
tEHQZ
Chip Disable to Output Inactive
tLZOE
[6]
tGLQX
Output Enable to Output Active
tHZOE [6]
tDOE
tOHA
[5]
13
0
tGHQZ
Output Disable to Output Inactive
tPU
[3]
tELICCH
Chip Enable to Power Active
tPD
[3]
tEHICCL
Chip Disable to Power Standby
15
25
0
13
0
0
15
ns
25
0
35
0
45
ns
ns
ns
55
ns
Switching Waveforms
Figure 6. SRAM Read Cycle 1: Address Controlled [4, 5]
W5&
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W $$
W2+$
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'$7$9$/,'
Figure 7. SRAM Read Cycle 2: CE and OE Controlled [4]
W5&
$''5(66
W$&(
W3'
W/=&(
&(
W+=&(
2(
W+=2(
W'2(
W/=2(
'4'$7$287
'$7$9$/,'
W 38
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$&7,9(
67$1'%<
Notes
4. WE must be High during SRAM Read cycles.
5. I/O state assumes CE and OE < VIL and WE > VIH; device is continuously selected.
6. Measured ± 200 mV from steady state output voltage.
Document Number: 001-51001 Rev. *A
Page 7 of 15
[+] Feedback
STK11C68-5 (SMD5962-92324)
SRAM Write Cycle
Parameter
Cypress
Alt
Parameter
tAVAV
tWC
tWLWH, tWLEH
tPWE
tELWH, tELEH
tSCE
tSD
tDVWH, tDVEH
tWHDX, tEHDX
tHD
tAVWH, tAVEH
tAW
tSA
tAVWL, tAVEL
tWHAX, tEHAX
tHA
[6,7]
tWLQZ
tHZWE
Write Cycle Time
Write Pulse Width
Chip Enable To End of Write
Data Setup to End of Write
Data Hold After End of Write
Address Setup to End of Write
Address Setup to Start of Write
Address Hold After End of Write
Write Enable to Output Disable
35
25
25
12
0
25
0
0
tLZWE [6]
Output Active After End of Write
5
tWHQX
35 ns
Description
Min
45 ns
Max
Min
55 ns
Max
45
30
30
15
0
30
0
0
13
Min
Max
55
45
45
30
0
45
0
0
15
5
35
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Switching Waveforms
Figure 8. SRAM Write Cycle 1: WE Controlled [7, 8]
tWC
ADDRESS
tHA
tSCE
CE
tAW
tSA
tPWE
WE
tSD
tHD
DATA VALID
DATA IN
tHZWE
DATA OUT
tLZWE
HIGH IMPEDANCE
PREVIOUS DATA
Figure 9. SRAM Write Cycle 2: CE and OE Controlled [7, 8]
tWC
ADDRESS
CE
WE
tHA
tSCE
tSA
tAW
tPWE
tSD
DATA IN
DATA OUT
tHD
DATA VALID
HIGH IMPEDANCE
Notes
7. If WE is Low when CE goes Low, the outputs remain in the high impedance state.
8. CE or WE must be greater than VIH during address transitions.
Document Number: 001-51001 Rev. *A
Page 8 of 15
[+] Feedback
STK11C68-5 (SMD5962-92324)
AutoStore INHIBIT or Power Up RECALL
Parameter
Alt
STK11C68-5
Description
Min
Max
Unit
tHRECALL [9] tRESTORE
Power up RECALL Duration
550
μs
tSTORE
STORE Cycle Duration
10
ms
4.5
V
3.6
V
tHLHZ
VSWITCH
Low Voltage Trigger Level
VRESET
Low Voltage Reset Level
4.0
Figure 10. AutoStore INHIBIT/Power Up RECALL
VCC
5V
VSWITCH
VRESET
STORE INHIBIT
POWER-UP RECALL
tHRECALL
DQ (DATA OUT)
POWER-UP
RECALL
BROWN OUT
STORE INHIBIT
BROWN OUT
STORE INHIBIT
BROWN OUT
STORE INHIBIT
NO RECALL
(VCC DID NOT GO
BELOW VRESET)
NO RECALL
(VCC DID NOT GO
BELOW VRESET)
RECALL WHEN
VCC RETURNS
ABOVE VSWITCH
Notes
9. tHRECALL starts from the time VCC rises above VSWITCH.
Document Number: 001-51001 Rev. *A
Page 9 of 15
[+] Feedback
STK11C68-5 (SMD5962-92324)
Software Controlled STORE/RECALL Cycle
The software controlled STORE/RECALL cycle follows. [10, 11]
Parameter
Alt
Description
35 ns
Min
45 ns
Max
Min
55 ns
Max
Min
Max
Unit
tRC
tAVAV
STORE/RECALL Initiation Cycle Time
35
45
55
ns
tSA[10]
tCW[10]
tHACE[10]
tRECALL[10]
tAVEL
Address Setup Time
0
0
0
ns
tELEH
Clock Pulse Width
25
30
35
ns
tELAX
Address Hold Time
20
20
20
ns
RECALL Duration
20
20
20
μs
Switching Waveform
Figure 11. CE Controlled Software STORE/RECALL Cycle [10]
tRC
ADDRESS # 1
ADDRESS
tSA
tRC
ADDRESS # 6
tSCE
CE
tHACE
OE
t STORE / t RECALL
DQ (DATA)
DATA VALID
DATA VALID
HIGH IMPEDANCE
Notes
10. The software sequence is clocked on the falling edge of CE without involving OE (double clocking aborts the sequence).
11. The six consecutive addresses must be read in the order listed in Table 1 on page 4. WE must be HIGH during all six consecutive cycles.
Document Number: 001-51001 Rev. *A
Page 10 of 15
[+] Feedback
STK11C68-5 (SMD5962-92324)
Part Numbering Nomenclature
STK11C68 - 5 C 45 M
Temperature Range:
M - Military (-55 to 125°C)
Speed:
35 - 35 ns
45 - 45 ns
55 - 55 ns
Package:
C = Ceramic 28-pin 300 mil DIP (gold lead finish)
K = Ceramic 28-pin 300 mil DIP (Solder dip finish)
L = Ceramic 28-pin LLC
Retention / Endurance
5 = Military (10 years or 105 cycles)
SMD5962-92324 04 MX X
Lead Finish
A = Solder DIP lead finish
C = Gold lead DIP finish
X = Lead finish “A” or “C” is acceptable
Case Outline
X = Ceramic 28-pin 300 mil DIP
Y = Ceramic 28-pin LLC
Device Class Indicator - Class M
Device Type:
04 = 55 ns
05 = 45 ns
06 = 35 ns
Document Number: 001-51001 Rev. *A
Page 11 of 15
[+] Feedback
STK11C68-5 (SMD5962-92324)
Ordering Information
Speed (ns)
35
45
55
Ordering Code
Package Diagram
Package Type
STK11C68-5C35M
001-51695
28-Pin CDIP (300 mil)
STK11C68-5K35M
001-51695
28-Pin CDIP (300 mil)
STK11C68-5L35M
001-51696
28-Pin LCC (350 mil)
STK11C68-5C45M
001-51695
28-Pin CDIP (300 mil)
STK11C68-5K45M
001-51695
28-Pin CDIP (300 mil)
STK11C68-5L45M
001-51696
28-Pin LCC (350 mil)
STK11C68-5C55M
001-51695
28-Pin CDIP (300 mil)
STK11C68-5K55M
001-51695
28-Pin CDIP (300 mil)
STK11C68-5L55M
001-51696
28-Pin LCC (350 mil)
Operating Range
Military
This table contains Final information. Contact your local Cypress sales representative for availability of these parts.
Document Number: 001-51001 Rev. *A
Page 12 of 15
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STK11C68-5 (SMD5962-92324)
Package Diagrams
Figure 12. 28-Pin (300-Mil) Side Braze DIL (001-51695)
001-51695 **
Document Number: 001-51001 Rev. *A
Page 13 of 15
[+] Feedback
STK11C68-5 (SMD5962-92324)
Package Diagrams (continued)
Figure 13. 28-Pad (350-Mil) LCC (001-51696)
1. ALL DIMENSION ARE IN INCHES AND MILLIMETERS [MIN/MAX]
2. JEDEC 95 OUTLINE# MO-041
3. PACKAGE WEIGHT : TBD
001-51696 **
Document Number: 001-51001 Rev. *A
Page 14 of 15
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STK11C68-5 (SMD5962-92324)
Document History Page
Document Title: STK11C68-5 (SMD5962-92324) 64 Kbit (8K x 8) SoftStore nvSRAM
Document Number: 001-51001
Rev.
ECN No.
Orig. of Change
Submission
Date
**
2666844
GVCH/PYRS
03/02/09
*A
2685053
GVCH
04/07/2009
Description of Change
New data sheet
Added part numbers: STK11C68-5K45M and STK11C68-5K55M
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© Cypress Semiconductor Corporation, 2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-51001 Rev. *A
Revised April 07, 2009
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holders.
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