Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A http://www.semicon.panasonic.co.jp/en/ 7 x 7 Dots Matrix LED Driver LSI with Step-up DC/DC Converter for White LED FEATURES DESCRIPTION 7 x 7 LED Matrix Driver (Total LED that can be driven = 49) Built-in memory (ROM and RAM) Step-up DC/DC converter LDO : 2-ch GPIO : 2-ch GPI : 3-ch (3pins from GPI1 to GPI3 are in common with SPI2) GPO : 2-ch SPI Interface : 2-ch (SPI2 is only receiving. It is possible to control only address 05h by SPI2.) Driver for LED (Main LED : 4-ch, Sub LED : 2-ch, LED for Photo flash : 2-ch, RGB color unit : 1-ch) 80 pin Wafer level chip size package (WLCSP) AN32055A is a 6-ch LED driver for LCD backlights, and a driver for LED matrix. They supply voltage by step-up DC/DC converter. APPLICATIONS Mobile Phone Smart Phone PCs Game Consoles Home Appliances etc. TYPICAL APPLICATION 0.3 LX LDOCNT GPI [ 3ch ] GPO [ 2ch ] GPIO [ 2ch ] LEDCNT LEDCTL VIBCTL INT CSB CLK DI DO RSTB EXTCLK DCDCGND 7 LDO2 7 X0~X6 1.0 F LDO1 1.0 F 1.0 F IREF VREFD Y0~Y6 27 k TEST1 TEST2 LEDGND1 LEDGND2 RGBGND1 RGBGND2 PGND1 PGND2 AGND DGND CPU I/F 22 F FB VLED1 VLED2 10 F VB VBLED VBDCDC 4.7 H 100 Battery CHGGND R1 G1 B1 R2 G2 BL [ 4ch ] 2 B2 4 PL [ 2ch ] 2 BLS [ 2ch ] LED Note) The application circuit is an example. The operation of the mass production set is not guaranteed. Sufficient evaluation and verification is required in the design of the mass production set. The Customer is fully responsible for the incorporation of the above illustrated application circuit in the design of the equipment. Page 1 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A CONTENTS FEATURES ………………………………………………………………………………… 1 DESCRIPTION ……..……………………………………………………………………… 1 APPLICATIONS …………………………………………………………………………… 1 TYPICAL APPLICATION ………………………………………………………………… 1 CONTENTS ………………………………………………………………………………… 2 ABSOLUTE MAXIMUM RATINGS ……………………………………………………… 3 POWER DISSIPATION RATING ………………………………………………………… 3 RECOMMENDED OPERATING CONDITIONS …..…………………………………… 4 ELECTRICAL CHARACTERISTICS .…………………………………………………… 5 PIN CONFIGURATION ………………………………………………………………..…. 20 PIN FUNCTIONS .………………………………………………………………………… 21 FUNCTIONAL BLOCK DIAGRAM ..…………………………………………………… 25 OPERATION ……………………………………………………………………………… 26 PACKAGE INFORMATION …………………………………………………………….. 95 IMPORTANT NOTICE ………………………………………………………………….... 96 Page 2 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Unit Note VBMAX 6.0 V *1 VLEDMAX 6.5 V *1 Topr –30 to + 85 C *2 Tj – 30 to + 125 C *2 Tstg – 55 to + 125 C *2 LEDCTL, RSTB, CSB, CLK, DI, EXTCLK, VIBCTL, GPI1, GPI2, GPI3, GPIO1, GPIO2 – 0.3 to 3.4 V — LEDCNT, LDOCNT, FB – 0.3 to 6.0 V — GPO1, GPO2, INT, DO – 0.3 to 3.4 V — LDO1, LDO2 – 0.3 to 6.0 V — BL1, BL2, BL3, BL4, BLS1, BLS2, PL1, PL2, R1, G1, B1, R2, G2, B2, LDO1, LDO2, LX, X0, X1, X2, X3, X4, X5, X6, Y0, Y1, Y2, Y3, Y4, Y5, Y6 – 0.3 to 6.5 V — HBM 1.0 to 1.5 kV — Supply voltage Operating ambience temperature Operating junction temperature Storage temperature Input Voltage Range Output Voltage Range ESD Note) This product may sustain permanent damage if subjected to conditions higher than the above stated absolute maximum rating. This rating is the maximum rating and device operating at this range is not guaranteeable as it is higher than our stated recommended operating range. When subjected under the absolute maximum rating for a long time, the reliability of the product may be affected. *1: VBMAX = VBDCDC = VBLED = VB, VLEDMAX = VLED1 = VLED2. The values under the condition not exceeding the above absolute maximum ratings and the power dissipation. *2: Except for the power dissipation, operating ambient temperature, and storage temperature, all ratings are for Ta = 25C. POWER DISSIPATION RATING PACKAGE 80 pin Wafer level chip size package (WLCSP) JA PD (Ta=25 C) PD (Ta=85 C) 119.4 C /W 0.837 W 0.335 W Note) For the actual usage, please refer to the PD-Ta characteristics diagram in the package specification, follow the power supply voltage, load and ambient temperature conditions to ensure that there is enough margin and the thermal design does not exceed the allowable value. This value is based on the data LSI mount on PCB Grass Epoxy : 50 X 50 X 0.8 t ( mm ). CAUTION Although this LSI has built-in ESD protection circuit, it may still sustain permanent damage if not handled properly. Therefore, proper ESD precautions are recommended to avoid electrostatic damage to the MOS gates. Page 3 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A RECOMMENDED OPERATING CONDITIONS Parameter Supply voltage range Input Voltage Range Output Voltage Range Symbol Min. Typ. Max. Unit Note VB 3.1 3.7 4.6 V *1 VLED 3.1 5.0 5.6 V *1 LEDCTL, RSTB, CSB, CLK, DI, EXTCLK, VIBCTL, GPI1, GPI2, GPI3, GPIO1, GPIO2 – 0.3 — 3.0 V — LEDCNT, LDOCNT, FB – 0.3 — VB + 0.3 V *2 GPO1, GPO2, INT, DO – 0.3 — 3.0 V — BL1, BL2, BL3, BL4, BLS1, BLS2, PL1, PL2, R1, G1, B1, R2, G2, B2, LDO1, LDO2, LX, X0, X1, X2, X3, X4, X5, X6, Y0, Y1, Y2, Y3, Y4, Y5, Y6 – 0.3 — VLED + 0.3 V *2 Note) *1: The values under the condition not exceeding the above absolute maximum ratings and the power dissipation. Do not apply external currents and voltages to any pin not specifically mentioned. Voltage values, unless otherwise specified, are with respect to GND. GND is voltage for AGND, DGND, LEDGND1, LEDGND2, RGBGND1, RGBGND2, DCDCGND, PGND1 and PGND2. VB is voltage for VBDCDC, VBLED and VB. VLED is voltage for VLED1 and VLED2. *2: (VB + 0.3 ) V must not exceed 6 V. (VLED + 0.3) V must not exceed 6.5 V. Page 4 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A ELECTRICAL CHARACTERISTICS VB = VBDCDC = VBLED = 3.6 V, VLED1 = VLED2 = 4.9 V Note) Ta = 25 C 2 C unless otherwise specified. Parameter Symbol Condition Limits Min Typ Max Unit Note Current consumption ICC1 At OFF mode LDOCNT = Low 0 1 A — Current consumption (2) ICC2 At Standby mode LDOCNT = Low LDO2 is active. 8 12 A — Current consumption (3) ICC3 LDOCNT = High LDO1 and LDO2 are active. 18 24 A — VREF IVREF = 0 A 1.21 1.24 1.27 V — VIREF IIREF = 0 A 0.44 0.54 0.64 V — ILDO1 = – 30 mA 1.79 1.85 1.91 V — LDOCNT = High REG18 = Low VLDO1 = 0 V, IOFF1 = ILDO1 1 A — LDOCNT = High REG18 = High VLDO1 = 0 V, IPT1 = ILDO1 50 100 200 mA — PSL11 VB = 3.6 V + 0.2 V[p-p] f = 1 kHz ILDO1 = – 15 mA PSL11 = 20log(acVLDO1 / 0.2) – 45 – 40 dB — PSL12 VB = 3.6 V + 0.2 V[p-p] f = 10 kHz ILDO1 = – 15 mA PSL12 = 20log(acVLDO1 / 0.2) – 35 – 25 dB — Current consumption (1) Reference voltage Output voltage Reference current Output voltage Voltage regulator (LDO1) Output voltage Leakage Current when LDO1 turns off Short circuit protection current Ripple rejection (1) Ripple rejection (2) VL1 IOFF1 IPT1 Page 5 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A ELECTRICAL CHARACTERISTICS (continued) VB = VBDCDC = VBLED = 3.6 V, VLED1 = VLED2 = 4.9 V Note) Ta = 25 C 2 C unless otherwise specified. Parameter Symbol Condition Limits Min Typ Max Unit Note Voltage regulator (LDO2) VL2 ILDO2 = – 30 mA 2.76 2.85 2.94 V IOFF2 LDOCNT = Low REG28 = Low VLDO2 = 0 V IOFF2 = ILDO2 1 A IPT2 LDOCNT = High VLDO2 = 0V IPT2 = ILDO2 50 100 300 mA PSL21 VB = 3.6 V + 0.2 V[p-p] f = 1 kHz ILDO2 = – 15 mA PSL21 = 20log(acVLDO2 / 0.2) – 35 – 30 dB PSL22 VB = 3.6 V + 0.2 V[p-p] f = 10 kHz ILDO2 = – 15 mA PSL22 = 20log(acVLDO2 / 0.2) – 25 – 15 dB Output voltage (1) VDC1 Mode 1 Iout = – 400 mA 4.62 4.89 5.16 V Output voltage (2) VDC2 Mode 2 Iout = – 400 mA 5.03 5.3 5.57 V OSCEN = [1] , DDSW = [1] 0.96 1.20 1.44 MHz *1 Output voltage Leakage Current when LDO2 turns off Short circuit protection current Ripple rejection (1) Ripple rejection (2) Step-up DC/DC converter Oscillation frequency Short detection delay time FDC TSCP Time when INT is set to High from Low, after short detection. 3 13 30 ms RSCAN IY0, Y1, Y2, Y3, Y4, Y5, Y6 = – 5 mA RSCAN = VY0, Y1, Y2, Y3, Y4, Y5, Y6 / 5 mA 2 4.8 SCAN Switch Resistance at the Switch ON *1: Make sure to set both bits of OSCEN and DDSW to [1]. During OSCEN = [1] , DDSW must be set to [1]. Page 6 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A ELECTRICAL CHARACTERISTICS (continued) VB = VBDCDC = VBLED = 3.6 V, VLED1 = VLED2 = 4.9 V Note) Ta = 25 C 2 C unless otherwise specified. Parameter Symbol Condition Limits Unit Note Min Typ Max 0.945 1.027 1.109 mA *2 Current generator (For backlights) Output current (1) IBL1 At 1mA setup VBL1, BL2, BL3, BL4 = 1 V IBLS1 = IBL1, BL2, BL3, BL4 Output current (2) IBL2 At 2 mA setup VBL1, BL2, BL3, BL4 = 1 V IBLS2 = IBL1, BL2, BL3, BL4 1.894 2.058 2.223 mA *2 Output current (3) IBL4 At 4 mA setup VBL1, BL2, BL3, BL4 = 1 V IBLS4 = IBL1, BL2, BL3, BL4 3.808 4.139 4.470 mA *2 Output current (4) IBL8 At 8 mA setup VBL1, BL2, BL3, BL4 = 1 V IBLS8 = IBL1, BL2, BL3, BL4 7.630 8.294 8.957 mA *2 IBL16 At 16 mA setup VBL1, BL2, BL3, BL4 = 1 V IBLS16 = IBL1, BL2, BL3, BL4 15.516 16.865 18.214 mA *2 Output current (5) Leakage Current when BL1 ~ BL4 turn off The error between channels IBLOFF At current OFF setup VBL1, BL2, BL3, BL4 = 4.75 V IBLSOFF = IBL1, BL2, BL3, BL4 1 A — IBLCH At 15 mA setup The average value of all channels, and the current error of each channel –5 5 — *2: Values when recommended parts (ERJ2RHD273X) are used for IREF terminal. The other current settings are combination of above items. Page 7 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A ELECTRICAL CHARACTERISTICS (continued) VB = VBDCDC = VBLED = 3.6 V, VLED1 = VLED2 = 4.9 V Note) Ta = 25 C 2 C unless otherwise specified. Parameter Symbol Condition Limits Min Typ Max 0.949 1.032 1.114 Unit Note Current generator (For sub backlights) Output current (1) IBLS1 At 1mA setup VBLS1, BLS2 = 1 V IBLS1 = IBLS1, BLS2 Output current (2) IBLS2 At 2 mA setup VBLS1, BLS2 = 1 V IBLS2 = IBLS1, BLS2 1.912 2.078 2.244 mA *2 Output current (3) IBLS4 At 4 mA setup VBLS1, BLS2 = 1 V IBLS4 = IBLS1, BLS2 3.818 4.149 4.480 mA *2 Output current (4) IBLS8 At 8 mA setup VBLS1, BLS2 = 1 V IBLS8 = IBLS1, BLS2 7.677 8.344 9.011 mA *2 IBLS16 At 16 mA setup VBLS1, BLS2 = 1 V IBLS16 = IBLS1, BLS2 15.331 16.665 17.998 mA *2 Output current (5) Leak current at the time of OFF The error between channels mA *2 IBLSOFF At current OFF setup VBLS1, BLS2 = 4.75 V IBLSOFF = IBLS1, BLS2 1 A — IBLSCH At 15 mA setup The average value of all channels, and the current error of each channel –5 5 — *2: Values when recommended parts (ERJ2RHD273X) are used for IREF terminal. The other current settings are combination of above items. Page 8 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A ELECTRICAL CHARACTERISTICS (continued) VB = VBDCDC = VBLED = 3.6 V, VLED1 = VLED2 = 4.9 V Note) Ta = 25 C 2 C unless otherwise specified. Parameter Symbol Condition Limits Unit Note Min Typ Max 0.942 1.024 1.105 mA *2 Current generator (For photo flashes) Output current (1) IPL1 At 1mA setup VPL1, PL2 = 1 V IPL1 = IPL1, PL2 Output current (2) IPL2 At 2 mA setup VPL1, PL2 = 1 V IPL2 = IPL1, PL2 1.887 2.051 2.215 mA *2 Output current (3) IPL4 At 4 mA setup VPL1, PL2 = 1 V IPL4 = IPL1, PL2 3.757 4.083 4.410 mA *2 Output current (4) IPL8 At 8 mA setup VPL1, PL2 = 1 V IPL8 = IPL1, PL2 7.526 8.180 8.835 mA *2 Output current (5) IPL16 At 16 mA setup VPL1, PL2 = 1 V IPL16 = IPL1, PL2 15.215 16.538 17.861 mA *2 Output current (6) IPL30 At 30mA setup VPL1, PL2 = 1 V IPL30 = IPL1, PL2 28.244 30.700 33.156 mA *2 IPLOFF At current OFF setup VPL1, PL2 = 4.75 V IPLOFF = IPL1, PL2 1 A — IPLCH At 15 mA setup The average value of all channels, and the current error of each channel –5 5 % — Leak current at the time of OFF The error between channels *2: Values when recommended parts (ERJ2RHD273X) are used for IREF terminal. The other current settings are combination of above items. Page 9 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A ELECTRICAL CHARACTERISTICS (continued) VB = VBDCDC = VBLED = 3.6 V, VLED1 = VLED2 = 4.9 V Note) Ta = 25 C 2 C unless otherwise specified. Parameter Symbol Condition Limits Unit Note Min Typ Max 0.920 1.000 1.080 mA *2 Current generator (For 7*7 dots matrix LED) Output current (1) IMX1 At 1mA setup VX0, X1, X2, X3, X4, X5, X6 = 1 V IMX1 = IX0, X1, X2, X3, X4, X5, X6 Output current (2) IMX2 At 2 mA setup VX0, X1, X2, X3, X4, X5, X6 = 1 V IMX2 = IX0, X1, X2, X3, X4, X5, X6 1.858 2.019 2.181 mA *2 Output current (3) IMX4 At 4 mA setup VX0, X1, X2, X3, X4, X5, X6 = 1 V IMX4 = IX0, X1, X2, X3, X4, X5, X6 3.742 4.068 4.393 mA *2 Output current (4) IMX8 At 8 mA setup VX0, X1, X2, X3, X4, X5, X6 = 1 V IMX8 = IX0, X1, X2, X3, X4, X5, X6 7.480 8.131 8.781 mA *2 IMX15 At 15 mA setup 14.220 15.456 16.693 mA VX0, X1, X2, X3, X4, X5, X6 = 1 V IMX15 = IX0, X1, X2, X3, X4, X5, X6 *2 1 A –5 5 Output current (5) Leak current at the time of OFF IMXOFF Current OFF setup VX0, X1, X2, X3, X4, X5, X6 = 4.75 V IMXOFF = IX0, X1, X2, X3, X4, X5, X6 The error between channels IMXCH The average value of all channels, and the current error of each channel *2: Values when recommended parts (ERJ2RHD273X) are used for IREF terminal. The other current settings are combination of above items. Page 10 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A ELECTRICAL CHARACTERISTICS (continued) VB = VBDCDC = VBLED = 3.6 V, VLED1 = VLED2 = 4.9 V Note) Ta = 25 C 2 C unless otherwise specified. Parameter Symbol Condition Limits Min Typ Max Unit Note Current generator (For RGB color unit) Output current (1) IRGB1 At 1mA setup VR1, G1, B1 = 1 V 0.950 1.032 1.115 mA *2 Output current (2) IRGB2 At 2 mA setup VR1, G1, B1 = 1 V 1.903 2.068 2.234 mA *2 Output current (3) IRGB4 At 4 mA setup VR1, G1, B1 = 1 V 3.777 4.105 4.434 mA *2 Output current (4) IRGB8 At 8 mA setup VR1, G1, B1 = 1 V 7.566 8.223 8.881 mA *2 Leak current at the time of OFF The error between channels IRGBOFF Current OFF setup VR1, G1, B1, R2, G2, B2 = 4.75 V IRGBOFF = IR1, G1, B1, R2, G2, B2 1 A IRGBCH The average value of all channels, and the current error of each channel –5 5 % RVLED VBLED = 2.2 V VCHGGND = 0 V ILED1 = – 10 mA RVLED = ( 2.2 V – VLED1 ) / 10 mA 5 20 10 50 Switch of Pch-MOS (VLED1) VBLED – VLED output impedance Switch of Nch-MOS (R1, R2, G2, B2) R1 output impedance RR1 VB = 2.2 V VCHGGND = 0 V IR1 = 5 mA RR1 = VR1 / 5 mA R2 output impedance RR2 Register : 19hD4 = High IR2 = 5 mA RR2 = VR2 / 5 mA 10 30 G2 output impedance RG2 Register : 19hD3 = High IG2 = 5 mA RG2 = VG2 / 5 mA 10 30 B2 output impedance RB2 Register : 19hD2 = High IB2 = 5 mA RB2 = VB2 / 5 mA 10 30 *2: Values when recommended parts (ERJ2RHD273X) are used for IREF terminal. The other current settings are combination of above items. Page 11 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A ELECTRICAL CHARACTERISTICS (continued) VB = VBDCDC = VBLED = 3.6 V, VLED1 = VLED2 = 4.9 V Note) Ta = 25 C 2 C unless otherwise specified. Parameter Symbol Condition Limits Min Typ Max Unit Note SPI I/F, LEDCTL, RSTB Input voltage range of Highlevel VIH High-level recognition voltage 1.4 LDO1 + 0.3 V Input voltage range of Lowlevel VIL Low-level recognition voltage – 0.3 0.4 V Input current of High-level IIH VLEDCTL, RSTB, CSB, CLK, DI = 1.85 V IIH = ILEDCTL, RSTB, CSB, CLK, DI 0 1 A Input current of Low-level IIL VLEDCTL, RSTB, CSB, CLK, DI = 0 V IIL = ILEDCTL, RSTB, CSB, CLK, DI 0 1 A GPIO I/F, GPI I/F Input voltage range of Highlevel 1 VIH1 High-level recognition voltage (LDO1 mode) 1.4 LDO1 + 0.3 V Input voltage range of Highlevel 1 VIH2 High-level recognition voltage (LDO2 mode) 2.1 LDO2 + 0.3 V Input voltage range of Lowlevel VIL Low-level recognition voltage – 0.3 0.4 V Input current of High-level IIH VGPI1, GPI2, GPI3, GPIO1, GPIO2 = 2.85 V IIH = IGPI1, GPI2, GPI3, GPIO1, GPIO2 0 1 A Input current of Low-level IIL VGPI1, GPI2, GPI3, GPIO1, GPIO2 = 0 V IIL = IGPI1, GPI2, GPI3, GPIO1, GPIO2 0 1 A LDO2 0.8 V LDO2 0.2 (0.15) V LDO1 0.8 V LDO1 0.3 (0.15) V GPIO I/F, GPO I/F, INT VOH1 IGPO1, GPO2, GPIO1, GPIO2, INT = – 2 mA VDDSEL = LDO2 Output voltage of Low-level (1) VOL1 IGPO1, GPO2, GPIO1, GPIO2, INT = 2 mA VDDSEL = LDO2 (IGPO1, GPO2, GPIO1, GPIO2, INT = 0.5 mA ) Output voltage of High-level (2) VOL2 IGPO1, GPO2, GPIO1, GPIO2, INT = – 2 mA VDDSEL = LDO1 VOL2 IGPO1, GPO2, GPIO1, GPIO2, INT = 2 mA VDDSEL = LDO1 (IGPO1, GPO2, GPIO1, GPIO2, INT = 0.5 mA ) Output voltage of High-level (1) Output voltage of Low-level (2) Page 12 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A ELECTRICAL CHARACTERISTICS (continued) VB = VBDCDC = VBLED = 3.6 V, VLED1 = VLED2 = 4.9 V Note) Ta = 25 C 2 C unless otherwise specified. Parameter Symbol Condition Limits Min Typ Max Unit Note LDOCNT, LEDCNT Input voltage range of Highlevel VIH High-level recognition voltage VB 0.7 VB + 0.3 V Input voltage range of Lowlevel VIL Low-level recognition voltage – 0.3 0.4 V Input current of High-level IIH VLDOCNT, LEDCNT = 3.6 V IIH = ILDOCNT, LEDCNT 0 1 A Input current of Low-level IIL VLDOCNT, LEDCNT = 0 V IIL = ILDOCNT, LEDCNT 0 1 A Input voltage range of Highlevel VIH High-level recognition voltage 2.1 3.3 V Input voltage range of Lowlevel VIL Low-level recognition voltage – 0.3 0.4 V Input current of High-level IIH VVIBCTL = 3.0 V IIH = IVIBCTL 0 1 V Input current of Low-level IIL VVIBCTL = 0 V IIL = IVIBCTL 0 1 A Output voltage of High-level VOH3 IDO = – 2 mA LDO1 0.8 V Output voltage of Low-level VOL3 IDO = 2 mA LDO1 0.2 V RPD ITEST1, TEST2, GPI1, GPI2, GPI3 = 5 A RPD = VTEST1, TEST2, GPI1, GPI2, GPI3 / 5 A 70k 100k 130k RPU IGPIO1, GPIO2 = 0 A RPU1 = VGPIO1, GPIO2 IGPIO1, GPIO2 = – 5 A RPU = ( RPU1 – VGPIO1, GPIO2 ) / 5 A 70k 100k 130k VIBCTL DO TEST1, TEST2, GPI1, GPI2, GPI3 Pull-down resistance GPIO1, GPIO2 Pull-up resistance Page 13 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A ELECTRICAL CHARACTERISTICS (continued) VB = VBDCDC = VBLED = 3.6 V, VLED1 = VLED2 = 4.9 V Note) Ta = 25 C 2 C unless otherwise specified. Parameter Symbol Condition Limits Unit Note Min Typ Max 0.36 0.40 0.44 V DC/DC converter automatic control part Detection voltage VMON Voltage which DC/DC converter turns on when the voltage of BL1, BL2, BL3, BL4, BLS1, and BLS2 terminal falls Current consumption of DC/DC converter part DC/DC control current (1) DC/DC control current (2) IDC1 Current when DC/DC converter is active. 1.2 3.0 mA IDC2 Current when DC/DC converter is inactive and the automatic control circuit is operating 0.7 1.4 mA Page 14 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A ELECTRICAL CHARACTERISTICS (continued) VB = VBDCDC = VBLED = 3.6 V, VLED1 = VLED2 = 4.9 V Ta = 25 C 2 C unless otherwise specified. Note) Parameter Symbol Condition Rise time Tsu1 Fall time Limits Unit Note Min Typ Max Time until output voltage reaches to 0 V to 90 % 250 s *3 *4 Tsd1 Time until output voltage reaches to 10 % 5 ms *3 *4 Load transient response (1) Vtr11 ILDO1 = – 50 A – 15 mA (1 s) 70 mV *4 Load transient response (2) Vtr12 ILDO1 = – 15 mA – 50 A (1 s) 70 mV *4 Output capacity range Cldo1 1.0 F *4 Output capacity ESR tolerance level Resr1 0.05 *4 Maximum output current Imax1 15 mA *5 Rise time Tsu2 Time until output voltage reaches to 0 V to 90 % 250 s *3 *4 Fall time Tsd2 Time until output voltage reaches to 10 % 5 ms *3 *4 Load transient response (1) Vtr21 ILDO2 = – 50 A – 15 mA (1 s) 70 mV *4 Load transient response (2) Vtr22 ILDO2 = – 15 mA – 50 A (1 s) 70 mV *4 Output capacity range Cldo2 1.0 F *4 Output capacity ESR tolerance level Resr2 0.05 *4 Maximum output current Imax2 15 mA *5 Voltage regulator (LDO1) Voltage regulator (LDO2) Note) *3 : Rise time and Fall time are defined as below. *4 : Typical Design Value LDOCNT Serial LDO1 90% 10% Tsu1 LDO2 Tsd1 90% 10% Tsu2 Tsd2 *5 : This IC consumes each 5mA maximum from LDO1 and LDO2 for the internal circuit. When it is used to supply external components, it must be used within 25mA load current. Page 15 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A ELECTRICAL CHARACTERISTICS (continued) VB = VBDCDC = VBLED = 3.6 V, VLED1 = VLED2 = 4.9 V Note) Ta = 25 C 2 C unless otherwise specified. Parameter Symbol Condition Min Limits Typ Max Unit Note Step-up DC/DC converter Rise time Tsu11 Time until output voltage reaches to 90 % from battery voltage 1 ms *4 *6 Fall time Tsd11 Time until output voltage reaches to 3.8 V from 4.9 V IDCDCOUT = 0 mA 1 s *4 *6 Load transient response (1) Vtrdc1 IDCDCOUT = – 50 A – 400 mA (1 s) 1 V *4 Load transient response (2) Vtrdc2 IDCDCOUT = – 400 mA – 50 A (1 s) 1 V *4 Output capacity range Cdc1 22 F *4 Output capacity ESR tolerance level Resr1 0.30 *4 Excess voltage detection voltage VOVP VLED voltage which detects excess voltage 6.2 V *4 Delay time of Excess voltage detection voltage TOVP Time after excess voltage is detected until INT is set to High from Low 12.75 ms *4 TMON Time after the voltage of BL1 to 4 / BLS1 to 2 goes under 0.4 V until it detects coincidence 3 times and DC/DC converter operates. 2.0 ms *4 Tdet Temperature which LDO1, LDO2, DC/DC, Constant current circuit, Matrix SW and RGB turns off. 160 C *4 *7 Returning temperature 110 C *4 *8 Delay time of Constant voltage circuit monitor TSD (Thermal shutdown circuit) Detection temperature Return temperature Note) Tsd11 *4 : Typical Design Value *6, *7, *8 : Refer to the next page Page 16 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A ELECTRICAL CHARACTERISTICS (continued) VB = VBDCDC = VBLED = 3.6 V, VLED1 = VLED2 = 4.9 V Note) Ta = 25 C 2 C unless otherwise specified. Note) *6 : VLF4012AT-4R7M1R1-7 DCDCOUT 4.7 H VBATT 10 F 22 F Ceramics PSLA21A106M x 2 PSLB31A226M CPH5811 VBDCDC LX 0.3 Serial FB DCDC DCDCGND VLED1 VLED2 Serial 90% DCDCOUT 10% Rise time Fall time *7: LDO1, LDO2, DC/DC converter, Constant current circuit, and Matrix SW and RGB are turned off when TSD is High. When TSD is High, the register is set as 14hD 1 = 1. However, data can be read only when the register is read immediately after INT occurs since internal regulator is turned off. *8: Only LDO1 and LDO2 return after ON state of TSD. A logic part will be in Reset state. Page 17 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A ELECTRICAL CHARACTERISTICS (continued) VB = VBDCDC = VBLED = 3.6 V, VLED1 = VLED2 = 4.9 V Note) Ta = 25 C 2 C unless otherwise specified. Parameter Symbol Limits Condition Min Typ Max Unit Note Microcomputer interface characteristic (Vdd = 1.85 V 3%) CLK cycle time tscyc1 — — 125 — ns *4 CLK cycle time High period twhc1 — — 60 — ns *4 CLK cycle time Low period twlc1 — — 60 — ns *4 Serial-data setup time tss1 — — 62 — ns *4 Serial-data hold time tsh1 — — 62 — ns *4 Transceiver interval tcsw1 — — 62 — ns *4 Chip enable setup time tcss1 — — 5 — ns *4 Chip enable hold time tcgh1 — — 5 — ns *4 tdodly1 Only READ — 25 — ns *4 DC delay time Note) *4 : Typical Design Value Microcomputer interface Timing chart tcgh1 CSB tscyc1 tcss1 twhc1 tcsw1 twlc1 CLK DI tss1 tsh1 DO tdodly1 Page 18 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A ELECTRICAL CHARACTERISTICS (continued) VB = VBDCDC = VBLED = 3.6 V, VLED1 = VLED2 = 4.9 V Note) Ta = 25 C 2 C unless otherwise specified. Parameter Symbol Limits Condition Min Typ Max Unit Note SPI2 format Microcomputer interface characteristic (Vdd = 1.85 V 3%) BLSCLK cycle time tscyc2 — — 125 — ns *4 BLSCLK cycle time High period twhc2 — — 60 — ns *4 BLSCLK cycle time Low period Twlc2 — — 60 — ns *4 Serial-data setup time tss2 — — 62 — ns *4 Serial-data hold time tsh2 — — 62 — ns *4 Transceiver interval tcsw2 — — 62 — ns *4 BLSCE setup time tcss2 — — 5 — ns *4 BLSCE hold time tcgh2 — — 5 — ns *4 Note) *4 : Typical Design Value tcsw2 BLSCE tcss2 twhc2 tcgh2 tscyc2 BLSCLK twlc2 BLSDAT D7 D6 D5 D4 D3 D2 tss2 D1 D0 tsh2 SPI1 REG 05h SPI2 Constant current circuit LCDMAIN SERSEL SERSEL GPI1 terminal GPI2 terminal GPI3 terminal Operation 0 GPI1 operation GPI2 operation GPI3 operation GPIO operation 1 BLSCE operation BLSCLK operation BLSDAT operation SPI2 operation Page 19 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A PIN CONFIGURATION Top View 7 8 9 RGB GND1 Y0 VLED1 Y2 VLED2 Y5 R1 Y1 Y3 Y4 Y6 G1 VB LED RSTB LED CNT VREFD GPIO 2 GPIO 1 TEST 2 IREF LDO2 CLK CSB LDO1 VB RGB GND2 X6 R2 G2 B1 PGND 2 X5 B2 CHG GND X3 X4 GPI 1 PGND 1 X2 TEST 1 GPI 3 GPI 2 DI DO LDO CNT FB X0 X1 EXT CLK GPO 2 INT GPO 1 VIB CTL LX VB DCDC PL2 BL4 BL2 BL1 LED CTL PL1 BL3 LED GND1 BLS2 BLS1 J H B 6 C 5 D 4 E 3 F 2 G A 1 LED GND2 AGND DCDC GND DGND Page 20 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A PIN FUNCTIONS Pin No. Pin name Type Description G1(1) X0 Output Constant current circuit. The output terminal of PWM control. It connects with the 1st Row of matrix LED. G2(2) X1 Output Constant current circuit. The output terminal of PWM control. It connects with the 2nd Row of matrix LED. F2(3) X2 Output Constant current circuit. The output terminal of PWM control. It connects with the 3rd Row of matrix LED. E1(4) X3 Output Constant current circuit. The output terminal of PWM control. It connects with the 4th Row of matrix LED. F1(5) D1(6) PGND1 PGND2 Ground The GND terminal for matrix LED E2(7) X4 Output Constant current circuit. The output terminal of PWM control. It connects with the 5th Row of matrix LED. D2(8) X5 Output Constant current circuit. The output terminal of PWM control. It connects with the 6th Row of matrix LED. C1(9) X6 Output Constant current circuit. The output terminal of PWM control. It connects with the 7th Row of matrix LED. A3(10) Y0 Output Constant current circuit. The output terminal of PWM control. It connects with the A Column of matrix LED. B4(11) Y1 Output Constant current circuit. The output terminal of PWM control. It connects with the B Column of matrix LED. A5(12) Y2 Output Constant current circuit. The output terminal of PWM control. It connects with the C Column of matrix LED. B5(13) Y3 Output Constant current circuit. The output terminal of PWM control. It connects with the D Column of matrix LED. A4(14) A6(15) VLED1 VLED2 Power supply B6(16) Y4 Output Constant current circuit. The output terminal of PWM control. It connects with the E Column of matrix LED. A7(17) Y5 Output Constant current circuit. The output terminal of PWM control. It connects with the F Column of matrix LED. B7(18) Y6 Output Constant current circuit. The output terminal of PWM control. It connects with the G Column of matrix LED. The power supply's connect terminal for matrix LED. Connect with the output of battery or step-up DC/DC converter. Page 21 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A PIN FUNCTIONS (Continued) Pin No. Pin name Type Description F9(19) FB Input H9(20) DCDCGND Ground The GND terminal for step-up DC/DC converter. G8(21) LX Output The terminal for External Nch-type MOS-Tr Gate driver. G9(22) VBDCDC Power supply The power supply's connect terminal for step-up DC/DC converter. B3(23) R1 Output LED contact terminal. Control by LEDCNT terminal is also possible. C5(24) G1 Output LED contact terminal. C4(25) B1 Output LED contact terminal. A2(26) B1(27) RGBGND1 RGBGND2 Ground The GND terminal for RGB terminal. C2(28) R2 Output General-purpose output terminal.(Nch-MOS Open Drain) C3(29) G2 Output General-purpose output terminal.(Nch-MOS Open Drain) D3(30) B2 Output General-purpose output terminal.(Nch-MOS Open Drain) D4(31) CHGGND Output The resistance contact terminal for charge LED.(Connect current restriction resistance between this terminal and GND terminal.) C6(32) VBLED Power supply Battery voltage's connect terminal. This terminal supplies Power supply to R1 terminal and R2 terminal. C8(33) LEDCNT Input D9(34) LDO2 Output LDO2 (2.85 V) output terminal. E9(35) VB Power supply The power supply's connect terminal for BGR circuit and LDO circuit. E8(36) LDO1 Output LDO1 (1.85 V) output terminal. F8(37) LDOCNT Input C9(38) VREFD Output BGR circuit output terminal. D8(39) IREF Output The resistance connect terminal for constant current value setup. The feedback terminal for step-up DC/DC converter. ON/OFF control terminal of LED connected to R1 terminal and R2 terminal. ON/OFF control terminal of LDO1 and LDO2. Page 22 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A PIN FUNCTIONS (Continued) Pin No. Pin name Type Description J3(40) PL1 Output The constant current output terminal for LED driver. (0 to 61 mA) This terminal is driven with the same current value as PL2 terminal. H3(41) PL2 Output The constant current output terminal for LED driver. (0 to 61 mA) This terminal is driven with the same current value as PL1 terminal. J5(42) J2(43) LEDGND1 LEDGND2 Ground The GND terminal for constant current circuits for LED driver. H6(44) BL1 Output The constant current output terminal for LED driver. (0 to 31 mA) This terminal is driven with the same current value as BL2, BL3 and BL4 terminal. H5(45) BL2 Output The constant current output terminal for LED driver. (0 to 31 mA) This terminal is driven with the same current value as BL1, BL3 and BL4 terminal. J4(46) BL3 Output The constant current output terminal for LED driver. (0 to 31 mA) This terminal is driven with the same current value as BL1, BL2 and BL4 terminal. H4(47) BL4 Output The constant current output terminal for LED driver. (0 to 31 mA) This terminal is driven with the same current value as BL1, BL2 and BL3 terminal. J7(48) BLS1 Output The constant current output terminal for LED driver. (0 to 31 mA) This terminal is driven with the same current value as BLS2 terminal. J6(49) BLS2 Output The constant current output terminal for LED driver. (0 to 31 mA) This terminal is driven with the same current value as BLS1 terminal. B9(50) AGND Ground The GND terminal for Analog circuitry. G5(51) INT Output Interrupt output terminal. F3(52) TEST1 Input Test terminal. D7(53) TEST2 Input Test terminal. E7(54) CSB Input Chip-enable terminal for SPI1 interface. E6(55) CLK Input Clock input terminal for SPI1 interface. F6(56) DI Input Data input terminal for SPI1 interface. F7(57) DO Output C7(58) RSTB Input Data output terminal for SPI1 interface. Reset input terminal Page 23 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A PIN FUNCTIONS (Continued) Pin No. Pin name Type Description G3(59) EXTCLK Input J8(60) DGND Ground E3(61) GPI1 Input GPI input port terminal. (Chip-enable terminal for SPI2 interface.) F5(62) GPI2 Input GPI input port terminal. (Clock input terminal for SPI2 interface.) F4(63) GPI3 Input GPI input port terminal. (Data input terminal for SPI2 interface.) G6(64) GPO1 Output GPO output port terminal. G4(65) GPO2 Output GPO output port terminal. D6(66) GPIO1 Input / Output GPIO input/output port terminal. D5(67) GPIO2 Input / Output GPIO input/output port terminal. H7(68) LEDCTL Input LED's lighting ON/OFF control terminal. (It is based on register 0Ah.) G7(69) VIBCTL Input LED's lighting ON/OFF control terminal. (It is based on register 09h.) External clock input terminal. (It can operate by the clock frequency of a maximum of 1.44 MHz.) The GND terminal for Logic circuitry. Page 24 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A BGR TSD VBLED CHGGND B2 G2 R2 LEDCNT C8(33) C6(32) D4(31) D3(30) C3(29) C2(28) D9(34) LDO2 E9(35) VB STANDBY ON/OFF ON/OFF ON/OFF H6(44) Back light Constant current control (6-ch) RGB control DAC (6-ch) B6(16) Y4 A6(15) VLED2 SCAN VLED1 switch A4(14) (7-ch) B5(13) Y3 A5(12) Y2 CLK E6(55) DI F6(56) DO F7(57) RSTB C7(58) EXT CLK G3(59) Register Fixed pattern ROM Pattern register RAM Command decoding Level shift SPI1 BLSCE SPI2 PWM control (7-ch) GPIO BLSCLK BLSDAT GPI1 E3(61) GPI2 F5(62) GPI3 F4(63) GPO1 G6(64) GPO2 G4(65) GPIO1 D6(66) GPIO2 D5(67) LEDCTL H7(68) E7(54) DGND J8(60) CSB Step-up G8(21) LX DC/DC Converter H9(20) DCDCGND B7(18) Y6 A7(17) Y5 Level shift INT G5(51) TEST1 F3(52) D7(53) G9(22) VBDCDC F9(19) FB B9(50) TEST2 C4(25) B1 C5(24) G1 B3(23) R1 B4(11) Y1 A3(10) Y0 C1(9) X6 D2(8) X5 E2(7) X4 D1(6) PGND2 Constant F1(5) PGND1 Current control E1(4) X3 (7-ch) F2(3) X2 G2(2) X1 G1(1) X0 VIBCTL G7(69) AGND LDO1 LDO2 1.85 V/30mA 2.85 V/30mA HTSD LED J2(43) GND2 BL2 H5(45) J4(46) BL3 H4(47) BL4 J7(48) BLS1 J6(49) BLS2 E8(36) LDO1 F8(37) LDOCNT VREFD IREF DAC (2-ch) BL1 B1(27) RGBGND2 A2(26) RGBGND1 ON/OFF Photo flash Constant current control (2-ch) C9(38) D8(39) IREF J3(40) PL1 H3(41) PL2 J5(42) LEDGND1 FUNCTIONAL BLOCK DIAGRAM Notes: This block diagram is for explaining functions. Part of the block diagram may be omitted, or it may be simplified. Page 25 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION 1. Explanation of each mode ( Power supply startup sequence ) LDOCNT REG18 REG28 Itotal typ (A) Notes • It is necessary to make it LDOCNT = High for the return from OFF-mode. • RSTB = Low is forbidden at OFF-mode. (An internal circuit becomes unfixed.) • Do not impress voltage to GPI1, GPI2, GPI3, GPIO1, and GPIO2 terminal at OFF-mode. Low (Initial condition) OFF OFF <1 Low High N.C. (ON) N.C. (ON) 18 — 18 • The signal from serial interface is not received in LDOCNT = Low and the state of REG28 = Low or REG18 = Low. • It shifts to standby mode with LDOCNT = Low and REG28 = High. • The signal from serial interface is not received at Standby-mode. (Power supply for Logic is LDO1 and LDO2.) Therefore, standby release by the signal from serial interface cannot be performed. • In Standby-mode, if LDOCNT is switched to High from Low, it will return to the normal mode. • It cannot shift to OFF-mode from Standbymode. Once returning to the normal mode, please shift to OFF-mode. • RSTB = Low is prohibited in Standby-mode. (An internal circuit becomes unfixed.) • Do not impress voltage to GPI1, GPI2, GPI3, GPIO1, and GPIO2 terminal in Standby-mode. High N.C. (ON) N.C. (ON) N.C. (OFF) Low : OFF At OFF mode Low : OFF High : ON High : ON At Standby mode High Low • Regardless of the value of REG18, LDO1 turns on at LDOCNT = High. • Regardless of the value of REG28, LDO2 turns on at LDOCNT = High. • Serial interface signal is not received at RSTB < 1 (OFF mode ) = Low or • 5 ms after being set to LDOCNT = High, the 8 (Standby mode) receptionist of serial interface signal is attained. • To activate RSTB, RSTB should be kept low for more than one internal clock period. • RSTB terminal prohibits the input signal of those other than a rectangle wave. Page 26 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 1. Explanation of each mode ( Power supply startup sequence ) (continued) Shift to the Normal mode from OFF-mode LDOCNT REG18 REG28 LDO1 LDO2 RSTB over 3 ms over 5 ms A register input is possible. Shift to the Normal mode from Standby mode LDOCNT REG18 REG28 LDO1 LDO2 Low power mode RSTB over 3 ms over 5 ms A register input is possible. * This is the waveform in the case of applying reset to register setup at Standby mode. * Maintain the state of RSTB = High to hold the register setup. Page 27 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 1. Explanation of each mode ( Power supply startup sequence ) (continued) Shift to the OFF-mode from Normal mode Over 1 ms LDOCNT REG18 Set REG18 and REG28 to Low before LDOCNT. REG28 LDO1 LDO2 RSTB A register input is possible. Over 3 ms Shift to the Standby mode from Normal mode Over 1 ms LDOCNT Set REG18 to Low before LDOCNT. REG18 REG28 LDO1 LDO2 Low power mode RSTB A register input is possible. Page 28 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 2. Explanation of operation Matrix part operation waveform The following waveform is an internal signal. In following Yx = Xx = Low, the waveform of actual Yx terminal is set to Hi-Z. 945clk (787.5 s) 8clk (6.67 s) Y0 Y1 Y2 Y3 Y4 Y5 Y6 X0 to X6 Minimum width of PWM 63clk (52.5 s) 6671clk (About 180.83 Hz) Page 29 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 2. Explanation of operation (continued) Explanation of excess voltage protection circuit of operation Latch release will be carried out if serial DDSW is set to Low. V LDO2 Serial DDSW 0V Time FB terminal is open V VB LX 0V Time V DCDC Output 6.2 V 4.9 V FB VB 0V About 8 ms The shut after about 13 ms after DC/DC output voltage is set to about 6.2 V. About 13 ms Time V LDO2 Internal shutdown signal 0V Time Page 30 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 2. Explanation of operation (continued) Explanation of over-current protection circuit of operation Latch release will be carried out if serial DDSW is set to Low. V LDO2 Serial DDSW 0V DC/DC output is short-circuited to GND. V Time VB LX 0V Time V DCDC Output FB About 8 ms 4.9V VB 0V V Internal error amplifier output voltage A shutdown is generated, when the output voltage of internal error amplifier goes up, and duty MAX state is set to about 13 ms or more. Time About 13 ms 0V Time V LDO2 Internal shutdown signal 0V Time Page 31 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 3. Block configuration RESET part block configuration VB VBATT VREFD ON/OFF BGR TSD HTSD 1 F LDOCNT LDO2 LDO2 2.85 V 1 F LDO1 LDO1 1.85 V ON/OFF STANDBY ON/OFF ON/OFF 1 F LDO1 LDO2 CE CLK LEVEL SHIFT DI LDO2 VB Register REG18 DO RST REG28 LEVEL SHIFT LDO1 LDO2 RSTB LEVEL SHIFT LDO2 All the logic portions to which the power supply is not connected are connected to VB as power supplies. Page 32 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 3. Block configuration (continued) The LED part for charge block configuration VBLED VBATT VLF4012 4.7 H LX CPH5811 DC/DC FB 22 F VLED1 VLED2 0.3 100 k R1 GNDCHG *R DGND LEDCNT[VB] DDSW This function cannot be used when DC/DC converter is active. All the logic portions to which the power supply is not connected are connected to VB as power supplies. Adjust R value with the LED and current you use. Page 33 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 3. Block configuration (continued) Explanation of matrix LED part, matrix LED’s number The connected terminal name X0 1 X1 2 X2 3 X3 4 X4 5 X5 6 X6 7 Y0 Y1 Y2 Y3 Y4 Y5 Y6 A B C D E F G LED’s number LED’s number Page 34 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 4. Register and Address Register Map Sub Address R/W Data Name 01h W 02h DATA D7 D6 D5 D4 D3 D2 D1 D0 POWE RCNT — — — — VFOFF OSCEN DCOSE L DDSW W LDOC NT — — — — — — REG18 REG28 03h W SERS EL — — — — — — — SERSE L 04h R LSIVE R 05h W LCDM AIN — — — LCDMAIN[4:0] 06h W LCDSU B — — — LCDSUB[4:0] 07h W PLCNT — — HIEN PLCNT[4:0] 08h W PWMC NT — BL1M BL2M BL3M BL4M BLS1M BLS2M PWMC LK 09h W VIBCT L VIBA CT VIBPL 1 VIBPL 2 VIBSU B1 VIBSU B2 VIBMT X VIBRG B1 — 0Ah W LEDCT L LEDA CT DISPL 1 DISPL 2 DISSU B1 DISSU B2 DISMT X DISRG B1 — 10h W/R GPIOC NT — — — — — — — GPIOC LK 11h W/R IOSEL — — — — — — IOSEL1 IOSEL2 12h W/R IOMSK — — — IMSK1 IMSK2 IMSK3 IOMSK 1 IMSK2 13h W/R IOOUT — — — — OOUT1 OOUT2 IOOUT 1 IOOUT 2 14h R IOFAC TOR FACG D1 ERR2 EH — — RAMA CT FRMIN T CPUW RER TSD 15h R IOSTA TE STAG D — — ISTA1 ISTA2 ISTA3 IOSTA1 IOSTA2 16h W/R ICHAT — — 17h W/R IOCHA T — — — 18h W/R IODET — — 19h W/R IOPLU D — 1Ah W/R VDDS EL INTVS EL LSIVER[7:0] ICHAT1[1:0] ICHAT2[1:0] ICHAT3[1:0] — IOCHAT1[1:0] IOCHAT2[1:0] — — IDET[1:0] IODET[1:0] — — R2ON G2ON B2ON IOPLU D1 IOPLU D2 — — — OVSEL 1 OVSEl2 IOVSE L1 IOVSE L2 Page 35 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 4. Register and Address (continued) Register Map (continued) DATA Sub Address R/W Data Name D7 D6 D5 D4 D3 D2 D1 D0 20h R/W MTXON — — — — — — — MTXON 21h R/W MTXDATA 22h R/W FFROM 23h R/W ROMSEL 24h R/W RAMCOPY 25h R/W SETFROM SETFROM[7:0] 26h R/W SETTO SETTO[7:0] 27h R/W REPON — — — — 28h R/W SETTIME — — — 29h R/W RAMRST — — 2Ah R/W SCROLL — 2Bh R/W SCLTIME 2Ch R/W 2Dh MTXDATA[7:0] — — — — — — ROM77[1:0] SELROM[7:0] — SELR AM COPYSTA RT — — — REPON — — — — — — — RAM1 RAM2 — — — — — — SCLON — — — — — — RGBON — — — — — — R/W RGBDATA — — 2Eh R ERROR FACG D2 SCP OVP IFAC1 IFAC2 30h R/W RAMNUM — — — — 6Bh R/W PROT1 — — — 6Dh R/W PROT2 — — 6Fh R/W PROT3 PROT 3 — 70h R/W TEST1 TEST1 71h R/W TEST2 TEST2 72h R/W TEST3 TEST3 73h R/W TEST4 TEST4 74h R/W TEST5 TEST5 75h R/W TEST6 TEST6 76h R/W TEST7 TEST6 77h R/W TEST8 TEST7 — — — — — SETTIME[1:0] SCLTIME[1:0] — RGBON IFAC3 IOFA C1 IOFAC2 — — — RAMNUM — — — — PROT1 — PROT 2 — — — — — — — — — — RGBDATA[5:0] Page 36 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 4. Register and Address (continued) RAM Address Map DATA Sub Address Data Name 31h A1 BLA1[3:0] FRA1[1:0] DLA1[1:0] 32h A2 BLA2[3:0] FRA2[1:0] DLA2[1:0] 33h A3 BLA3[3:0] FRA3[1:0] DLA3[1:0] 34h A4 BLA4[3:0] FRA4[1:0] DLA4[1:0] 35h A5 BLA5[3:0] FRA5[1:0] DLA5[1:0] 36h A6 BLA6[3:0] FRA6[1:0] DLA6[1:0] 37h A7 BLA7[3:0] FRA7[1:0] DLA7[1:0] 38h B1 BLB1[3:0] FRB1[1:0] DLB1[1:0] 39h B2 BLB2[3:0] FRB2[1:0] DLB2[1:0] 3Ah B3 BLB3[3:0] FRB3[1:0] DLB3[1:0] 3Bh B4 BLB4[3:0] FRB4[1:0] DLB4[1:0] 3Ch B5 BLB5[3:0] FRB5[1:0] DLB5[1:0] 3Dh B6 BLB6[3:0] FRB6[1:0] DLB6[1:0] 3Eh B7 BLB7[3:0] FRB7[1:0] DLB7[1:0] 3Fh C1 BLC1[3:0] FRC1[1:0] DLC1[1:0] 40h C2 BLC2[3:0] FRC2[1:0] DLC2[1:0] 41h C3 BLC3[3:0] FRC3[1:0] DLC3[1:0] 42h C4 BLC4[3:0] FRC4[1:0] DLC4[1:0] 43h C5 BLC5[3:0] FRC5[1:0] DLC5[1:0] 44h C6 BLC6[3:0] FRC6[1:0] DLC6[1:0] 45h C7 BLC7[3:0] FRC7[1:0] DLC7[1:0] 46h D1 BLD1[3:0] FRD1[1:0] DLD1[1:0] 47h D2 BLD2[3:0] FRD2[1:0] DLD2[1:0] 48h D3 BLD3[3:0] FRD3[1:0] DLD3[1:0] 49h D4 BLD4[3:0] FRD4[1:0] DLD4[1:0] 4Ah D5 BLD5[3:0] FRD5[1:0] DLD5[1:0] 4Bh D6 BLD6[3:0] FRD6[1:0] DLD6[1:0] 4Ch D7 BLD7[3:0] FRD7[1:0] DLD7[1:0] D7 D6 D5 D4 D3 D2 D1 D0 Page 37 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 4. Register and Address (continued) RAM Address Map (continued) DATA Sub Address Data Name 4Dh E1 BLE1[3:0] FRE1[1:0] DLE1[1:0] 4Eh E2 BLE2[3:0] FRE2[1:0] DLE2[1:0] 4Fh E3 BLE3[3:0] FRE3[1:0] DLE3[1:0] 50h E4 BLE4[3:0] FRE4[1:0] DLE4[1:0] 51h E5 BLE5[3:0] FRE5[1:0] DLE5[1:0] 52h E6 BLE6[3:0] FRE6[1:0] DLE6[1:0] 53h E7 BLE7[3:0] FRE7[1:0] DLE7[1:0] 54h F1 BLF1[3:0] FRF1[1:0] DLF1[1:0] 55h F2 BLF2[3:0] FRF2[1:0] DLF2[1:0] 56h F3 BLF3[3:0] FRF3[1:0] DLF3[1:0] 57h F4 BLF4[3:0] FRF4[1:0] DLF4[1:0] 58h F5 BLF5[3:0] FRF5[1:0] DLF5[1:0] 59h F6 BLF6[3:0] FRF6[1:0] DLF6[1:0] 5Ah F7 BLF7[3:0] FRF7[1:0] DLF7[1:0] 5Bh G1 BLG1[3:0] FRG1[1:0] DLG1[1:0] 5Ch G2 BLG2[3:0] FRG2[1:0] DLG2[1:0] 5Dh G3 BLG3[3:0] FRG3[1:0] DLG3[1:0] 5Eh G4 BLG4[3:0] FRG4[1:0] DLG4[1:0] 5Fh G5 BLG5[3:0] FRG5[1:0] DLG5[1:0] 60h G6 BLG6[3:0] FRG6[1:0] DLG6[1:0] 61h G7 BLG7[3:0] FRG7[1:0] DLG7[1:0] 62h LEDR1 BLLEDR1[3:0] FRLEDR1[1:0] DLLEDR1[1:0] 63h LEDG1 BLLEDG1[3:0] FRLEDG1[1:0] DLLEDG1[1:0] 64h LEDB1 BLLEDB1[3:0] FRLEDB1[1:0] DLLEDB1[1:0] D7 D6 D5 D4 D3 D2 D1 D0 Page 38 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 4. Register and Address (continued) ROM Address Map [00000000] - [10010101] : ROM(Only luminosity) 7 7 Pattern No.0 (default) to Pattern No.149 Pattern No. Contents of the pattern Display Pattern No. Contents of the pattern Display 0 All putting out lights Nothing 31 Alphabetic character U 1 Number 0 32 Alphabetic character V 2 Number 1 33 Alphabetic character W 3 Number 2 34 Alphabetic character X 4 Number 3 35 Alphabetic character Y 5 Number 4 36 Alphabetic character Z 6 Number 5 37 Alphabetic character a 7 Number 6 38 Alphabetic character b 8 Number 7 39 Alphabetic character c 9 Number 8 40 Alphabetic character d 10 Number 9 41 Alphabetic character e 11 Alphabetic character A 42 Alphabetic character f 12 Alphabetic character B 43 Alphabetic character g 13 Alphabetic character C 44 Alphabetic character h 14 Alphabetic character D 45 Alphabetic character i 15 Alphabetic character E 46 Alphabetic character j 16 Alphabetic character F 47 Alphabetic character k 17 Alphabetic character G 48 Alphabetic character l 18 Alphabetic character H 49 Alphabetic character m 19 Alphabetic character I 50 Alphabetic character n 20 Alphabetic character J 51 Alphabetic character o 21 Alphabetic character K 52 Alphabetic character p 22 Alphabetic character L 53 Alphabetic character q 23 Alphabetic character M 54 Alphabetic character r 24 Alphabetic character N 55 Alphabetic character s 25 Alphabetic character O 56 Alphabetic character t 26 Alphabetic character P 57 Alphabetic character u 27 Alphabetic character Q 58 Alphabetic character v 28 Alphabetic character R 59 Alphabetic character w 29 Alphabetic character S 60 Alphabetic character x 30 Alphabetic character T 61 Alphabetic character y Page 39 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 4. Register and Address (continued) ROM Address Map (continued) [00000000] - [10010101] : ROM(Only luminosity) 7 7 Pattern No.0 (default) to Pattern No.149 Pattern No. Contents of the pattern Display Pattern No. Contents of the pattern Display 62 Alphabetic character z 93 Katakana ノ 63 Katakana ア 94 Katakana ハ 64 Katakana ァ 95 Katakana ヒ 65 Katakana イ 96 Katakana フ 66 Katakana ィ 97 Katakana へ 67 Katakana ウ 98 Katakana ホ 68 Katakana ゥ 99 Katakana マ 69 Katakana エ 100 Katakana ミ 70 Katakana ェ 101 Katakana ム 71 Katakana オ 102 Katakana メ 72 Katakana ォ 103 Katakana モ 73 Katakana カ 104 Katakana ヤ 74 Katakana キ 105 Katakana ャ 75 Katakana ク 106 Katakana ユ 76 Katakana ケ 107 Katakana ュ 77 Katakana コ 108 Katakana ヨ 78 Katakana サ 109 Katakana ョ 79 Katakana シ 110 Katakana ラ 80 Katakana ス 111 Katakana リ 81 Katakana セ 112 Katakana ル 82 Katakana ソ 113 Katakana レ 83 Katakana タ 114 Katakana ロ 84 Katakana チ 115 Katakana ワ 85 Katakana ツ 116 Katakana ヲ 86 Katakana ッ 117 Katakana ン 87 Katakana テ 118 Symbol ゛ 88 Katakana ト 119 Symbol ゜ 89 Katakana ナ 120 Symbol ー 90 Katakana ニ 121 Symbol Heart 91 Katakana ヌ 122 Symbol Mail 92 Katakana ネ 123 Symbol Telephone Page 40 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 4. Register and Address (continued) ROM Address Map (continued) [00000000] - [10010101] : ROM(Only luminosity) 7 7 Pattern No.0 (default) to Pattern No.149 Pattern No. Contents of the pattern Display Pattern No. Contents of the pattern Display 124 Symbol Zero antenna 144 Symbol 125 Symbol One antenna 145 Symbol △ 126 Symbol Two antenna 146 Symbol □ 127 Symbol Three antenna 147 Symbol ◇ 128 Symbol + 148 Symbol ▽ 129 Symbol 149 Symbol ¥ 130 Symbol 131 Symbol 132 Symbol = 133 Symbol : 134 Symbol ! 135 Symbol ? 136 Symbol 137 Symbol 138 Symbol 139 Symbol 140 Symbol 〒 141 Symbol Clock mark 142 Symbol ♪ 143 Symbol ○ Page 41 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 4. Register and Address (continued) ROM Address Map (continued) [10010110] - [11010000] : ROM(Luminosity Cycle Delay) 7 7 Pattern No.150 to Pattern No.208 Pattern No. Contents of the pattern Display Pattern No. Contents of the pattern Display 150 Gradation Square out 1 s 174 Gradation Right 1 s 151 Gradation Square out 2 s 175 Gradation Right 2 s 152 Gradation Square out 3 s 176 Gradation Right 3 s 153 Gradation Square in 1 s 177 Gradation Left 1 s 154 Gradation Square in 2 s 178 Gradation Left 2 s 155 Gradation Square in 3 s 179 Gradation Left 3 s 156 Gradation Slant right down 1 s 180 Gradation Slant right center 1 s 157 Gradation Slant right down 2 s 181 Gradation Slant right center 2 s 158 Gradation Slant right down 3 s 182 Gradation Slant right center 3 s 159 Gradation Slant left down 1 s 183 Gradation Slant left center 1 s 160 Gradation Slant left down 2 s 184 Gradation Slant left center 2 s 161 Gradation Slant left down 3 s 185 Gradation Slant left center 3 s 162 Gradation Slant right up 1 s 186 Gradation Vertical center 1 s 163 Gradation Slant right up 2 s 187 Gradation Vertical center 2 s 164 Gradation Slant right up 3 s 188 Gradation Vertical center 3 s 165 Gradation Slant left up 1 s 189 Gradation Side center 1 s 166 Gradation Slant left up 2 s 190 Gradation Side center 2 s 167 Gradation Slant left up 3 s 191 Gradation Side center 3 s 168 Gradation Down 1 s 192 Gradation Square right down 1 s 169 Gradation Down 2 s 193 Gradation Square right down 2 s 170 Gradation Down 3 s 194 Gradation Square right down 3 s 171 Gradation Up 1 s 172 Gradation Up 2 s 173 Gradation Up 3 s Page 42 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 4. Register and Address (continued) ROM Address Map (continued) [10010110] - [11010000] : ROM(Luminosity Cycle Delay) 7 7 Pattern No.150 to Pattern No.208 Pattern No. Contents of the pattern Display 195 Gradation Square left down 1 s 196 Gradation Square left down 2 s 197 Gradation Square left down 3 s 198 Gradation Square right up 1 s 199 Gradation Square right up 2 s 200 Gradation Square right up 3 s 201 Gradation Square left up 1 s 202 Gradation Square left up2 s 203 Gradation Square left up 3 s 204 Gradation Square crossing in 1 s 205 Gradation Square crossing in 2 s 206 Gradation Square crossing in 3 s 207 Gradation Square crossing out1 s 208 Gradation Square crossing out2 s Page 43 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 4. Register and Address (continued) ROM Address Map (continued) [000001] - [101010] : ROM(RGB pattern, Luminosity Cycle Delay )RGB pattern No.1 to No.42 Pattern No. Contents of the pattern Display Pattern No. Contents of the pattern Display 1 Color 1 Turn on : Blue 25 Color 1 Firefly 2 s Firefly 2 s : Color 1 2 Color 2 Turn on : Between 1 and 3 26 Color 2 Firefly 2 s Firefly 2 s : Color 2 27 Color 3 Firefly 2 s Firefly 2 s : Color 3 3 Color 3 Turn on : Green + Blue 28 Color 4 Firefly 2 s Firefly 2 s : Color 4 4 Color 4 Turn on : Between 3 and 5 29 Color 5 Firefly 2 s Firefly 2 s : Color 5 5 Color 5 Turn on : Green 30 Color 6 Firefly 2 s Firefly 2 s : Color 6 31 Color 7 Firefly 2 s Firefly 2 s : Color 7 6 Color 6 Turn on : Between 5 and 7 32 Color 8 Firefly 2 s Firefly 2 s : Color 8 7 Color 7 Turn on : Red + Green 33 Color 9 Firefly 2 s Firefly 2 s : Color 9 Color 10 Firefly 2 s Firefly 2 s : Color 10 Color 8 Turn on : Between 7 and 9 34 8 35 Color 11 Firefly 2 s Firefly 2 s : Color 11 9 Color 9 Turn on : Red 36 Color 12 Firefly 2 s Firefly 2 s : Color 12 10 Color 10 Turn on : Red + Blue 37 Gradation 1 Gradation 1 Gradation 2 Gradation 2 Color 11 Turn on : Between 9 and 10 38 11 39 Gradation 3 Gradation 3 Gradation 4 Gradation 4 Color 12 Turn on : Red + Blue + Green 40 12 41 Gradation 5 Gradation 5 13 Color 1 Firefly 1 s Firefly 1 s : Color 1 42 Gradation 6 Gradation 6 14 Color 2 Firefly 1 s Firefly 1 s : Color 2 15 Color 3 Firefly 1 s Firefly 1 s : Color 3 16 Color 4 Firefly 1 s Firefly 1 s : Color 4 17 Color 5 Firefly 1 s Firefly 1 s : Color 5 18 Color 6 Firefly 1 s Firefly 1 s : Color 6 19 Color 7 Firefly 1 s Firefly 1 s : Color 7 20 Color 8 Firefly 1 s Firefly 1 s : Color 8 21 Color 9 Firefly 1 s Firefly 1 s : Color 9 22 Color 10 Firefly 1 s Firefly 1 s : Color 10 23 Color 11 Firefly 1 s Firefly 1 s : Color 11 24 Color 12 Firefly 1 s Firefly 1 s : Color 12 Page 44 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 4. Register and Address (continued) Register table which needs a clock About the following addresses, even if an internal clock or an external clock does not exist, Read / Write is possible in the data to register. However, it cannot be given to operation finally needed. Sub Address R/W Data Name 01h W 05h DATA D7 D6 D5 D4 D3 D2 D1 D0 POWERCNT — — — — VF OFF OSC EN DCO SEL DDS W W LCDMAIN — — — LCDMAIN[4:0] 06h W LCDSUB — — — LCDSUB[4:0] 07h W PLCNT — — HIEN PLCNT[4:0] 12h W/R IOMSK — — — IMSK1 IMSK 2 IMSK 3 IOMSK1 IMSK 2 14h R IOFACTOR FACGD 1 ERR2EH — — RAM ACT FRM INT CPU WRER TSD 15h R IOSTATE STAGD — — ISTA1 ISTA 2 ISTA3 IOSTA1 IOST A2 16h W/R ICHAT — — ICHAT1[1:0] 17h W/R IOCHAT — — — 18h W/R IODET — — — ICHAT2[1:0] ICHAT3[1:0] — IOCHAT1[1:0] IOCHAT2[1:0] — IDET[1:0] IODET[1:0] Page 45 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 4. Register and Address (continued) Register table which needs a clock (continued) About the following addresses, even if an internal clock or an external clock does not exist, Read / Write is possible in the data to register. However, it cannot be given to operation finally needed. DATA Sub Address R/W Data Name 20h R/W MTXON 21h R/W MTXDATA 22h R/W FFROM 23h R/W ROMSEL 24h R/W RAMCOPY 25h R/W SETFROM SETFROM[7:0] 26h R/W SETTO SETTO[7:0] 27h R/W REPON — — — — 28h R/W SETTIME — — — 29h R/W RAMRST — — 2Ah R/W SCROLL — 2Bh R/W SCLTIME 2Ch R/W 2Dh D7 D6 D5 D4 D3 D2 D1 D0 — — — — — — — MTXON MTXDATA[7:0] — — — — — — ROM77[1:0] SELROM[7:0] — SEL RAM COPY START — — — REPON — — — — — — — RAM1 RAM2 — — — — — — SCLON — — — — — — RGBON — — — — — — R/W RGBDATA — — 2Eh R ERROR FACGD2 SCP OVP IFAC1 IFAC2 30h R/W RAMNUM — — — — — — — — — — SETTIME[1:0] SCLTIME[1:0] — RGBON IFAC3 IOFAC 1 IOFAC2 — — RAMNUM RGBDATA[5:0] Page 46 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 4. Register and Address (continued) Register table which needs a clock (continued) About the following addresses, when an internal clock or an external clock does not exist, data cannot be Read / Write in at register. DATA Sub Address Data Name 31h A1 BLA1[3:0] FRA1[1:0] DLA1[1:0] 32h A2 BLA2[3:0] FRA2[1:0] DLA2[1:0] 33h A3 BLA3[3:0] FRA3[1:0] DLA3[1:0] 34h A4 BLA4[3:0] FRA4[1:0] DLA4[1:0] 35h A5 BLA5[3:0] FRA5[1:0] DLA5[1:0] 36h A6 BLA6[3:0] FRA6[1:0] DLA6[1:0] 37h A7 BLA7[3:0] FRA7[1:0] DLA7[1:0] 38h B1 BLB1[3:0] FRB1[1:0] DLB1[1:0] 39h B2 BLB2[3:0] FRB2[1:0] DLB2[1:0] 3Ah B3 BLB3[3:0] FRB3[1:0] DLB3[1:0] 3Bh B4 BLB4[3:0] FRB4[1:0] DLB4[1:0] 3Ch B5 BLB5[3:0] FRB5[1:0] DLB5[1:0] 3Dh B6 BLB6[3:0] FRB6[1:0] DLB6[1:0] 3Eh B7 BLB7[3:0] FRB7[1:0] DLB7[1:0] 3Fh C1 BLC1[3:0] FRC1[1:0] DLC1[1:0] 40h C2 BLC2[3:0] FRC2[1:0] DLC2[1:0] 41h C3 BLC3[3:0] FRC3[1:0] DLC3[1:0] 42h C4 BLC4[3:0] FRC4[1:0] DLC4[1:0] 43h C5 BLC5[3:0] FRC5[1:0] DLC5[1:0] 44h C6 BLC6[3:0] FRC6[1:0] DLC6[1:0] 45h C7 BLC7[3:0] FRC7[1:0] DLC7[1:0] 46h D1 BLD1[3:0] FRD1[1:0] DLD1[1:0] 47h D2 BLD2[3:0] FRD2[1:0] DLD2[1:0] 48h D3 BLD3[3:0] FRD3[1:0] DLD3[1:0] 49h D4 BLD4[3:0] FRD4[1:0] DLD4[1:0] 4Ah D5 BLD5[3:0] FRD5[1:0] DLD5[1:0] 4Bh D6 BLD6[3:0] FRD6[1:0] DLD6[1:0] 4Ch D7 BLD7[3:0] FRD7[1:0] DLD7[1:0] D7 D6 D5 D4 D3 D2 D1 D0 Page 47 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 4. Register and Address (continued) Register table which needs a clock (continued) About the following addresses, when an internal clock or an external clock does not exist, data cannot be Read / Write in at register. DATA Sub Address Data Name 4Dh E1 BLE1[3:0] FRE1[1:0] DLE1[1:0] 4Eh E2 BLE2[3:0] FRE2[1:0] DLE2[1:0] 4Fh E3 BLE3[3:0] FRE3[1:0] DLE3[1:0] 50h E4 BLE4[3:0] FRE4[1:0] DLE4[1:0] 51h E5 BLE5[3:0] FRE5[1:0] DLE5[1:0] 52h E6 BLE6[3:0] FRE6[1:0] DLE6[1:0] 53h E7 BLE7[3:0] FRE7[1:0] DLE7[1:0] 54h F1 BLF1[3:0] FRF1[1:0] DLF1[1:0] 55h F2 BLF2[3:0] FRF2[1:0] DLF2[1:0] 56h F3 BLF3[3:0] FRF3[1:0] DLF3[1:0] 57h F4 BLF4[3:0] FRF4[1:0] DLF4[1:0] 58h F5 BLF5[3:0] FRF5[1:0] DLF5[1:0] 59h F6 BLF6[3:0] FRF6[1:0] DLF6[1:0] 5Ah F7 BLF7[3:0] FRF7[1:0] DLF7[1:0] 5Bh G1 BLG1[3:0] FRG1[1:0] DLG1[1:0] 5Ch G2 BLG2[3:0] FRG2[1:0] DLG2[1:0] 5Dh G3 BLG3[3:0] FRG3[1:0] DLG3[1:0] 5Eh G4 BLG4[3:0] FRG4[1:0] DLG4[1:0] 5Fh G5 BLG5[3:0] FRG5[1:0] DLG5[1:0] 60h G6 BLG6[3:0] FRG6[1:0] DLG6[1:0] 61h G7 BLG7[3:0] FRG7[1:0] DLG7[1:0] 62h LEDR1 BLLEDR1[3:0] FRLEDR1[1:0] DLLEDR1[1:0] 63h LEDG1 BLLEDG1[3:0] FRLEDG1[1:0] DLLEDG1[1:0] 64h LEDB1 BLLEDB1[3:0] FRLEDB1[1:0] DLLEDB1[1:0] D7 D6 D5 D4 D3 D2 D1 D0 Page 48 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 4. Register and Address (continued) Register map detailed explanation Sub Address 01h DATA D7 D6 D5 D4 D3 D2 D1 D0 Data Name — — — — VFOFF OSCEN DCOSEL DDSW Default 0 0 0 0 0 0 0 0 mode W W W W W W W W D3 : VFOFF DC/DC converter automatic control selection bit [0] : The automatic control of DC/DC converter is possible. (default) [1] : The automatic control of DC/DC converter is impossible. * The constant current terminal which acts as a monitor is chosen by BL1M, BL2M, BL3M, BL4M, BLS1M, and BLS2M bit of address 08h at VFOFF = Low. And if it is less than 0.4 V, DC/DC converter will be activated. D2 : OSCEN The ON/OFF bit for internal oscillators [0] : Internal oscillating circuit is OFF (default) [1] : Internal oscillating circuit is ON * The variation width of an internal oscillator is set to 0.96MHz - 1.44 MHz. * The variation width of an internal clock is set to 694.4 ns – 1042 ns. D1 : DCOSEL DC/DC converter output voltage setup [0] : Output voltage set to 4.9 V (default) [1] : Output voltage set to 5.3 V D0 : DDSW The ON/OFF bit for DC/DC converter [0] : DC/DC converter is OFF (default) [1] : DC/DC converter is ON * Set both bits of DDSW and OSCEN to [1] to operate DC/DC converter. * Make sure to set both bits of OSCEN and DDSW to [1]. * During OSCEN = [1] , DDSW must be set to [1]. Page 49 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 4. Register and Address (continued) Register map detailed explanation (continued) Sub Address 02h DATA D7 D6 D5 D4 D3 D2 D1 D0 Data Name — — — — — — REG18 REG28 Default 0 0 0 0 0 0 1 1 mode W W W W W W W W D1 : REG18 The ON/OFF control for LDO1(When LDOCNT terminal is Low) [0] : LDO1 OFF [1] : LDO1 ON (default) D0 : REG28 The ON/OFF control for LDO2( When LDOCNT terminal is Low ) [0] : LDO2 OFF [1] : LDO2 ON (default) * When LDOCNT terminal is High, regardless of the state of REG18, LDO1 will be activated. * When LDOCNT terminal is High, regardless of the state of REG28, LDO2 will be activated. * Set LDOCNT to Low after setting REG28 to Low to put into OFF mode. LDOCNT REG18 REG28 Itotal typ(mA) Note Low (Initial condition) OFF OFF <1 * Low High N.C. (ON) N.C. (ON) 18 — High N.C. (ON) N.C. (ON) 18 * N.C. (OFF) Low : OFF At OFF mode Low : OFF High : ON High : ON At Standby mode <1 (OFF mode) or 8 (Standby mode) * High Low Note) * : Explanation in each mode (Power supply starting sequence) of Page 26. Refer to the note. Page 50 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 4. Register and Address (continued) Register map detailed explanation (continued) DATA Sub Address D7 D6 D5 D4 D3 D2 D1 D0 Data Name — — — — — — — SERSEL Default 0 0 0 0 0 0 0 0 mode W W W W W W W W 03h D0 : SERSEL The serial interface change which controls LCDMAIN luminosity control. [0] : GPIO operation (default) [1] : Serial control of address 05h (LCDMAIN) by SPI2 * GPI1 to GPI3 terminals serve as an input setup and an interruption mask compulsorily at SERSEL = High setup. SPI1 REG 05h SPI2 Constant current circuit LCDMAIN SERSEL SERSEL GPI1 terminal GPI2 terminal GPI3 terminal Operation 0 GPI1 operation GPI2 operation GPI3 operation GPIO operation 1 BLSCE operation BLSCLK operation BLSDAT operation SPI2 operation Page 51 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 4. Register and Address (continued) Register map detailed explanation (continued) Sub Address DATA D7 D6 D5 D3 D2 D1 D0 LSIVER[7:0] Data Name 04h D4 Default 0 0 0 0 0 0 0 0 mode R R R R R R R R D7-0 : LSIVER[7:0] The register showing the version of LSI [00000000] : ES1 [00000001] : ES2 : : Page 52 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 4. Register and Address (continued) Register map detailed explanation (continued) DATA Sub Address 05h D7 D6 D5 D4 D3 Data Name — — — Default 0 0 0 0 0 mode W W W W W D2 D1 D0 0 0 0 W W W LCDMAIN[4:0] D4-0 : LCDMAIN[4:0] Output current setup of BL1-BL4 terminal [00000] : 0 mA (default) [00001] : 1 mA [00010] : 2 mA : : [11110] : 30 mA [11111] : 31 mA The waveform of main LCD backlights current of operation * As for main LCD backlights part, output current changes stepwise for noise reduction. * By the time it reaches current setup value, there will be delay of setup value internal 32clk. * When internal CLK stops during state transition, the state at that time is held. * The following waveform is internal signal. 32clk 8step 32clk Internal luminosity set point signal (typ26.6 s) 01000 00111 00110 00101 00100 00011 00010 00001 00000 0000001000 t 01000 00011 Page 53 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 4. Register and Address (continued) Register map detailed explanation (continued) DATA Sub Address 06h D7 D6 D5 D4 D3 Data Name — — — Default 0 0 0 0 0 mode W W W W W D2 D1 D0 0 0 0 W W W LCDSUB[4:0] D4-0 : LCDSUB[4:0] Output current setup of BLS1 - BLS2 terminal. [00000] : 0 mA (default) [00001] : 1 mA [00010] : 2 mA : : [11110] : 30 mA [11111] : 31 mA * D7, D6, and D5 must not be written. The waveform of sub LCD backlights current of operation * As for sub LCD backlights part, output current changes stepwise for noise reduction. * By the time it reaches current setup value, there will be delay of setup value internal 32clk. * When internal CLK stops during state transition, the state at that time is held. * The following waveform is internal signal. 32clk 8step 32clk Internal luminosity set point signal (typ26.6 s) 01000 00111 00110 00101 00100 00011 00010 00001 00000 0000001000 t 01000 00011 Page 54 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 4. Register and Address (continued) Register map detailed explanation (continued) DATA Sub Address 07h D7 D6 D5 D4 D3 Data Name — — HIEN Default 0 0 0 0 0 mode W W W W W D2 D1 D0 0 0 0 W W W PLCNT[4:0] D5 : HIEN Current large mode ON/OFF control of PL1 - PL2 terminal. [0] : OFF (default) [1] : ON (+30 mA) D4-0 : PLCNT[4:0] Output current setup of PL1 - PL2 terminal. [00000] : 0 mA (default) [00001] : 1 mA [00010] : 2 mA : : [11110] : 30 mA [11111] : 31 mA The waveform of Photo flashes current of operation * As for Photo flashes part, output current changes stepwise for noise reduction. * By the time it reaches current setup value, there will be delay of setup value internal 32clk. * When internal CLK stops during state transition, the state at that time is held. * The following waveform is internal signal. 32clk 8step 32clk Internal luminosity set point signal (typ26.6 s) 01000 00111 00110 00101 00100 00011 00010 00001 00000 0000001000 t 0100000011 Page 55 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 4. Register and Address (continued) Register map detailed explanation (continued) Sub Address 08h DATA D7 D6 D5 D4 D3 D2 D1 D0 Data Name — BL1M BL2M BL3M BL4M BLS1M BLS2M PWMCLK Default 0 0 0 0 0 0 0 0 mode W W W W W W W W D6 : BL1M The automatic ON control monitor selection bit of DC/DC converter. (BL1 terminal) [0] : Monitor of BL1 terminal is possible.(default) [1] : Monitor of BL1 terminal is impossible. D5 : BL2M The automatic ON control monitor selection bit of DC/DC converter. (BL2 terminal) [0] : Monitor of BL2 terminal is possible.(default) [1] : Monitor of BL2 terminal is impossible. D4 : BL3M The automatic ON control monitor selection bit of DC/DC converter. (BL3 terminal) [0] : Monitor of BL3 terminal is possible.(default) [1] : Monitor of BL3 terminal is impossible. D3 : BL4M The automatic ON control monitor selection bit of DC/DC converter. (BL4 terminal) [0] : Monitor of BL4 terminal is possible.(default) [1] : Monitor of BL4 terminal is impossible. D2 : BLS1M The automatic ON control monitor selection bit of DC/DC converter. (BLS1 terminal) [0] : Monitor of BLS1 terminal is possible.(default) [1] : Monitor of BLS1 terminal is impossible. D1 : BLS2M The automatic ON control monitor selection bit of DC/DC converter. (BLS2 terminal) [0] : Monitor of BLS2 terminal is possible.(default) [1] : Monitor of BLS2 terminal is impossible. D0 : PWMCLK The PWM operation clock selection bit. [0] : It operates by an internal clock. (default) [1] : It operates by an EXTCLK clock. * Interruption of address 14h is generated only in the OSCEN = High state at PWMCLK = Low. * Interruption of address 14h is generated only in the state where a clock is input into EXTCLK terminal, at PWMCLK = High Page 56 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 4. Register and Address (continued) Register map detailed explanation (continued) Sub Address 09h DATA D7 D6 D5 D4 D3 D2 D1 D0 Data Name VIBACT VIBPL1 VIBPL2 VIBSUB1 VIBSUB2 VIBMTX VIBRGB1 VIBRGB2 Default 0 0 0 0 0 0 0 0 mode W W W W W W W W D7 : VIBACT A putting-out-lights setup of LED by VIBCTL terminal. [0] : The light is switched on at VIBCTL = Low.(default) [1] : The light is switched on at VIBCTL = High. D6 : VIBPL1 A putting-out-lights ON/OFF setup of PL1 terminal by VIBCTL terminal. [0] : Putting-out-lights control OFF by VIBCTL terminal. (default) [1] : Putting-out-lights control ON by VIBCTL terminal. D5 : VIBPL2 A putting-out-lights ON/OFF setup of PL2 terminal by VIBCTL terminal. [0] : Putting-out-lights control OFF by VIBCTL terminal. (default) [1] : Putting-out-lights control ON by VIBCTL terminal. D4 : VIBSUB1 A putting-out-lights ON/OFF setup of BLS1 terminal by VIBCTL terminal. [0] : Putting-out-lights control OFF by VIBCTL terminal. (default) [1] : Putting-out-lights control ON by VIBCTL terminal. D3 : VIBSUB2 A putting-out-lights ON/OFF setup of BLS2 terminal by VIBCTL terminal. [0] : Putting-out-lights control OFF by VIBCTL terminal. (default) [1] : Putting-out-lights control ON by VIBCTL terminal. D2 : VIBMTX A putting-out-lights ON/OFF setup of 7*7 dots matrix LED by VIBCTL terminal. [0] : Putting-out-lights control OFF by VIBCTL terminal. (default) [1] : Putting-out-lights control ON by VIBCTL terminal. D1 : VIBRGB1 A putting-out-lights ON/OFF setup of R1, G1 and B1 terminal by VIBCTL terminal. [0] : Putting-out-lights control OFF by VIBCTL terminal. (default) [1] : Putting-out-lights control ON by VIBCTL terminal. D0 : VIBRGB2 A putting-out-lights ON/OFF setup of R2, G2 and B2 terminal by VIBCTL terminal. [0] : Putting-out-lights control OFF by VIBCTL terminal. (default) [1] : Putting-out-lights control ON by VIBCTL terminal. Page 57 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 4. Register and Address (continued) Register map detailed explanation (continued) Sub Address 0Ah DATA D7 D6 D5 D4 D3 D2 D1 D0 Data Name LEDACT DISPL1 DISPL2 DISSUB1 DISSUB2 DISMTX DISRGB1 DISRGB2 Default 0 0 0 0 0 0 0 0 mode W W W W W W W W D7 : LEDACT A putting-out-lights setup of LED by LEDCTL terminal. [0] : The light is switched on at LEDCTL = Low(default) [1] : The light is switched on at LEDCTL = High D6 : DISPL1 A putting-out-lights ON/OFF setup of PL1 terminal by LEDCTL terminal. [0] : Putting-out-lights control OFF by LEDCTL terminal. (default) [1] : Putting-out-lights control ON by LEDCTL terminal. D5 : DISPL2 A putting-out-lights ON/OFF setup of PL2 terminal by LEDCTL terminal. [0] : Putting-out-lights control OFF by LEDCTL terminal. (default) [1] : Putting-out-lights control ON by LEDCTL terminal. D4 : DISSUB1 A putting-out-lights ON/OFF setup of BLS1 terminal by LEDCTL terminal. [0] : Putting-out-lights control OFF by LEDCTL terminal. (default) [1] : Putting-out-lights control ON by LEDCTL terminal. D3 : DISSUB2 A putting-out-lights ON/OFF setup of BLS2 terminal by LEDCTL terminal. [0] : Putting-out-lights control OFF by LEDCTL terminal. (default) [1] : Putting-out-lights control ON by LEDCTL terminal. D2 : DISMTX A putting-out-lights ON/OFF setup of 7*7 dots matrix LED by LEDCTL terminal. [0] : Putting-out-lights control OFF by LEDCTL terminal. (default) [1] : Putting-out-lights control ON by LEDCTL terminal. D1 : DISRGB1 A putting-out-lights ON/OFF setup of R1, G1 and B1 terminal by LEDCTL terminal. [0] : Putting-out-lights control OFF by LEDCTL terminal. (default) [1] : Putting-out-lights control ON by LEDCTL terminal. D0 : DISRGB2 A putting-out-lights ON/OFF setup of R2, G2 and B2 terminal by LEDCTL terminal. [0] : Putting-out-lights control OFF by LEDCTL terminal. (default) [1] : Putting-out-lights control ON by LEDCTL terminal. Page 58 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 4. Register and Address (continued) Register map detailed explanation (continued) Ex.)In the case of PL1 terminal VIBCTL VIBACT VIBPL1 PL1 control signal Current value 0 0 0 ON OFF is PLCNT[4:0] = [00000] by PLCNT[4:0] 0 1 0 ON OFF is PLCNT[4:0] = [00000] by PLCNT[4:0] 1 0 0 ON OFF is PLCNT[4:0] = [00000] by PLCNT[4:0] 1 1 0 ON OFF is PLCNT[4:0] = [00000] by PLCNT[4:0] 0 0 1 ON OFF is PLCNT[4:0] = [00000] by PLCNT[4:0] 0 1 1 OFF 0mA 1 0 1 OFF 0mA 1 1 1 ON OFF is PLCNT[4:0] = [00000] by PLCNT[4:0] LEDCTL LEDAC T DISPL1 PL1 control signal Current value 0 0 0 ON OFF is PLCNT[4:0] = [00000] by PLCNT[4:0] 0 1 0 ON OFF is PLCNT[4:0] = [00000] by PLCNT[4:0] 1 0 0 ON OFF is PLCNT[4:0] = [00000] by PLCNT[4:0] 1 1 0 ON OFF is PLCNT[4:0] = [00000] by PLCNT[4:0] 0 0 1 ON OFF is PLCNT[4:0] = [00000] by PLCNT[4:0] 0 1 1 OFF 0mA 1 0 1 OFF 0mA 1 1 1 ON OFF is PLCNT[4:0] = [00000] by PLCNT[4:0] * When control signal is input from both VIBCTL terminal and LEDCTL terminal, the OFF state of each PL1 terminal control signal is processed in OR logic. * Same control for VIBPL2 and PL2 terminal * Same control for VIBSUB1 and BLS1 terminal * Same control for VIBSUB2 and BLS2 terminal * Same control for VIBMTX and X0 - X6 terminal * Same control for VIBRGB1 and R1, G1 and B1 terminal * Same control for VIBRGB2 and R2, G2 and B2 terminal * Same control for DISPL2 and PL2 terminal * Same control for DISSUB1 and BLS1 terminal * Same control for DISSUB2 and BLS2 terminal * Same control for DISMTX and X0 - X6 terminal * Same control for DISRGB1 and R1, G1 and B1 terminal * Same control for DISRGB2 and R2, G2 and B2 terminal Page 59 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 4. Register and Address (continued) Register map detailed explanation (continued) Sub Address 10h DATA D7 D6 D5 D4 D3 D2 D1 D0 Data Name — — — — — — — GPIOCLK Default 0 0 0 0 0 0 0 0 mode W/R W/R W/R W/R W/R W/R W/R W/R D0 : GPIOCLK Change of the clock for GPIO control. [0] : It operates by an internal clock. (default) [1] : It operates by an EXTCLK clock. * At GPIOCLK = Low, register (IOFACTOR, IOSTATE, ICHAT, IOCHAT), interruption of address 2Eh, and INT terminal operate in the state of OSCEN = High. * At GPIOCLK = High, register (IOFACTOR, IOSTATE, ICHAT, IOCHAT), interruption of address 2Eh, and INT terminal operate, where clock is input into EXTCLK terminal. Page 60 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 4. Register and Address (continued) Register map detailed explanation (continued) DATA Sub Address 11h D7 D6 D5 D4 D3 D2 D1 D0 Data Name — — — — — — IOSEL1 IOSEL2 Default 0 0 0 0 0 0 0 0 mode W/R W/R W/R W/R W/R W/R W/R W/R D1 : IOSEL1 An input/output setup of GPIO1 terminal [0] : Input (default) [1] : Output D0 : IOSEL2 An input/output setup of GPIO2 terminal [0] : Input (default) [1] : Output Page 61 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 4. Register and Address (continued) Register map detailed explanation (continued) Sub Address 12h DATA D7 D6 D5 D4 D3 D2 D1 D0 Data Name — — — IMSK1 IMSK2 IMSK3 IOMSK1 IOMSK2 Default 0 0 0 0 0 0 0 0 mode W/R W/R W/R W/R W/R W/R W/R W/R D4 : IMSK1 GPI1 terminal change-of-state detection mask setup. [0] : Interruption output mask (default) [1] : Interruption output enable * The mask of the interruption detection output ISTA1 by change-of-state detection of GPI1 terminal is carried out. D3 : IMSK2 GPI2 terminal change-of-state detection mask setup. [0] : Interruption output mask (default) [1] : Interruption output enable * The mask of the interruption detection output ISTA2 by change-of-state detection of GPI2 terminal is carried out. D2 : IMSK3 GPI3 terminal change-of-state detection mask setup. [0] : Interruption output mask (default) [1] : Interruption output enable * The mask of the interruption detection output ISTA3 by change-of-state detection of GPI3 terminal is carried out. D1 : IOMSK1 GPIO1 terminal change-of-state detection mask setup. [0] : Interruption output mask (default) [1] : Interruption output enable * The mask of the interruption detection output IOSTA1 by change-of-state detection of GPIO1 terminal is carried out. D0 : IOMSK2 GPIO2 terminal change-of-state detection mask setup. [0] : Interruption output mask (default) [1] : Interruption output enable * The mask of the interruption detection output IOSTA2 by change-of-state detection of GPIO2 terminal is carried out. Page 62 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 4. Register and Address (continued) Register map detailed explanation (continued) DATA Sub Address 13h D7 D6 D5 D4 D3 D2 D1 D0 Data Name — — — — OOUT1 OOUT2 IOOUT1 IOOUT2 Default 0 0 0 0 0 0 0 0 mode W/R W/R W/R W/R W/R W/R W/R W/R D3 : OOUT1 An output logic setup of GPO1 terminal [0] : Output is Low (default) [1] : Output is High D2 : OOUT2 An output logic setup of GPO2 terminal [0] : Output is Low (default) [1] : Output is High D1 : IOOUT1 An output logic setup of GPIO1 terminal [0] : Output is Low (default) [1] : Output is High * Effective only at IOSEL1 = High (output mode). D0 : IOOUT2 An output logic setup of GPIO2 terminal [0] : Output is Low (default) [1] : Output is High * Effective only at IOSEL2 = High (output mode). Page 63 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 4. Register and Address (continued) Register map detailed explanation (continued) DATA Sub Address 14h D7 D6 D5 D4 D3 D2 D1 D0 Data Name FACGD1 ERR2EH — — RAMACT FRMINT CPUWRER TSD Default 0 0 0 0 0 0 0 0 mode R R R R R R R R D7 : FACGD1 [0] : Normal operation (default) [1] : No Read clearance D6 : ERR2EH Unusual detection of address 2Eh 0 : It is NOT unusual detection to address 2Eh. (default) 1 : It is unusual detection to address 2Eh. Read to address 2Eh. D3 : RAMACT Internal RAM access judgment 0 : RAM is NOT accessed. (default) 1 : RAM is accessed. D2 : FRMINT An one-frame display end judging scroll on display. 0 : Under a frame display (default) 1 : Frame display end D1 : CPUWRER CPU access error judgment 0 : CPU access error does NOT occur. (default) 1 : CPU access error occurs. D0 : TSD Unusual detection of TSD error. 0 : TSD unusual detection does NOT occur. (default) 1 : TSD unusual detection occurs. * The WRITE contents from CPU are not reflected in this IC at CPUWRER = High. Write from CPU again. * The interval of FACGD1 = High is maximum 1.93 s (at the internal clock operation) from the renewal time of data. * At FACGD1 = Low, if address 14h data is read, data of D0 - D6 are cleared. * RAM access from CPU cannot be performed at RAMACT = High . * When each address 14h register is set to High, the pulse in a cycle of 4 ms is output from INT. * The pulse output from INT continues an output until address 14h is read. * The pulse output from INT continues an output until address 2Eh is also read in ERR2EH = High . * The states for RAMACT = High are shown below. 1. While copying to RAM from ROM. 2. While clearing RAM Page 64 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 4. Register and Address (continued) Register map detailed explanation (continued) DATA Sub Address 15h D7 D6 D5 D4 D3 D2 D1 D0 Data Name STAGD — — ISTA1 ISTA2 ISTA3 IOSTA1 IOSTA2 Default 0 0 0 0 0 0 0 0 mode R R R R R R R R D7 : STAGD [0] : Normal operation (default) [1] : Data interruption disregard D4 : ISTA1 The state after chattering removal of GPI1 terminal. [0] : The terminal state after chattering is 0. (default) [1] : The terminal state after chattering is 1. D3 : ISTA2 The state after chattering removal of GPI2 terminal. [0] : The terminal state after chattering is 0. (default) [1] : The terminal state after chattering is 1. D2 : ISTA3 The state after chattering removal of GPI3 terminal. [0] : The terminal state after chattering is 0. (default) [1] : The terminal state after chattering is 1. D1 : IOSTA1 The state after chattering removal of GPIO1 terminal. [0] : The terminal state after chattering is 0. (default) [1] : The terminal state after chattering is 1. D0 : IOSTA2 The state after chattering removal of GPIO2 terminal. [0] : The terminal state after chattering is 0. (default) [1] : The terminal state after chattering is 1. * The interval of STAGD = High is maximum 1.93 s (at internal clock operation) from the time at which data was updated. * At IOSEL1 = High or IOSEL2 = High, the data of IOOUT1 or IOOUT2 is stored. Page 65 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 4. Register and Address (continued) Register map detailed explanation (continued) DATA Sub Address 16h D7 D6 D5 D4 Data Name — — ICHAT1[1:0] Default 0 0 0 mode W/R W/R W/R D3 D2 D1 D0 ICHAT2[1:0] ICHAT3[1:0] 0 0 0 0 0 W/R W/R W/R W/R W/R D5-4 : ICHAT1[1:0] An interruption chattering processing time setup of GPI1 terminal. [00] : 4800CLK 0 No chattering processing time (default) [01] : 4800CLK (4-1) Chattering processing time is 10.58 ms to 18.47 ms [10] : 4800CLK (9-1) Chattering processing time is 28.23 ms to 41.54 ms [11] : 4800CLK (16-1) Chattering processing time is 52.94 ms to 73.85 ms D3-2 : ICHAT2[1:0] An interruption chattering processing time setup of GPI2 terminal. [00] : 4800CLK 0 No chattering processing time (default) [01] : 4800CLK (4-1) Chattering processing time is 10.58 ms to 18.47 ms [10] : 4800CLK (9-1) Chattering processing time is 28.23 ms to 41.54 ms [11] : 4800CLK (16-1) Chattering processing time is 52.94 ms to 73.85 ms D1-0 : ICHAT3[1:0] An interruption chattering processing time setup of GPI3 terminal. [00] : 4800CLK 0 No chattering processing time (default) [01] : 4800CLK (4-1) Chattering processing time is 10.58 ms to 18.47 ms [10] : 4800CLK (9-1) Chattering processing time is 28.23 ms to 41.54 ms [11] : 4800CLK (16-1) Chattering processing time is 52.94 ms to 73.85 ms *The times shown above are for when the internal clock operates. Page 66 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 4. Register and Address (continued) Register map detailed explanation (continued) Sub Address 17h DATA D7 D6 D5 D4 D3 D2 D1 D0 Data Name — — — — IOCHAT1[1:0] IOCHAT2[1:0] Default 0 0 0 0 0 0 0 0 mode W/R W/R W/R W/R W/R W/R W/R W/R D3-2 : IOCHAT1[1:0] An interruption chattering processing time setup of GPIO1 terminal. [00] : 4800CLK 0 No chattering processing time (default) [01] : 4800CLK (4-1) Chattering processing time is 10.58 ms to 18.47 ms [10] : 4800CLK (9-1) Chattering processing time is 28.23 ms to 41.54 ms [11] : 4800CLK (16-1) Chattering processing time is 52.94 ms to 73.85 ms D1-0 : IOCHAT2[1:0] An interruption chattering processing time setup of GPIO2 terminal. [00] : 4800CLK 0 No chattering processing time (default) [01] : 4800CLK (4-1) Chattering processing time is 10.58 ms to 18.47 ms [10] : 4800CLK (9-1) Chattering processing time is 28.23 ms to 41.54 ms [11] : 4800CLK (16-1) Chattering processing time is 52.94 ms to 73.85 ms *The times shown above are for when the internal clock operates. Page 67 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 4. Register and Address (continued) Register map detailed explanation (continued) DATA Sub Address 18h D7 D6 D5 D4 D3 D2 Data Name — — — — Default 0 0 0 0 0 0 0 0 mode W/R W/R W/R W/R W/R W/R W/R W/R IDET[1:0] D1 D0 IODET[1:0] D3-2 : IDET[1:0] The interruption detection method setup of GPI1, GPI2 and GPI3 terminal. [00] : Change-of-state detection is impossible. (default) [01] : Change of the terminal state from Low to High is detected. [10] : Change of the terminal state from High to Low is detected. [11] : Both the edge of change of a terminal state is detected. (Low High and High Low ) D1-0 : IODET[1:0] The interruption detection method setup of GPIO1 and GPIO2 terminal. [00] : Change-of-state detection is impossible. (default) [01] : Change of the terminal state from Low to High is detected. [10] : Change of the terminal state from High to Low is detected. [11] : Both the edge of change of a terminal state is detected. (Low High and High Low ) Page 68 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 4. Register and Address (continued) Register map detailed explanation (continued) DATA Sub Address 19h D7 D6 D5 D4 D3 D2 D1 D0 Data Name — — — R2ON G2ON B2ON IOPLUD1 IOPLUD2 Default 0 0 0 0 0 0 0 0 mode W/R W/R W/R W/R W/R W/R W/R W/R D4 : R2ON ON/OFF control of R2 terminal [0] : OFF (default) [1] : ON D3 : G2ON ON/OFF control of G2 terminal [0] : OFF (default) [1] : ON D2 : B2ON ON/OFF control of B2 terminal [0] : OFF (default) [1] : ON D1 : IOPLUD1 A terminal processing setup of GPIO1 terminal [0] : PULL-UP processing (default) [1] : NOT PULL-UP processing D0 : IOPLUD2 A terminal processing setup of GPIO2 terminal [0] : PULL-UP processing (default) [1] : NOT PULL-UP processing * IOPLUD1 and IOPLUD2 are effective only when IOSEL1 and IOSEL2 are input modes. * In the case of the state of IOPLUD1 = Low and IOVSEL1 = High, the power of 2.85 V cannot be applied to GPIO1. * In the case of the state of IOPLUD2 = Low and IOVSEL2 = High, the power of 2.85 V cannot be applied to GPIO2. Page 69 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 4. Register and Address (continued) Register map detailed explanation (continued) DATA Sub Address 1Ah D7 D6 D5 D4 D3 D2 D1 D0 Data Name INTVSEL — — — OVSEL1 OVSEL2 IOVSEL1 IOVSEL2 Default 0 0 0 0 0 0 0 0 mode W/R W/R W/R W/R W/R W/R W/R W/R D7 : INTVSEL A terminal voltage setup of INT terminal [0] : 1.85 V (default) [1] : 2.85 V D3 : OVSEL1 A terminal voltage setup of GPO1 terminal [0] : 2.85 V (default) [1] : 1.85 V D2 : OVSEL2 A terminal voltage setup of GPO2 terminal [0] : 2.85 V (default) [1] : 1.85 V D1 : IOVSEL1 A terminal voltage setup of GPIO1 terminal [0] : 2.85 V (default) [1] : 1.85 V D0 : IOVSEL2 A terminal voltage setup of GPIO2 terminal [0] : 2.85 V (default) [1] : 1.85 V Page 70 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 4. Register and Address (continued) Register map detailed explanation (continued) DATA Sub Address 20h D7 D6 D5 D4 D3 D2 D1 D0 Data Name — — — — — — — MTXON Default 0 0 0 0 0 0 0 0 mode W/R W/R W/R W/R W/R W/R W/R W/R D0 : MTXON An ON/OFF setup of matrix LED [0] : OFF (default) [1] : ON * During MTXON = High, subsequent ROM, RAM, and the control contents to a register are sequentially processed and lit up. * When address 08h PWMCLK is Low, set MTXON to High 5 ms after setting address 01h OSCEN to High. * When address 08h PWMCLK is High, set MTXON to High 5 ms after inputting clocks to EXTCLK terminal. * Set MTXON to High, and then set up other addresses to display the matrix part. Page 71 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 4. Register and Address (continued) Register map detailed explanation (continued) Sub Address DATA D7 D6 D5 Data Name 21h D4 D3 D2 D1 D0 MTXDATA[7:0] Default 0 0 0 0 0 0 0 0 mode W/R W/R W/R W/R W/R W/R W/R W/R D7-0 : MTXDATA[7:0] An address setup of ROM/RAM of the data to read [00000000] - [10010101] : ROM ( Only luminosity ) 7*7 pattern No.0 (default) to No.149 [10010110] - [11010000] : ROM ( Luminosity Cycle Delay ) 7*7 pattern No. 150 to No.208 [11010001] - [11010010] : RAM ( Luminosity Cycle Delay ) 7*7 pattern RAM No.1, 2 * The pattern No.0 of ROM is all 0 data of matrix LED. * Accessing to 21h is disabled while copying from ROM to RAM (COPYSTART = High of 24h). Page 72 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 4. Register and Address (continued) Register map detailed explanation (continued) DATA Sub Address 22h D7 D6 D5 D4 D3 D2 D1 D0 Data Name — — — — — — ROM77[1:0] Default 0 0 0 0 0 0 0 0 mode W/R W/R W/R W/R W/R W/R W/R W/R D1-0 : ROM77[1:0] Lighting control of the 7x7 (LED No.A1-G7) fixed pattern of ROM [00] : ROM data is displayed. [01] : ROM data is displayed by firefly lighting in 1 s. [10] : ROM data is displayed by firefly lighting in 2 s. [11] : ROM data is displayed by firefly lighting in 3 s. * During display of repetition (REPON = High), ROM77 must not be changed. The peak value of luminosity is a value set up by ROM. Luminosity t1 = t2 = t4 = 249.2 ms t3 = 265.8 ms Firefly lighting cycle : T t2 t1 t4 t3 t A B C D E F G LED’s number 1 2 3 4 5 6 7 LED’s number Page 73 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 4. Register and Address (continued) Register map detailed explanation (continued) DATA Sub Address D7 D6 D5 D3 D2 D1 D0 SELROM[7:0] Data Name 23h D4 Default 0 0 0 0 0 0 0 0 mode W/R W/R W/R W/R W/R W/R W/R W/R D7-0 : SELROM[7:0] An address setup of ROM copied to RAM. [00000000] - [10010101] : ROM (Only luminosity) 7*7 pattern No.0 (default) to No.149 [10010110] - [11010000] : ROM (Luminosity Cycle Delay) 7*7 pattern No.150 to No.208 * Accessing to 23h is disabled while copying from ROM to RAM (COPYSTART = High of 24h). Page 74 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 4. Register and Address (continued) Register map detailed explanation (continued) Sub Address 24h DATA D7 D6 D5 D4 D3 D2 D1 D0 Data Name — — — — — — SELRAM COPYSTART Default 0 0 0 0 0 0 0 0 mode W/R W/R W/R W/R W/R W/R W/R W/R D1 : SELRAM A RAM number setup of a copy place. 0 : RAM No.1 1 : RAM No.2 D0 : COPYSTART Copy start ON/OFF control to RAM from ROM [0] : OFF [1] : The copy set up by SELROM and SELRAM is started. (It returns to 0 by internal 51 CLK.) * Address 24h is only for copying data to RAM and never start LED display. (However, if this RAM is copied when LED display is showing, LED display is updated.) * Writing in address 21h-MTXDATA, 2Ah-SCLON, and 27h-REPON is disabled while copying. (RAMACT flag is raised.) * Accessing to SELRAM is disabled while copying from ROM to RAM (COPYSTART = High of 24h) * Don’t write address 29h (RAM-clear ) while copying. (The waiting time for 1 ms or more is required after COPYSTART.) Page 75 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 4. Register and Address (continued) Register map detailed explanation (continued) Sub Address DATA D7 D6 D5 D3 D2 D1 D0 SETFROM[7:0] Data Name 25h D4 Default 0 0 0 0 0 0 0 0 mode W/R W/R W/R W/R W/R W/R W/R W/R D7-0 : SETFROM[7:0] An address setup of the ROM frame data at the repetition display start. [00000000] - [10010101] : ROM (Only luminosity) 7*7 pattern No.0 (default) to No.149 [10010110] - [11010000] : ROM (Luminosity Cycle Delay) 7*7 pattern No.150 to No.208 * During display of repetition (REPON = High), Don’t change the setting of SETFROM. Page 76 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 4. Register and Address (continued) Register map detailed explanation (continued) Sub Address DATA D7 D6 D5 Data Name 26h D4 D3 D2 D1 D0 SETTO[7:0] Default 0 0 0 0 0 0 0 0 mode W/R W/R W/R W/R W/R W/R W/R W/R D7-0 : SETTO[7:0] An address setup of the ROM frame data at the repetition display end. [00000000] - [10010101] : ROM (Only luminosity) 7*7 pattern No.0 (default) to No.149 [10010110] - [11010000] : ROM (Luminosity Cycle Delay) 7*7 pattern No.150 to No.208 * During display of repetition (REPON = High), don’t change the setting of SETTO. Page 77 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 4. Register and Address (continued) Register map detailed explanation (continued) Sub Address 27h DATA D7 D6 D5 D4 D3 D2 D1 D0 Data Name — — — — — — — REPON Default 0 0 0 0 0 0 0 0 mode W/R W/R W/R W/R W/R W/R W/R W/R D0 : REPON Repetition display ON/OFF control 0 : Repetition display OFF (default) 1 : Repetition display ON * During display of repetition, display of set-up ROM is continued. * A repetition display is started in the state of MTXON = High and REPON = High. * Accessing to 27h is disabled while copying from ROM to RAM (COPYSTART = High of 24h). * When the setting of SCLON is changed from Low to High while REPON = High, REPON becomes Low and it shifts to scroll function. * During display of repetition (REPON = High), don’t change the setting of SETFROM and SETTO. Page 78 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 4. Register and Address (continued) Register map detailed explanation (continued) DATA Sub Address 28h D7 D6 D5 D4 D3 D2 D1 D0 Data Name — — — — — — SETTIME[1:0] Default 0 0 0 0 0 0 0 0 mode W/R W/R W/R W/R W/R W/R W/R W/R D1-0 : SETTIME[1:0] A frame display time setup of repetition display [00] : 1 s (default) [01] : 2 s [10] : 3 s [11] : 4 s Page 79 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 4. Register and Address (continued) Register map detailed explanation (continued) Sub Address 29h DATA D7 D6 D5 D4 D3 D2 D1 D0 Data Name — — — — — — RAM1 RAM2 Default 0 0 0 0 0 0 0 0 mode W/R W/R W/R W/R W/R W/R W/R W/R D1 : RAM1 The data in 7*7 RAM1 is cleared. 0 : Overwrite is possible. (default) 1 : The data in 7*7 RAM1 is cleared. (It returns to 0 by internal 2 CLK.) D0 : RAM2 The data in 7*7 RAM2 is cleared. 0 : Overwrite is possible. (default) 1 : The data in 7*7 RAM2 is cleared. (It returns to 0 by internal 2 CLK.) * Don’t set the RAM-clear operation for RAM1 or RAM2 during display of repetition (SCLON = High). * Don’t set the RAM-clear operation (29h) during the COPY operation (24h). (The waiting time for 1 ms or more is required after COPYSTART.) Page 80 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 4. Register and Address (continued) Register map detailed explanation (continued) Sub Address 2Ah DATA D7 D6 D5 D4 D3 D2 D1 D0 Data Name — — — — — — — SCLON Default 0 0 0 0 0 0 0 0 mode W/R W/R W/R W/R W/R W/R W/R W/R D0 : SCLON ON/OFF setup of scroll display 0 : OFF (default) 1 : ON * A scroll display displays the data which exists in the RAM No.1-2 of 7*7 in order of A-G column. The display travel time of a column is the preset value of SCLTIME. * During display of scroll, data can be written to RAM without specifying RAM number. (Writing is performed to empty RAM.) * A scroll display is started in the state of MTXON = High and SCLON. * Accessing to 2Ah is disabled while copying from ROM to RAM (COPYSTART = High of 24h). * When the setting of REPON is changed from Low to High while SCLON = High, SCLON becomes Low and it shifts to repetition display function. * During display of scroll (SCLON = High), don’t change the setting of RAM1 and RAM2. Page 81 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 4. Register and Address (continued) Register map detailed explanation (continued) DATA Sub Address 2Bh D7 D6 D5 D4 D3 D2 D1 D0 Data Name — — — — — — SCLTIME[1:0] Default 0 0 0 0 0 0 0 0 mode W/R W/R W/R W/R W/R W/R W/R W/R D1-0 : SCLTIME[1:0] A frame display time setup of scroll display [00] : 0.1 s (default) [01] : 0.2 s [10] : 0.4 s [11] : 0.8 s * The display travel time of the column is the preset value of SCLTIME. Page 82 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 4. Register and Address (continued) Register map detailed explanation (continued) DATA Sub Address 2Ch D7 D6 D5 D4 D3 D2 D1 D0 Data Name — — — — — — — RGBON Default 0 0 0 0 0 0 0 0 mode W/R W/R W/R W/R W/R W/R W/R W/R D0 : RGBON ON/OFF setup of RGB lighting 0 : OFF (default) 1 : ON * When address 08h PWMCLK is Low, set RGBON to High 5 ms after setting address 01h OSCEN to High. * When address 08h PWMCLK is High, set RGBON to High 5 ms after inputting clocks to EXTCLK terminal. Page 83 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 4. Register and Address (continued) Register map detailed explanation (continued) Sub Address 2Dh DATA D7 D6 D5 D4 D3 Data Name — — Default 0 0 0 0 0 mode W/R W/R W/R W/R W/R D2 D1 D0 0 0 0 W/R W/R W/R RGBDATA D7-0 : RGBDATA[5:0] An address setup of ROM and register which read RGB data [000000] : Register is displayed. [000001] - [101010] : ROM (RGB pattern, Luminosity Cycle Delay) pattern No.1 to No.42 Page 84 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 4. Register and Address (continued) Register map detailed explanation (continued) DATA Sub Address 2Eh D7 D6 D5 D4 D3 D2 D1 D0 Data Name FACGD2 SCP OVP IFAC1 IFAC2 IFAC3 IOFAC1 IOFAC2 Default 0 0 0 0 0 0 0 0 mode R R R R R R R R D7 : FACGD [0] : Normal operation (default) [1] : No read clearance D6 : SCP An interruption factor register when short comparator operates while the DC/DC converter operated. [0] : An interrupt does NOT occur. (default) [1] : An interrupt occurs. D5 : OVP An interruption factor register when over-voltage detection comparator operates while the DC/DC converter operated. [0] : An interrupt does NOT occur. (default) [1] : An interrupt occurs. D4 : IFAC1 The interruption factor register of GPI1 terminal [0] : An interrupt does NOT occur. (default) [1] : An interrupt occurs. D3 : IFAC2 The interruption factor register of GPI2 terminal [0] : An interrupt does NOT occur. (default) [1] : An interrupt occurs. D2 : IFAC3 The interruption factor register of GPI3 terminal [0] : An interrupt does NOT occur. (default) [1] : An interrupt occurs. D1 : IOFAC1 The interruption factor register of GPIO1 terminal [0] : An interrupt does NOT occur. (default) [1] : An interrupt occurs. D0 : IOFAC2 The interruption factor register of GPIO2 terminal [0] : An interrupt does NOT occur. (default) [1] : An interrupt occurs. * The interval of FACGD2 = High is maximum 1.93 s (at internal clock operation) from the renewal time of data. * At FACGD2 = Low, if the data of address 2Eh is read, data of D0 - D6 are cleared. * Only at IOSEL1 = Low or IOSEL2 = Low, an interruption factor is generated. * In the case of IOSEL1 = High or IOSEL2 = High, status and register in chattering removal circuit is reset. * When each address 2Eh register is set to High, the pulse in a cycle of 4 ms is output from INT. * The pulse output from INT continues an output until address 14h is read. Page 85 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 4. Register and Address (continued) Register map detailed explanation (continued) DATA Sub Address 30h D7 D6 D5 D4 D3 D2 D1 D0 Data Name — — — — — — — RAMNUM Default 0 0 0 0 0 0 0 0 mode W/R W/R W/R W/R W/R W/R W/R W/R D1-0 : RAMNUM[1:0] A RAM number setup at the CPU access (READ and WRITE). 0 : RAM No.1 1 : RAM No.2 * Accessing to 30h is disabled during display of scroll (2Ah SCLON = High). Page 86 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 4. Register and Address (continued) Register map detailed explanation (continued) DATA Sub Address D7 D6 D4 D3 BLA1[1:0] Data Name 31h D5 D2 D1 FRA1[1:0] D0 DLA1[1:0] Default 0 0 0 0 0 0 0 0 mode W/R W/R W/R W/R W/R W/R W/R W/R A B C D E F G LED’s number 1 2 3 4 5 6 7 LED’s number D7-4 : BLA1[1:0] Luminosity setup of LED No.A1 [0000] : 0 mA (default) [0001] : 1 mA [0010] : 2 mA [0011] : 3 mA [0100] : 4 mA [0101] : 5 mA [0110] : 8 mA [0111] : 11 mA [1000] : 15 mA [1001] : 17 mA [1010] : 19 mA [1011] : 21 mA [1100] : 24 mA [1101] : 26 mA [1110] : 28 mA [1111] : 30 mA D3-2 : FRA1[1:0] Firefly operation and cycle setup of the LED No.A1 [00] : Lighting mode (default) [01] : Firefly lighting cycle 1 s [10] : Firefly lighting cycle 2 s [11] : Firefly lighting cycle 3 s D1-0 : DLA1[1:0] Firefly operation delay setup of the LED No.A1 [00] : No delay (default) [01] : Delay 25 % [10] : Delay 50 % [11] : Delay 75 % * The operation is the same as above for the addresses to 61h corresponding to each LED number. * The waiting time for 2 or more internal clocks (2 s or more) is required after the data from address 31h to 61h is written in. Please input other serial commands after that. Page 87 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 4. Register and Address (continued) Register map detailed explanation (continued) DATA Sub Address D7 D5 D4 BLLEDR1[1:0] Data Name 62h D6 D3 D2 FRLEDR1[1:0] D1 D0 DLLEDR1[1:0] Default 0 0 0 0 0 0 0 0 mode W/R W/R W/R W/R W/R W/R W/R W/R D7-4 : BLLEDR1[1:0] Luminosity setup of R1 terminal [0000] : 0 mA (default) [0001] : 1 mA [0010] : 2 mA : : [1110] : 14 mA [1111] : 15 mA D3-2 : FRLEDR1[1:0] Firefly operation and cycle setup of R1 terminal [00] : Lighting mode (default) [01] : Firefly lighting cycle 1 s [10] : Firefly lighting cycle 2 s [11] : Firefly lighting cycle 3 s D1-0 : DLLEDR1[1:0] Firefly operation delay setup of R1 terminal [00] : No delay (default) [01] : Delay 25 % [10] : Delay 50 % [11] : Delay 75 % * The operation is the same as above for the addresses to 67h corresponding to G1 and B1 terminal. * The waiting time for 2 or more internal clocks (2 s or more) is required after the data from address 62h to 64h is written in. Please input other serial commands after that. Page 88 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 4. Register and Address (continued) Register map detailed explanation (continued) DATA Sub Address 6Bh D7 D6 D5 D4 D3 D2 D1 D0 Data Name — — — — — — — PROT1 Default 0 0 0 0 0 0 0 0 mode W/R W/R W/R W/R W/R W/R W/R W/R DATA Sub Address 6Dh D7 D6 D5 D4 D3 D2 D1 D0 Data Name — — — PROT2 — — — — Default 0 0 0 0 0 0 0 0 mode W/R W/R W/R W/R W/R W/R W/R W/R DATA Sub Address 6Fh D7 D6 D5 D4 D3 D2 D1 D0 Data Name PROT3 — — — — — — — Default 0 0 0 0 0 0 0 0 mode W/R W/R W/R W/R W/R W/R W/R W/R D2 D1 D0 6BhD0(PROT1), 6DhD4(PROT2), 6FhD7(PROT3) * Please don’t access to address 6Bh to 6Fh. * Addresses to 77h are for test. * When all the three above bits are set to High, it is allowed to write in Addresses [ 70h - 77h ]. (For test. Do not setup these addresses.) Sub Address DATA D7 D6 D5 D4 Data Name 70h D3 TEST1[7:0] Default 0 0 0 0 0 0 0 0 mode W/R W/R W/R W/R W/R W/R W/R W/R D7-0 : TEST1[7:0] The register for test * Addresses to 77h are for test. * Please don’t access to address 70h to 77h. Page 89 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 5. Serial interface format SPI1 format The interface with microcomputer consists of 16 bit-serial register (8-bit of command, 8-bit of address), and address decoder and transmitting register (8-bit). Serial interface consists of four terminals of serial clock terminal (CLK), serial-data input terminal (DI), serialdata output terminal (DO), and chip enable input terminal (CE). (1) Reception operation Data is taken into internal shift register by the rising edge of CLK. (A maximum of 13 MHz of frequency of CLK can be used) In High interval of CE, reception of data becomes ENABLE. (active : High) Data is transmitted at MSB first in order of a control register address (8-bit) and control command (8-bit). Timing of reception CE CLK DI W A6 A5 A4 A3 A2 A1 DO A0 D7 D6 D5 D4 D3 D2 D1 D0 Hi-Z (2) Transmission operation Data is taken into internal shift register by the rising edge of CLK. (A maximum of 6 MHz of frequency of CLK can be used) * It is not possible to read RAM data. In High interval of CE, reception of data becomes ENABLE. (active : High) Data is transmitted at MSB first in order of a control register address (8-bit) and control command (max 8-bit). Timing of transmission CE CLK DI R A6 DO A5 A4 Hi-Z A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Hi-Z Page 90 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 6. Signal distribution diagram Power supply distribution diagram VB VBLED VBDCDC VLED1 VLED2 LDO1 LDO2 BGR TSD LDO1 LDO2 DCDC I/O LOGIC CHGSW BL BLS PL MTX RGB SCAN AGND DGND DCDCGND LEDGND1 LEDGND2 PGND1 PGND2 RGBGND1 RGBGND2 Page 91 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 6. Signal distribution diagram (continued) Control / Clock distribution diagram 1 (PAD) EXTCLK 1.2MHz Oscillator 0 Selector REGMAP (Register) PWMCLK 1 0 Selector * Step change of states of output current 05h LCDMAIN 06h LCDSUB 07h PLCNT Matrix RGB * Matrix, RGB operation PWM control Read / Write of memory data (ROM and RAM) 14h RAMACT, FRMINT, CPUWRER GPIO * GPIO operation 4 ms sampling control 4 ms pulse control of interruption 14h interruption generating 2Eh interruption generating SPI1 * Serial ⇔ Parallel conversion SCLK Serial ⇔ Parallel conversion (input) SCLK_N Parallel Serial conversion (output) REGCLK Serial Parallel conversion output is latched in a standup. SPI2 * Serial ⇔ Parallel conversion Only 05h BLSCLK Serial Parallel conversion (input) REGCLK2 Serial Parallel conversion output is latched in a standup. (Register) GPIOCLK SCLK (PAD) CLK SCLK_N REGCLK (PAD) CSB (PAD) DI (PAD) DO 1 (PAD) GPI1 BLSCE 0 Selector REGCLK2 (Register) SERSEL (PAD) GPI2 (PAD) GPI3 BLSCLK BLSDAT Page 92 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 7. Example of firefly lighting Example of firefly lighting 1 Example of initial setting for lighting BLA1[1:0] 1 0 FRA1[1:0] 0 0 0 DLA1[1:0] 0 0 0 Current value A1 19 mA BLA1 = [1000] Serial ON t BLA1[1:0] Firefly lighting setup 1 s 1 1 FRA1[1:0] 1 1 0 DLA1[1:0] 1 0 0 Firefly lighting cycle T = 1.0134 s FRA1 = [01] Current value 33 mA A1 Serial ON t BLA1 = [1111] BLA1[1:0] Change to cycle 1 s to 2 s 1 1 FRA1[1:0] 1 1 1 DLA1[1:0] 0 0 0 Firefly lighting cycle T2 = 2.0268 s FRA1 = [10] Current value 33 mA A1 Serial ON t BLA1 = [1111] BLA1[1:0] Change to delay 0 25 % 1 1 DLA1 = [01] Current value 33 mA FRA1[1:0] 1 1 Firefly lighting cycle T2 = 2.0268 s FRA1 = [10] t5 1 t6 DLA1[1:0] 0 t7 0 t8 1 t5 = t6 = t8 = 498.4 ms t7 = 531.6 ms A1 Serial ON BLA1 = [1111] t Page 93 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A OPERATION (continued) 7. Example of firefly lighting (continued) Example of firefly lighting 2 Luminosity Firefly lighting cycle T1 = 3.0402 s FRA1 = [11] t1 = t2 = t4 = 747.6 ms t3 = 797.4 ms t1 t2 t3 t4 BLA1 A1 t t1 = t2 = t4 = 747.6 ms Firefly lighting cycle T1 = 3.0402 s t3 = 797.4 ms FRE7 = [11] DLE7 = [11] Luminosity E7 t1 t2 t3 t4 BLE7 t DLC5 = [01] Luminosity t5 = t6 = t8 = 498.4 ms Firefly lighting cycle T2 = 2.0268s t7 = 531.6 ms t5 t6 t7 t8 FRC5 = [10] C5 BLC5 t DLF3 = [10] Luminosity t9 = t10 = t12 = 249.2 ms t11 = 265.8 ms Firefly lighting cycle T3 = 1.0134 s t10 FRF3 = [01] t11 t12 t9 F3 t BLF3 Page 94 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A PACKAGE INFORMATION ( Reference Data ) Page 95 of 96 Established : 2006-08-29 Revised : 2013-04-01 Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A IMPORTANT NOTICE 1. When using the LSI for new models, verify the safety including the long-term reliability for each product. 2. When the application system is designed by using this LSI, please confirm the notes in this book. Please read the notes to descriptions and the usage notes in the book. 3. This LSI is intended to be used for general electronic equipment. Consult our sales staff in advance for information on the following applications: Special applications in which exceptional quality and reliability are required, or if the failure or malfunction of this LSI may directly jeopardize life or harm the human body. Any applications other than the standard applications intended. (1) Space appliance (such as artificial satellite, and rocket) (2) Traffic control equipment (such as for automobile, airplane, train, and ship) (3) Medical equipment for life support (4) Submarine transponder (5) Control equipment for power plant (6) Disaster prevention and security device (7) Weapon (8) Others : Applications of which reliability equivalent to (1) to (7) is required Our company shall not be held responsible for any damage incurred as a result of or in connection with the LSI being used for any special application, unless our company agrees to the use of such special application. 4. This LSI is neither designed nor intended for use in automotive applications or environments unless the specific product is designated by our company as compliant with the ISO/TS 16949 requirements. Our company shall not be held responsible for any damage incurred by customers or any third party as a result of or in connection with the LSI being used in automotive application, unless our company agrees to such application in this book. 5. Please use this product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Our company shall not be held responsible for any damage incurred as a result of our LSI being used by our customers, not complying with the applicable laws and regulations. 6. Pay attention to the direction of LSI. When mounting it in the wrong direction onto the PCB (printed-circuit-board), it might emit smoke or ignite. 7. Pay attention in the PCB (printed-circuit-board) pattern layout in order to prevent damage due to short circuit between pins. In addition, refer to the Pin Description for the pin configuration. 8. Perform visual inspection on the PCB before applying power, otherwise damage might happen due to problems such as solder-bridge between the pins of the semiconductor device. Also, perform full technical verification on the assembly quality, because the same damage possibly can happen due to conductive substances, such as solder ball, that adhere to the LSI during transportation. 9. Take notice in the use of this product that it might be damaged or occasionally emit smoke when an abnormal state occurs such as output pin-VCC short (Power supply fault), output pin-GND short (Ground fault), or output-to-output-pin short (load short). Safety measures such as installation of fuses are recommended because the extent of the above-mentioned damage and smoke emission will depend on the current capability of the power supply. 10. The protection circuit is for maintaining safety against abnormal operation. Therefore, the protection circuit should not work during normal operation. Especially for the thermal protection circuit, if the area of safe operation or the absolute maximum rating is momentarily exceeded due to output pin to VCC short (Power supply fault), or output pin to GND short (Ground fault), the LSI might be damaged before the thermal protection circuit could operate. 11. Unless specified in the product specifications, make sure that negative voltage or excessive voltage are not applied to the pins because the device might be damaged, which could happen due to negative voltage or excessive voltage generated during the ON and OFF timing when the inductive load of a motor coil or actuator coils of optical pick-up is being driven. 12. Verify the risks which might be caused by the malfunctions of external components. 13. Due to the unshielded structure of this LSI, functions and characteristics of the product cannot be guaranteed under the exposure of light. During normal operation or even under testing condition, please ensure that the LSI is not exposed to light. 14. Please ensure that your design does not have metal shield parts touching the chip surface as the surface potential is GND voltage. 15. Pay attention to the breakdown voltage of this LSI when using. More than + 1500 V or less than – 1500 V electrostatic discharge to all the pins might damage this product. Page 96 of 96 Established : 2006-08-29 Revised : 2013-04-01 Request for your special attention and precautions in using the technical information and semiconductors described in this book (1) If any of the products or technical information described in this book is to be exported or provided to non-residents, the laws and regulations of the exporting country, especially, those with regard to security export control, must be observed. (2) The technical information described in this book is intended only to show the main characteristics and application circuit examples of the products. No license is granted in and to any intellectual property right or other right owned by Panasonic Corporation or any other company. Therefore, no responsibility is assumed by our company as to the infringement upon any such right owned by any other company which may arise as a result of the use of technical information described in this book. (3) The products described in this book are intended to be used for general applications (such as office equipment, communications equipment, measuring instruments and household appliances), or for specific applications as expressly stated in this book. Consult our sales staff in advance for information on the following applications: – Special applications (such as for airplanes, aerospace, automotive equipment, traffic signaling equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. It is to be understood that our company shall not be held responsible for any damage incurred as a result of or in connection with your using the products described in this book for any special application, unless our company agrees to your using the products in this book for any special application. (4) The products and product specifications described in this book are subject to change without notice for modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements. (5) When designing your equipment, comply with the range of absolute maximum rating and the guaranteed operating conditions (operating power supply voltage and operating environment etc.). Especially, please be careful not to exceed the range of absolute maximum rating on the transient state, such as power-on, power-off and mode-switching. Otherwise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products. (6) Comply with the instructions for use in order to prevent breakdown and characteristics change due to external factors (ESD, EOS, thermal stress and mechanical stress) at the time of handling, mounting or at customer's process. When using products for which damp-proof packing is required, satisfy the conditions, such as shelf life and the elapsed time since first opening the packages. (7) This book may be not reprinted or reproduced whether wholly or partially, without the prior written permission of our company. 20100202