54LS194A/DM74LS194A 4-Bit Bidirectional Universal Shift Register General Description This bidirectional shift register is designed to incorporate virtually all of the features a system designer may want in a shift register; they feature parallel inputs, parallel outputs, right-shift and left-shift serial inputs, operating-mode-control inputs, and a direct overriding clear line. The register has four distinct modes of operation, namely: Parallel (broadside) load Shift right (in the direction QA toward QD) Shift left (in the direction QD toward QA) Inhibit clock (do nothing) Synchronous parallel loading is accomplished by applying the four bits of data and taking both mode control inputs, S0 and S1, high. The data is loaded into the associated flipflops and appear at the outputs after the positive transition of the clock input. During loading, serial data flow is inhibited. Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is high and S1 is low. Serial data for this mode is entered at the shift-right data input. When S0 is low and S1 is high, data shifts left synchronously and new data is entered at the shift-left serial input. Clocking of the flip-flop is inhibited when both mode control inputs are low. Features Y Y Y Y Parallel inputs and outputs Four operating modes: Synchronous parallel load Right shift Left shift Do nothing Positive edge-triggered clocking Direct overriding clear Connection Diagram Dual-In-Line Package TL/F/6407 – 1 Order Number 54LS194ADMQB, 54LS194AFMQB, 54LS194ALMQB, DM74LS194AM or DM74LS194AN See NS Package Number E20A, J16A, M16A, N16E or W16A C1995 National Semiconductor Corporation TL/F/6407 RRD-B30M105/Printed in U. S. A. 54LS194A/DM74LS194A 4-Bit Bidirectional Universal Shift Register June 1989 Absolute Maximum Ratings (Note) Note: The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings. The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation. If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage 7V Input Voltage 7V Operating Free Air Temperature Range b 55§ C to a 125§ C 54LS DM74LS 0§ C to a 70§ C Storage Temperature Range b 65§ C to a 150§ C Recommended Operating Conditions Symbol 54LS194A Parameter Max Min Nom Max 4.5 5 5.5 4.75 5 5.25 Supply Voltage VIH High Level Input Voltage VIL Low Level Input Voltage IOH High Level Output Current IOL Low Level Output Current fCLK Clock Frequency (Note 1) 30 Clock Frequency (Note 2) Pulse Width (Note 3) tSU Setup Time (Note 3) Units Nom VCC tW DM74LS194A Min 2 2 V V 0.7 0.8 V b 0.4 b 0.4 mA 8 mA 4 0 0 25 22 0 20 Clock 17 20 Clear 12 20 Mode 25 30 Data 16 20 tH Hold Time (Note 3) 0 0 tREL Clear Release Time (Note 3) 18 25 TA Free Air Operating Temperature b 55 125 MHz ns ns ns ns 0 70 §C Note 1: CL e 15 pF, TA e 25§ C and VCC e 5V. Note 2: CL e 50 pF, RL e 2 kX, TA e 25§ C and VCC e 5V. Note 3: TA e 25§ C and VCC e 5V. Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL Parameter Conditions Min Input Clamp Voltage VCC e Min, II e b18 mA High Level Output Voltage VCC e Min, IOH e Max VIL e Max, VIH e Min 54LS 2.5 DM74 2.7 Low Level Output Voltage VCC e Min, IOL e Max VIL e Max, VIH e Min 54LS Typ (Note 4) Max Units b 1.5 V V 3.4 0.4 DM74 0.35 0.5 IOL e 4 mA, VCC e Min 0.4 Input Current @ Max Input Voltage VCC e Max, VI e 7V 0.1 IIH High Level Input Current IIL Low Level Input Current VCC e Max, VI e 2.7V VCC e Max, VI e 0.4V IOS Short Circuit Output Current VCC e Max (Note 5) Supply Current VCC e Max (Note 6) II ICC mA 20 mA b 0.4 mA 54LS b 20 b 100 DM74 b 20 b 100 15 V 23 mA mA Note 4: All typicals are at VCC e 5V, TA e 25§ C. Note 5: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 6: With all outputs open, inputs A through D grounded, and 4.5V applied to S0, S1, CLEAR, and the serial inputs, ICC is tested with momentary ground, then 4.5V applied to CLOCK. 2 Switching Characteristics at VCC e 5V and TA e 25§ C (See Section 1 for Test Waveforms and Output Load) 54LS DM74LS CL e 15 pF CL e 50 pF RL e 2 kX From (Input) Symbol Parameter To (Output) Min Max Min Units Max fMAX Maximum Clock Frequency tPLH Propagation Delay Time Low to High Level Output Clock to Any Q 21 26 ns tPHL Propagation Delay Time High to Low Level Output Clock to Any Q 24 35 ns tPHL Propagation Delay Time High to Low Output Clear to Any Q 26 38 ns 30 20 MHz Note 1: All typicals are at VCC e 5V, TA e 25§ C. Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 3: With all outputs open, inputs A through D grounded, and 4.5V applied to S0, S1, CLEAR, and the serial inputs, ICC is tested with momentary ground, then 4.5V applied to CLOCK. Logic Diagram LS194A TL/F/6407 – 2 Function Table Inputs Clear L H H H H H H H Mode S1 S0 X X H L L H H L X X H H H L L L Clock X L u u u u u X Outputs Serial Parallel Left Right A B C D X X X X X H L X X X X H L X X X X X a X X X X X X X b X X X X X X X c X X X X X X X d X X X X X QA QB QC QD L QA0 a H L QBn QBn QA0 L QB0 b QAn QAn QCn QCn QB0 L QC0 c QBn QBn QDn QDn QC0 L QD0 d QCn QCn H L QD0 H e High Level (steady state), L e Low Level (steady state), X e Don’t Care (any input, including transitions) u e Transition from low to high level a, b, c, d e The level of steady state input at inputs A, B, C or D, respectively. QA0, QB0, QC0, QD0 e The level of QA, QB, QC, or QD, respectively, before the indicated steady state input conditions were established. QAn, QBn, QCn, QDn e The level of QA, QB, QC, respectively, before the most-recent 3 u transition of the clock. Timing Diagram Typical Clear, Load, Right-Shift, Left-Shift, Inhibit, and Clear Sequences TL/F/6407 – 3 4 5 Physical Dimensions inches (millimeters) Ceramic Leadless Chip Carrier Package (E) Order Number 54LS194ALMQB NS Package Number E20A 16-Lead Ceramic Dual-In-Line Package (J) Order Number 54LS194ADMQB NS Package Number J16A 6 Physical Dimensions inches (millimeters) (Continued) 16-Lead Small Outline Molded Package (M) Order Number DM74LS194AM NS Package Number M16A 16-Lead Molded Dual-In-Line Package (N) Order Number DM74LS194AN NS Package Number N16E 7 54LS194A/DM74LS194A 4-Bit Bidirectional Universal Shift Register Physical Dimensions inches (millimeters) (Continued) 16-Lead Ceramic Flat Package (W) Order Number 54LS194AFMQB NS Package Number W16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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