93L00 4-Bit Universal Shift Register General Description Features The 93L00 is a 4-bit universal shift register. As a high speed multifunctional sequential logic block, it is useful in a wide variety of register and counter applications. It may be used in serial-serial, shift left, shift right, serial-parallel, parallelserial, and parallel-parallel data register transfers. Y Connection Diagram Logic Symbol Y Asynchronous master reset J, K inputs to first stage Dual-In-Line Package TL/F/9576 – 2 VCC e Pin 16 GND e Pin 8 TL/F/9576 – 1 Order Number 93L00DMQB or 93L00FMQB See NS Package Number J16A or W16A Pin Names PE P0–P3 J K CP MR Q0–Q3 Q3 C1995 National Semiconductor Corporation TL/F/9576 Description Parallel Enable Input (Active LOW) Parallel Inputs First Stage J Input (Active HIGH) First Stage K Input (Active LOW) Clock Pulse Input (Active Rising Edge) Master Reset Input Parallel Outputs Complementary Last Stage Output RRD-B30M105/Printed in U. S. A. 93L00 4-Bit Universal Shift Register June 1989 Absolute Maximum Ratings (Note) Note: The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings. The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation. If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage 7V Input Voltage 5.5V Operating Free Air Temperature Range b 65§ C to a 125§ C MIL Recommended Operating Conditions Symbol 93L00 (MIL) Parameter VCC Supply Voltage VIH High Level Input Voltage VIL Low Level Input Voltage IOH High Level Output Voltage IOL Low Level Output Current Units Min Nom Max 4.5 5 5.5 2 b 55 V V 0.7 V b 0.4 mA 4.8 mA 125 §C TA Free Air Operating Temperature ts (H) ts (L) Setup Time HIGH or LOW, J, K and P0–P3 to CP 60 60 ns th (H) th (L) Hold Time HIGH or LOW, J, K and P0–P3 to CP 0 0 ns ts (H) ts (L) Setup Time HIGH or LOW, PE to CP 68 68 ns th (H) th (L) Hold Time HIGH or LOW, PE to CP 0 0 ns tw (H) tw (L) CP Pulse Width HIGH or LOW 38 38 ns tw (L) MR Pulse Width LOW 53 ns trec Recovery Time, MR to CP 70 ns 2 Electrical Characteristics Over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions VI Input Clamp Voltage VCC e Min, II e b10 mA VOH High Level Output Voltage VCC e Min, IOH e Max, VIL e Max, VIH e Min VOL Low Level Output Voltage VCC e Min, IOL e Max, VIH e Min, VIL e Max II Input Current @ Max Input Voltage VCC e Max, VI e 5.5V IIH High Level Input Current VCC e Max, VI e 2.4V Min 2.4 Typ (Note 1) Low Level Input Current VCC e Max, VI e 0.3V IOS Short Circuit Output Current VCC e Max (Note 2) ICC Supply Current VCC e Max Units b 1.5 V 3.4 V 0.3 V 1 mA Inputs 20 CP 40 PE IIL Max mA 46 Inputs b 400 CP b 800 PE b 920 b 2.5 mA b 25 mA 23 mA Note 1: All typicals are at VCC e 5V, TA e 25§ C. Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second. Switching Characteristics VCC e a 5.0V, TA e a 25§ C (See Section 1 for waveforms and load configurations) 93L Symbol CL e 15 pF Parameter Min Units Max fmax Maximum Shift Frequency tPLH tPHL Propagation Delay CP to Qn 10 35 51 ns tPHL Propagation Delay, MR to Qn 60 ns 3 MHz Functional Description When the PE input is LOW, the 93L00 appears as four common clocked D flip-flops. The data on the parallel inputs P0 – P3 is transferred to the respective Q0 – Q3 outputs following the LOW-to-HIGH clock transition. Shift left operation (Q3 x Q2) can be achieved by tying the Qn outputs to the Pnb1 inputs and holding the PE input LOW. All serial and parallel data transfers are synchronous, occuring after each LOW-to-HIGH clock transition. Since the 93L00 utilizes edge triggering, there is no restriction on the activity of the J, K, Pn and PE inputs for logic operationÐexcept for the setup and release time requirements. A LOW on the asynchronous Master Reset (MR) input sets all Q outputs LOW, independent of any other input condition. The Logic Diagrams and Truth Table indicate the functional characteristics of the 93L00 4-bit shift register. The device is useful in a wide variety of shifting, counting and storage applications. It performs serial, parallel, serial-to-parallel, or parallel-to-serial data transfers. The 93L00 has two primary modes of operation, shift right (Q0 x Q1) and parallel load, which are controlled by the state of the Parallel Enable (PE) input. When the PE input is HIGH, serial data enters the first flip-flop Q0 via the J and K inputs and is shifted one bit in the direction Q0 x Q1 x Q2 x Q3 following each LOW-to-HIGH clock transition. The JK inputs provide the flexibility of the JK type input for special applications, and the simple D-type input for general applications by tying the two pins together. Truth Table Operating Mode Inputs (MR e H) Outputs @ tn a 1 PE J K P0 P1 P2 P3 Q0 Q1 Q2 Q3 Q3 Shift Mode H H H H L L H H L H L H X X X X X X X X X X X X X X X X L Q0 Q0 H Q0 Q0 Q0 Q0 Q1 Q1 Q1 Q1 Q2 Q2 Q2 Q2 Q2 Q2 Q2 Q2 Parallel Entry Mode L L X X X X L H L H L H L H L H L H L H L H H L *tn a 1 e Indicates state after next LOW-to-HIGH clock transition. H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial 4 TL/F/9576 – 3 Logic Diagram 5 6 Physical Dimensions inches (millimeters) 16-Lead Ceramic Dual-In-Line Package (J) Order Number 93L00DMQB NS Package Number J16A 7 93L00 4-Bit Universal Shift Register Physical Dimensions inches (millimeters) (Continued) 16-Lead Ceramic Flat Package (W) Order Number 93L00FMQB NS Package Number W16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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