Digital Multi-Phase Buck Controller FEATURES CHL8203/12/13/14 DESCRIPTION Dual output 2/3/4+1-phase PWM Controller (CHL8212/13/14) and single output 3-phase PWM Controller (CHL8203) Easiest layout and fewest pins in the industry Footprint compatible with CHL8225 (CHL8213/14) for analog and power signals Up to 3 VID select lines for dynamic voltage transitions Slow OCP for Thermal Design Current (TDC) protection Programmable ICRITICAL signal I2C interface for configuration & telemetry Pin programmable I2C address (CHL8203/13/14) Overclocking support with I2C voltage override and Vmax setting Flexible I2C bus security features I2C security enable pin (CHL8203/13/14) Independent loop switching frequencies from 200kHz to 1.2MHz per phase IR Efficiency Shaping with Dynamic Phase Control (DPC) 1-phase & Active Diode Emulation modes for light load efficiency The CHL8212/13/14 are dual-loop digital multi-phase buck controllers and the CHL8203 is a single-loop digital multiphase buck controller designed for GPU voltage regulation. Dynamic voltage control is provided by registers which are programmed through I2C and then selected using a 3-bit parallel bus for fast access. The CHL8203/12/13/14 include IR Efficiency Shaping Technology to deliver exceptional efficiency at minimum cost across the entire load range. IR Dynamic Phase Control adds/drops active phases based upon load current and can be configured to enter 1-phase operation and diode emulation mode automatically or by command. IR’s unique Adaptive Transient Algorithm (ATA), based on proprietary non-linear digital PWM algorithms, minimizes output bulk capacitors and Multiple Time Programmable (MTP) storage saves pins and enables a small package size. Device configuration and fault parameters are easily defined using the IR Digital Power Design Center (DPDC) GUI and stored in on-chip MTP. The CHL8203/12/13/14 provides extensive OVP, UVP, OCP and OTP fault protection and the CHL8203/13/14 includes thermistor based temperature sensing with VRHOT signal. IRTN3 ISEN3 IRTN41/NC2 ISEN41/NC2 IRTN_L2 ISEN_L2 35 34 33 32 31 RCSP 1 30 RCSP_L2 RCSM 2 29 RCSM_L2 VPGM 3 28 VCC VSEN 4 27 VSEN_L2 26 VRTN_L2 CHL8213/14 40 Pin 6x6 QFN Top View VRTN 5 RRES 6 25 PWM_L2 TSEN 7 24 PWM41/ NC2 V18A 8 23 PWM3 VRRDY1 9 22 PWM2 VRRDY2 10 21 PWM1 1 CHL8214 CHL8213 11 12 13 14 15 16 17 18 19 20 SMB_DAT SMB_CLK TSEN2 41 GND ADDR/PROTECT 2 ENABLE GDDR Memory 36 VRHOT# Multi-phase GPU Systems 37 VIDSEL0 APPLICATIONS 38 VIDSEL1 Pb-Free, RoHS, QFN packages 39 VINSEN 3.3V +10%/-15% supply voltage; 0ºC to 85ºC operation 40 VIDSEL2 Compatible with IR ATL and 3.3V tri-state Drivers ISEN2 Multiple time programmable (MTP) memory for custom configuration IRTN2 PIN DIAGRAM ISEN1 Thermal Protection (OTP) and VRHOT# flag (CHL8203/13/14) IR Adaptive Transient Algorithm (ATA) on both loops minimizes output bulk capacitors and system cost IRTN1 Per-Loop Fault Protection: OVP, UVP, OCP The CHL8203/12/13/14 includes numerous features like register diagnostics for fast design cycles and platform differentiation, truly simplifying VRD design and enabling fastest time-to-market (TTM) with “set-and-forget” methodology. Figure 1: CHL8213/14 Package Top View 1 October 13, 2011 | FINAL | V1.3 Digital Multi-Phase Buck Controller CHL8203/12/13/14 ORDERING INFORMATION CHL82 ― Package Tape & Reel Qty Part Number QFN 3000 CHL8203-00CRT QFN 3000 CHL8203-xxCRT QFN 3000 CHL8212-00CRT C – Commercial Operating Temperature QFN 3000 CHL8212-xxCRT QFN 3000 CHL8213-00CRT xx – Configuration File QFN 3000 CHL8213-xxCRT QFN 3000 CHL8214-00CRT QFN 3000 CHL8214-xxCRT T – Tape and Reel R – Package Type: QFN Part Number: 03: CHL8203 12: CHL8212 13: CHL8213 14: CHL8214 1 2 1 2 1 2 1 2 Notes: 1. For unprogrammed/default parts, use configuration file 00. Unprogrammed parts will not start up until programmed in order to insure a safe power up. RCSM RCSP IRTN1 ISEN1 IRTN2 ISEN2 IRTN3 RCSP IRTN1 ISEN1 IRTN2 ISEN2 IRTN_L2 ISEN_L2 2. -xx indicates a customer specific configuration file. 28 27 26 25 24 23 22 28 27 26 25 24 23 22 VPGM 1 21 ISEN3 RCSM 1 21 RCSP_L2 VSEN 2 20 VCC VPGM 2 20 RCSM_L2 VRTN 3 19 PWM3 VSEN 3 19 VCC RRES 4 18 VSEN_L2 TSEN 5 17 PWM_L2 V18A 6 16 PWM2 15 PWM1 13 14 VIDSEL1 VIDSEL0 VRHOT# ENABLE ADDR/PROTECT RRES 5 16 SMB_CLK V18A 6 29 GND 15 SMB_DAT Figure 2: CHL8203 Package Top View 2 October 13, 2011 | FINAL | V1.3 VRRDY 7 8 9 10 11 12 13 14 SMB_CLK 12 PWM1 SMB_DAT 11 17 ENABLE 10 4 VIDSEL0 9 VRTN VIDSEL1 8 VIDSEL2 7 VINSEN VRRDY PWM2 VIDSEL2 29 GND 18 CHL8212 28 Pin 5X5 QFN Top View VINSEN CHL8203 28 Pin 5X5 QFN Top View Figure 3: CHL8212 Package Top View