IRF IR3570AMXXYYTRP

IR3564A
IR3570A
Dual Output Digital Multi-Phase Controller
FEATURES
DESCRIPTION
 Dual output 4+1 and 3+2 phase PWM Controllers
 Easiest layout and fewest pins in the industry
 Fully supports AMD® SVI1 & SVI2 with dual OCP
and Intel® VR12 & VR12.5
 Overclocking & Gaming Mode
 Switching frequency from 200kHz to 2MHz
per phase
 IR Efficiency Shaping Features including
Dynamic Phase Control and Automatic Power
State Switching
 Programmable 1-phase or 2-phase operation for
Light Loads and Active Diode Emulation for Very
Light Loads
 IR Adaptive Transient Algorithm (ATA) on both
loops minimizes output bulk capacitors and
system cost
 Auto-Phase Detection with auto-compensation
 Per-Loop Fault Protection: OVP, UVP, OCP,
OTP, CFP
 I2C/SMBus/PMBus system interface for telemetry
of Temperature, Voltage, Current & Power for
both loops
 Multiple Time Programming (MTP) with
integrated charge pump for easy custom
configuration
 Compatible with IR ATL and 3.3V tri-state Drivers
 +3.3V supply voltage; -40°C to 85°C ambient
operation
The IR3564A/70A is a dual-loop digital multi-phase buck
controller designed for CPU voltage regulation and is fully
compliant with AMD® SVI1 & SVI2 and Intel® VR12 & VR12.5
specifications.
The IR3564A/70A includes IR’s Efficiency Shaping Technology
to deliver exceptional efficiency at minimum cost across the
entire load range. IR’s Dynamic Phase Control adds/drops
active phases based upon load current and can be configured
to enter 1-phase operation and diode emulation mode
automatically or by command.
IR’s unique Adaptive Transient Algorithm (ATA), based on
proprietary non-linear digital PWM algorithms, minimizes
output bulk capacitors and Multiple Time Programmable
(MTP) storage saves pins and enables a small package size.
Device configuration and fault parameters are easily defined
using the IR Digital Power Design Center (DPDC) GUI and
stored in on-chip MTP.
The IR3564A/70A provides extensive OVP, UVP, OCP and OTP
fault protection and includes thermistor based temperature
sensing with VRHOT signal.
The IR3564A/70A includes numerous features like register
diagnostics for fast design cycles and platform differentiation,
simplifying VRD design and enabling fastest time-to-market
(TTM) with “set-and-forget” methodology.
APPLICATIONS
 AMD® SVI1 & SVI2, Intel® VR12 & VR12.5 based systems
 Desktop & Notebook CPU VRs
 Pb-Free, RoHS, 5x5mm, 40-pin, 0.4mm pitch QFN
BASIC APPLICATION
SVD
SVT/ALERT#
3.3V
Power
Stage 5
VOUT2
ISEN2_L2
IRTN2_L2
Figure 1: IR3564A/70A Basic Application Circuit
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August 9, 2012 | FINAL | Produc t Brief | V2.04
IRTN42/IRTN2_L21
IRTN1_L2
ISEN1_L2
ISEN3
ISEN42/ISEN2_L21
ISEN2
IRTN3
ISEN1
IRTN2
35
34
33
32
31
30
RCSP_L2
RCSM
2
29
RCSM_L2
VRDY2
3
28
VCC
VSEN
4
27
VSEN_L2
VRTN
5
26
VRTN_L2
RRES
6
25
PWM1_L2
TSEN1
7
24
PWM42/PWM2_L21
V18A
8
23
PWM3
22
PWM2
21
PWM1
PWRGD/
VRDY1
PWROK/EN_L2/
INMODE
9
10
IR3570A/IR3564A
40 Pin 5x5 QFN
Top View
1 = IR3570A
2 = IR3564A
11
12
13
41 GND
14
15
16
17
18
19
20
SM_DIO
SVD
36
SM_CLK
Power
Stage 4
SVC
37
ADDR_PROT
PWM1_L2
SVT/ALERT#
ISEN1_L2
IRTN1_L2
VCC
PWM2_L2
SVC
VOUT1
38
EN
Power
Stage 3
39
1
VRHOT_ICRIT#
PWM3
ISEN3
IRTN3
ENABLE
40
RCSP
SV_CLK/
VIDSEL1
SV_DIO/
VIDSEL0
ENABLE
...
IRTN1
VR_RDY_L2 ISEN1
IRTN1
VR_HOT#
VR_HOT#
SVT/
SV_ALERT
VR_RDY_L2
12V
Power
Stage 1
VINSEN
VR_RDY_L1 PWM1
PIN DIAGRAM
VDDIO/
SV_ADDR
IR3570A
VR_RDY_L1
 GPU & Memory VRs
Figure 2: IR3564A/70A Package Top View
IR3564A
IR3570A
Dual Output Digital Multi-Phase Controller
ORDERING INFORMATION
IR3564AM
IR3570AM        
Package
Packing
Qty
QFN
3000
IR3564AMTRPBF
IR3570AMTRPBF
QFN
3000
IR3564AMxxyyTRP
1
IR3570AMxxyyTRP
P/PBF – Lead Free
Part Number
Programming
Default
1
TR – Tape & Reel / TY - Tray
Customer
Configuration
yy – Configuration File ID
Notes:
1. Customer Specific Configuration File, where
xx = Customer ID and yy = Configuration File
(Codes assigned by IR Marketing).
xx – Customer ID
ISEN3
IRTN42/IRTN2_L21
ISEN42/ISEN2_L21
IRTN1_L2
ISEN1_L2
38
ISEN2
39
IRTN3
ISEN1
40
IRTN2
IRTN1
Package Type (QFN)
37
36
35
34
33
32
31
RCSP
1
30
RCSP_L2
RCSM
2
29
RCSM_L2
VRDY2
3
28
VCC
VSEN
4
27
VSEN_L2
VRTN
5
26
VRTN_L2
RRES
6
25
PWM1_L2
TSEN1
7
24
PWM42/PWM2_L21
V18A
8
23
PWM3
22
PWM2
21
PWM1
16
17
18
19
20
SM_DIO
SM_CLK
15
ADDR_PROT
14
EN
13
VRHOT_ICRIT#
12
41 GND
SV_CLK/
VIDSEL1
SV_DIO/
VIDSEL0
11
SVT/
SV_ALERT
10
1 = IR3570A
2 = IR3564A
VDDIO/
SV_ADDR
9
VINSEN
PWRGD/
VRDY1
PWROK/EN_L2/
INMODE
IR3570A/IR3564A
40 Pin 5x5 QFN
Top View
Figure 3: IR3564A/70A Pin Diagram Enlarge
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August 9, 2012 | FINAL | Produc t Brief | V2.04
IR3564A
IR3570A
Dual Output Digital Multi-Phase Controller
TYPICAL APPLICATION DIAGRAM
Vdrv
CCS
PWM1
ISEN1
IRTN1
RCSM
+3.3V
VCC
5V
IR3564A
IR3570A
VSEN
VRTN
LoGate
Boot
Vcc
CHL8505
HiGate
Switch
TSEN1
PWM
GND
5V
V_CPU_L1
L
O
A
D
12V
Vdrv
PWM2
ISEN2
IRTN2
RRES
PWM
GND
V
R series
CHL8505
HiGate
Switch
LoGate
12V
V
RCS
RTh
Boot
Vcc
RCSP
R series
12V
V
5V
RTh 2
Boot
Vcc
Vdrv
V18A
PWM
GND
PWM3
LoGate
ISEN3
VRDY1
IRTN3
IR3564A
Vin
CHL8505
HiGate
Switch
VRDY2
R VIN _ 1
5V
12V
V
VINSEN
R VIN _ 2
V
V
EN
PWROK/EN_L2/INMODE
VDDIO
V
V
LoGate
12V
Boot
Vcc
Vdrv
PWM1_L2
ISEN1_L2
IRTN1_L2
SM_DIO
SM_CLK
PWM
GND
CHL8505
HiGate
Switch
LoGate
V_CPU_L2
L
O
A
D
RCSP_L2
R series
RCS
R series
5V
VDDIO/SV_ADDR
Applicable circuit when pin is
configured as VDDIO only
RTh
PWM
GND
V
V
From
System
I2C Bus
Vdrv
SVT/SV_ALERT
SV_DIO
PWM2_L2/PWM4
SV_CLK
ISEN2_L2/ISEN4
IRTN2_L2/IRTN4
VRHOT_CRIT#
V
CPU
Serial
Bus
CHL8505
HiGate
Switch
IR3570A
Boot
Vcc
CCS
RCSM_L2
VSEN_L2
ADDR_PROT
VRTN_L2
GND
Figure 4: Dual-loop VR using IR3564A or IR3570A Controller and CHL8505 MOSFET Drivers in 4+1 or 3+2 Configuration
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August 9, 2012 | FINAL | Produc t Brief | V2.04
Dual Output Digital Multi-Phase Controller
IR3564A
IR3570A
Data and specifications subject to change without notice.
This product will be designed and qualified for the Consumer market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.
www.irf.com
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August 9, 2012 | FINAL | Produc t Brief | V2.04