ROHM BR25L020FVJ-WTR

TECHNICAL NOTE
High Reliability Series Serial EEPROM Series
SPI BUS Serial EEPROMs
Supply voltage 1.8V~5.5V
Operating temperature –40°C~+85°C type
BR25L010-W, BR25L020-W, BR25L040-W, BR25L080-W, BR25L160-W, BR25L320-W, BR25L640-W
● Description
BR25L□□□-W series is a serial EEPROM of SPI BUS interface method.
Features
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High speed clock action up to 5MHz (Max.)
Wait function by HOLD terminal
Part or whole of memory arrays settable as read only memory area by program
1.8 ~ 5.5V single power source action most suitable for battery use
Page write mode useful for initial value write at factory shipment
Highly reliable connection by Au pad and Au wire
For SPI bus interface (CPOL, CPHA) = (0, 0), (1, 1)
Auto erase and auto end function at data rewrite
Low current consumption
At write action (5V)
: 1.5mA (Typ.)
At read action (5V)
: 1.0mA (Typ.)
Page write
At standby action (5V) : 0.1μA (Typ.)
Number
of
Address auto increment function at read action
pages
Write mistake prevention function
Write prohibition at power on
Write prohibition by command code (WRDI)
Product
Write prohibition by WP pin
number
Write prohibition block setting by status registers (BP1, BP0)
Write mistake prevention function at low voltage
SOP8, SOP-J8, SSOP-B8, TSSOP-B8, MSOP8 TSSOP-B8J package *1 *2
Data at shipment Memory array : FFh, status register WPEN, BP1, BP0 : 0
Data kept for 40 years
Data rewrite up to 1,000,000 times
16 Byte
32 Byte
BR25L010-W
BR25L020-W
BR25L040-W
BR25L080-W
BR25L160-W
BR25L320-W
BR25L640-W
*1 BR25L080/160-W : SOP8, SOP-J8, SSOP-B8, TSSOP-B8
*2 BR25L320/640-W : SOP8, SOP-J8
BR25L series
Capacity
Bit format
Type
Power source
voltage
1Kbit
128 X 8
BR25L010-W
1.8 ~ 5.5V
2Kbit
256 X 8
BR25L020-W
1.8 ~ 5.5V
4Kbit
512 X 8
BR25L040-W
1.8 ~ 5.5V
8Kbit
1K X 8
BR25L080-W
1.8 ~ 5.5V
16Kbit
2K X 8
BR25L160-W
1.8 ~ 5.5V
32Kbit
4K X 8
BR25L320-W
1.8 ~ 5.5V
64Kbit
8K X 8
BR25L640-W
1.8 ~ 5.5V
SOP8
F
SOP-J8
FJ
SSOP-B8
FV
TSSOP-B8
FVT
MSOP8
TSSOP-B8J
FVM
FVJ
Oct. 2008
Recommended action conditions
Absolute maximum ratings (Ta = 25˚C)
Parameter
Impressed voltage
Symbol
VCC
Permissible
dissipation
Pd
Parameter
Power source voltage
Input voltage
Unit
V
Limits
-0.3 ~ +6.5
450(SOP8)
*1
450(SOP-J8)
*2
300(SSOP-B8)
*3
Storage
temperature range
Operating
temperature range
Terminal voltage
*5
310(TSSOP-B8J)
*6
Parameter
Number of data rewrite times
Data hold years
–
Unit
V
*1
*1
Min.
1,000,000
40
Limits
Typ.
Max.
–
–
–
–
Unit
Times
Years
*1:Not 100% TESTED
˚C
˚C
V
-65 ~ +125
-40 ~ +85
-0.3 ~ VCC+0.3
Tstg
Topr
Limits
1.8 ~ 5.5
0 ~ VCC
Memory cell characteristics (Ta=25˚C, VCC=1.8 ~ 5.5V)
mW
330(TSSOP-B8) *4
310(MSOP8)
Symbol
VCC
Vin
Input / output capacity (Ta=25˚C, frequency=5MHz)
Parameter
Input capacity *1
Output capacity *1
･When using at Ta = 25˚C or higher, 4.5mW (*1, *2), 3.0mW (*3),
3.3mW(*4), 3.1mW (*5, *6) to be reduced per 1˚C
Symbol Conditions
CIN
VIN=GND
COUT VOUT=GND
Min.
–
–
Max.
8
8
Unit
pF
pF
*1:Not 100% TESTED
Electrical characteristics (Unless otherwise specified, Ta = –40 ~ +85˚C, VCC = 1.8 ~ 5.5V)
Parameter
Symbol
Limits
Typ.
Min.
0.7x
–
VCC
"H" input voltage 1
VIH1
"L" input voltage 1
VIL1
-0.3
–
"L" output voltage 1
"L" output voltage 2
VOL1
VOL2
"H" output voltage 1
VOH1
0
0
VCC
-0.5
"H" output voltage 2
VOH2
Input leak current
Output leak current
Current consumption at write
action
Current consumption at read
action
Standby current
Unit
Max.
VCC
+0.3
Conditions
V
1.8≤VCC≤5.5V
V
1.8≤VCC≤5.5V
–
–
0.3x
VCC
0.4
0.2
V
V
IOL=2.1mA(VCC=2.5V ~ 5.5V)
IOL=150µA(VCC=1.8V ~ 2.5V)
–
VCC
V
IOH=-0.4mA(VCC=2.5V ~ 5.5V)
VCC
-0.2
–
VCC
V
IOH=-100µA(VCC=1.8V ~ 2.5V)
ILI
ILO
-1
-1
–
–
1
1
µA
µA
ICC1
–
–
1.0
mA
ICC2
–
–
2.0
mA
ICC3
–
–
3.0
mA
ICC4
–
–
1.5
mA
ICC5
–
–
2.0
mA
ISB
–
–
2
µA
VIN=0 ~ VCC
VOUT=0 ~ VCC,CS=VCC
VCC=1.8V,fSCK=2MHz,tE/W=5ms
Byte write
Page write
Write status register
VCC=2.5V,fSCK=5MHz,tE/W=5ms
Byte write
Page write
Write status register
VCC=5.5V,fSCK=5MHz,tE/W=5ms
Byte write
Page write
Write status register
VCC=2.5V,fSCK=5MHz
Read
Read status register
VCC=5.5V,fSCK=5MHz
Read
Read status register
VCC=5.5V
CS=HOLD=WP=VCC,SCK=SI=VCC or =GND,SO=OPEN
• Radiation resistance design is not made.
Block diagram
CS
VOLTAGE
DETECTION
INSTRUCTION DECODE
CONTROL CLOCK
SCK
SI
HOLD
WP
SO
GENERATION
WRITE
INHIBITION
HIGH VOLTAGE
GENERATOR
INSTRUCTION
REGISTER
STATUS REGISTER
ADDRESS
REGISTER
7~13bit *1
DATA
REGISTER
8bit
ADDRESS
DECODER
READ/WRITE
AMP
Fig.1 Block diagram
2/16
7~13bit *1
1K~64K
EEPROM
8bit
*1 7bit : BR25L010-W
8bit : BR25L020-W
9bit : BR25L040-W
10bit : BR25L080-W
11bit : BR25L160-W
12bit : BR25L320-W
13bit : BR25L640-W
Pin assignment and description
VCC
HOLD
SCK
Terminal name Input/output
BR25L010-W
BR25L020-W
BR25L040-W
BR25L080-W
BR25L160-W
BR25L320-W
BR25L640-W
CS
SO
WP
–
–
VCC
SI
GND
Function
Power source to be connected
GND
CS
SCK
SI
SO
Input
Input
Input
Output
HOLD
Input
WP
Input
All input / output reference voltage, 0V
Chip select input
Serial clock input
Start bit, ope code, address, and serial data input
Serial data output
Hold input
Command communications may be suspended temporarily (HOLD status).
Write protect input
Write command is prohibited.*1
Write status register command is prohibited.
Fig. 2 Pin assignment diagram
*1:BR25L010/020/040-W
Sync data input / output timing
Operating timing characteristics
(Ta = -40 ~ +85˚C, unless otherwise specified, load capacity CL1 100pF)
Parameter
Symbol
fSCK
SCK frequency
tSCKWH
SCK high time
tSCKWL
SCK low time
tCS
CS high time
tCSS
CS setup time
tCSH
CS hold time
SCK setup time
tSCKS
SCK hold time
tSCKH
tDIS
SI setup time
tDIH
SI hold time
tPD1
Data output delay time 1
Data output delay time 2
tPD2
(CL2=30pF)
1.8≤VCC<2.5V
2.5≤VCC<5.5V
Unit
Min. Typ. Max. Min. Typ. Max.
2
5
MHz
–
–
–
–
200
85
–
–
–
–
ns
85
200
–
–
–
–
ns
85
200
–
–
–
–
ns
ns
200
–
–
90
–
–
ns
200
–
–
85
–
–
90
200
–
–
–
–
ns
90
200
–
–
–
–
ns
20
40
–
–
–
–
ns
40
50
–
–
–
–
ns
ns
–
–
150
–
–
70
–
–
145
0
Fig. 3 Input timing
SI is taken into IC inside in sync with data rise edge of SCK. Input
address and data from the most significant bit MSB.
tCS
CS
–
SI
0
–
–
–
100
ns
ns
tHFS
120
–
–
60
–
–
ns
HOLD setting
hold time
tHFH
90
–
–
40
–
–
ns
HOLD release
setup time
tHRS
120
–
–
60
–
–
ns
HOLD release
hold time
tHRH
140
–
–
70
–
–
ns
High-Z
SO
SCK
–
tCSH tSCKH
tPD
tRO,tFO tOZ
tOH
High-Z
SO
Fig. 4 Input / output timing
SO is output in sync with data fall edge of SCK. Data is output
from the most significant bit MSB.
CS
"H"
"L"
tHFS tHFH
tHRS tHRH
SCK
tDIS
Time from HOLD
to output High-Z
tHOZ
–
–
250
–
–
100
ns
Time from HOLD
to output change
tHPD
–
–
150
–
–
70
ns
tRC
–
–
1
–
–
1
µs
tFC
–
–
1
–
–
1
µs
tRO
–
–
100
–
–
50
ns
tFO
–
–
100
–
–
50
ns
tE/W
–
–
5
–
–
5
ms
SCK
rise time
*1
SCK
fall time
*1
OUTPUT
rise time
*1
OUTPUT
fall time
*1
Write time
tDIS tDIH
ns
250
*1NOT 100% TESTED
AC measurement conditions
Parameter
Load capacity 1
Load capacity 2
Input rise time
Input fall time
Input voltage
Input / output judgment voltage
Symbol
CL1
CL2
–
–
–
–
Limits
Unit
Typ. Max.
100
pF
–
–
–
–
30
pF
–
–
50
ns
–
–
50
ns
0.2VCC/0.8VCC
V
0.3VCC/0.7VCC
V
Min.
3/16
tFC
SI
55
–
–
tRC
tSCKWL tSCKWH
SCK
–
–
tCSS
tSCKS
–
tOH
tOZ
Output hold time
Output disable time
HOLD setting
setup time
tCS
CS
SI
n+1
n
tHOZ
SO
Dn+1
Dn
High-Z
n-1
tHPD
Dn
HOLD
Fig. 5 HOLD timing
Dn-1
6
6
5
5
4
4
1
0.8
0.6
Ta=85˚C
3
VOL[V]
SPEC
3
VIL[V]
VIH[V]
Characteristic data (The following characteristic data are Typ. values.)
Ta=25˚C
Ta=-40˚C
Ta=85˚C
Ta=25˚C
0.4
2
2
SPEC
Ta=85˚C
Ta=25˚C
1
0.2
1
Ta=-40˚C
0 0
1
2
SPEC
3
4
5
0
6
0
1
2
3
4
5
0
6
Ta=-40˚C
0
1
2
3
Fig.6 "H" input voltage VIH(CS,SCK,SI,HOLD,WP)
Fig.7 "L" input voltage VIL(CS,SCK,SI,HOLD,WP)
2
4
5
6
IOL[mA]
VCC[V]
VCC[V]
Fig.8 "L" output voltage VOL-IOL(VCC=1.8V)
2.6
1
Ta=-40˚C
Ta=-40˚C
0.8
2.4
Ta=25˚C
Ta=85˚C
SPEC
1.4
VOH[V]
0.6
1.6
VOL[V]
VOH[V]
1.8
SPEC
Ta=85˚C
Ta=25˚C
0.4
Ta=25˚C
2.2
Ta=85˚C
SPEC
2
0.2
Ta=-40˚C
1.2
0
0.4
IOH[mA]
0
0.8
0
1
2
3
4
1.8
5
0
IOL[mA]
Fig.9 "H" output voltage VOH-IOH(VCC=1.8V)
Fig.11 "H" output voltage VOH-IOH(VCC=2.5V)
VCC=2.5V 2mA
VCC=5.5V 3mA
4
1.2
SPEC
SPEC
fSCK=5MHz
1
1
ILO[ µA]
ILI[ µA]
0.8
0.4
1
2
3
4
5
Ta=85˚C
Ta=25˚C
0.2
Ta=-40˚C
0
0.6
0.4
Ta=85˚C
Ta=25˚C
0.2
ICC2,3[mA]
0.8
0.8
0
6
Ta=25˚C
Ta=-40˚C
1
Ta=85˚C
Ta=-40˚C
0
1
2
3
4
5
0
6
0
1
2
3
4
5
VCC[V]
VCC[V]
VCC[V]
Fig.13 Output leak current ILO(SO)
Fig.14 Current consumption at WRITE operation
ICC1,2,3(WRITE,PAGE WRITE,WRSR,fSCK=5MHz)
BR25L010-W,BR25L020-W,BR25L040-W
Vcc=2.5V 1.5mA
Vcc=5.5V 2.0mA
fSCK=5MHz
2.5
100
2
SPEC
Ta=25˚C
1
Ta=85˚C
0.5
0
1
2
3
4
1
0
6
0
1
2
3
4
SPEC
SPEC
1
Ta=85˚C
Ta=25˚C
Ta=-40˚C
0.5
5
Ta=85˚C
10
1.5
fSCK[MHz]
ISB[µA]
Ta=-40˚C
1.5
0
5
0.1
6
0
1
2
3
4
VCC[V]
VCC[V]
VCC[V]
Fig.15 Consumption current at READ operation
ICC4,5(READ,WRSR,fSK=5MHz)
Fig.16 Consumption current at standby operation ISB
Fig.17 SCK frequency fSCK
250
250
150
SPEC
100
Ta=-40˚C
0
0
1
200
150
150
SPEC
100
Ta=85˚C
2
3
4
VCC[V]
Fig.18 tSCK high time tSCKWH
5
6
0
5
6
SPEC
100
Ta=-40˚C
Ta=25˚C
50
Ta=25˚C
6
SPEC
200
tCS[ns]
tSCKWL[ns]
200
5
250
SPEC
SPEC
50
6
Ta=25˚C
Ta=-40˚C
SPEC
SPEC
DATA=55h
2
ICC4,5[mA]
SPEC
2
Fig.12 Input leak current ILI(CS,SCK,SI,WP,HOLD)
2.5
tSCKWH[ns]
SPEC
DATA=55h
3
0
0.8
IOH[mA]
Fig.10 "L" output voltage VOL-IOL(VCC=2.5V)
1.2
0.4
Ta=85˚C
50
Ta=85˚C
0
1
2
3
4
VCC[V]
Fig.19 SCK low time tSCKWL
4/16
5
6
0
0
1
2
Ta=25˚C
Ta=-40˚C
3
VCC[V]
Fig.20 CS high time tCS
4
250
60
250
SPEC
200
SPEC
200
SPEC
40
SPEC
100
50
100
SPEC
50
Ta=85˚C
Ta=25˚C
Ta=85˚C Ta=25˚C
Ta=-40˚C
0
-50
150
0
1
2
3
VCC[V]
4
5
0
6
20
tDIS[ns]
tCSH[ns]
tCSS[ns]
150
0
Ta=85˚C
-20
Ta=-40˚C
Ta=-40˚C Ta=25˚C
0
1
Fig.21 CS setup time tCSS
2
3
VCC[V]
4
5
-40
6
0
1
Fig.22 CS hold time tCSH
2
3
VCC[V]
4
5
6
5
6
Fig.23 SI setup time tDIS
200
200
60
SPEC
50
SPEC
SPEC
SPEC
150
150
SPEC
30
Ta=85˚C Ta=-40˚C
tPD2[ns]
tPD1[ns]
tDIH[ns]
40
100
Ta=85˚C
Ta=85˚C
100
SPEC
SPEC
20
50
10
Ta=25˚C
Ta=25˚C
0
1
2
3
VCC[V]
4
5
Ta=25˚C
0
6
Fig.24 SI hold time tDIH
2
3
VCC[V]
5
6
tHFH[ns]
SPEC
Ta=85˚C
50
0
1
SPEC
2
3
VCC[V]
4
5
-20
6
0
1
Ta=25˚C
2
3
VCC[V]
4
Ta=-40˚C Ta=85˚C
0
5
6
-30
0
1
tRO[ns]
tHPD[ns]
40
60
SPEC
Ta=85˚C
0
1
2
3
VCC[V]
4
5
6
-40
Fig.30 Time from HOLD to output High-Z tHOZ
Ta=25˚C
0
1
2
Ta=-40˚C
3
VCC[V]
4
5
6
Fig.31 Time from HOLD to output change tHPD
10
120
SPEC
8
60
tE/W[ms]
tFO[ns]
90
SPEC
6
SPEC
Ta=-40˚C
4
Ta=85˚C
30
Ta=25˚C
Ta=85˚C
2
Ta=25˚C
Ta=-40˚C
0
0
1
2
3
VCC[V]
4
Fig.33 Output fall time
5
6
0
0
1
Ta=25˚C
30
Ta=85˚C
0
Ta=-40˚C
6
SPEC
100
0
5
SPEC
80
Ta=85˚C
Ta=25˚C
4
90
200
SPEC
3
VCC[V]
120
SPEC
120
50
2
Ta=25˚C
Fig.29 HOLD release hold time tHRH
160
150
SPEC
Fig.28 HOLD setting hold time tHFH
SPEC
250
SPEC
60
Ta=-40˚C
Fig.27 Output disable time tOZ
300
4
30
Ta=85˚C
0
Ta=-40˚C
3
VCC[V]
90
60
20
Ta=25˚C
2
Fig.26 Data output delay time tPD2(CL=30pF)
SPEC
80
40
100
1
120
100
150
0
150
120
200
tHFH[ns]
4
140
SPEC
250
tOZ[ns]
1
Fig.25 Data output delay time tPD1(CL=100pF)
300
0
0
Ta=-40˚C
0
tHRH[ns]
0
50
Ta=-40˚C
2
3
VCC[V]
4
5
Fig.34 Write cycle time tE/W
5/16
6
0
Ta=-40˚C
0
1
2
3
VCC[V]
4
5
Fig.32 Output rise time tRO
6
Features
Status registers
This IC has status registers. The status registers are of 8 bits and express the following parameters.
BP0 and BP1 can be set by write status register command. These 2 bits are memorized into the EEPROM, therefore are
valid even when power source is turned off.
Rewrite characteristics and data hold time are same as characteristics of the EEPROM.
WEN can be set by write enable command and write disable command. WEN becomes write disable status when power
source is turned off. R/B is for write confirmation, therefore cannot be set externally.
The value of status register can be read by read status command.
Status registers
Product number
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
1
1
1
1
BP1
BP0
WEN
R/B
WPEN
0
0
0
BP1
BP0
WEN
R/B
BR25L010-W
BR25L020-W
BR25L040-W
BR25L080-W
BR25L160-W
BR25L320-W
BR25L640-W
bit
Memory
location
WPEN
EEPROM
BP1
BP0
Function
WP pin enable / disable designation bit
Register
R/B
Register
This enables / disables the functions
of WP pin.
WPEN = 0 = invalid
WPEN = 1 = valid
EEPROM
WEN
Contents
This designates the write disable area
of EEPROM. Write designation areas
of product numbers are shown below.
EEPROM write disable block designation bit
Write and write status register write enable / disable status confirmation bit
WEN = 0 = prohibited
WEN = 1 = permitted
Write cycle status (READY / BUSY) status confirmation bit
R/B=0=READY
R/B=1=BUSY
Write disable block setting
Write disable block
BP1
BP0
BR25L010-W
BR25L020-W
BR25L040-W
BR25L080-W
BR25L160-W
BR25L320-W
BR25L640-W
0
0
None
None
None
None
None
None
None
0
1
60h-7Fh
C0h-FFh
180h-1FFh
300h-3FFh
600h-7FFh
C00h-FFFh
1800h-1FFFh
1
0
40h-7Fh
80h-FFh
100h-1FFh
200h-3FFh
400h-7FFh
800h-FFFh
1000h-1FFFh
1
1
00h-7Fh
00h-FFh
000h-1FFh
000h-3FFh
000h-7FFh
000h-FFFh
0000h-1FFFh
WP pin
By setting WP = LOW, write command is prohibited. As for BR25L080, 160, 320, 640-W, only when WPEN bit is set "1",
the WP pin functions become valid. And the write command to be disabled at this moment is WRSR. As for BR25L010,
020, 040-W, both WRITE and WRSR commands are prohibited.
However, when write cycle is in execution, no interruption can be made.
Product number
BR25L010-W
BR25L020-W
BR25L040-W
WRSR
WRITE
Prohibition
possible
Prohibition
possible
Prohibition
possible but
WPEN bit "1"
Prohibition
impossible
BR25L080-W
BR25L160-W
BR25L320-W
BR25L640-W
HOLD pin
By HOLD pin, data transfer can be interrupted. When SCK = "1", by making HOLD from "1" into "0", data transfer to
EEPROM is interrupted. When SCK = "0", by making HOLD from "0" into "1", data transfer is restarted.
6/16
Command mode
Ope code
Contents
Command
BR25L010-W
BR25L020-W
BR25L040-W
BR25L080-W
BR25L160-W
BR25L320-W
BR25L640-W
* 110
0000
0110
WREN Write enable
Write enable command
0000
* 110
0000
WRDI
Write disable
Write disable command
0000
* 100
0000
* 100
0000
0100
READ
Read
Read command
0000
* 011
0000
A8011
0000
0011
WRITE Write
Write command
0000
* 010
0000
A8010
0000
0010
RDSR
Read status register
Status register read
command
0000
* 101
0000
* 101
0000
0101
WRSR Write status register
Status register write
command
0000
* 001
0000
* 001
0000
0001
Timing chart
1. Write enable (WREN) / disable (WRDI) cycle
1.WREN (WRITE ENABLE) : Write enable
CS
SCK
SI
SO
0
0
1
0
2
0
3
0
4
*1
5
1
6
7
1
0
High-Z
Fig. 35 Write enable command
*1 BR25L010/020/040-W=Don't care
BR25L080/160/320/640-W=“0” input
1.WRDI (WRITE DISABLE) : Write disable
CS
SCK
SI
SO
0
0
1
0
2
0
3
0
4
*1
5
1
6
0
7
0
High-Z
Fig. 36 Write disable
*1 BR25L010/020/040-W=Don't care
BR25L080/160/320/640-W=“0” input
This IC has write enable status and write disable status. It is set to write enable status by write enable command, and it is
set to write disable status by write disable command. As for these commands, set CS LOW, and then input the respective
ope codes. The respective commands accept command at the 7-th clock rise. Even with input over 7 clocks, command
becomes valid.
When to carry out write and write status register command, it is necessary to set write enable status by the write enable
command. If write or write status register command is input in the write disable status, commands are cancelled. And even
in the write enable status, once write and write status register command is executed once, it gets in the write disable
status. After power on, this IC is in write disable status.
7/16
2. Read command (READ)
CS
SCK
0
0
SI
SO
1
0
2
3
0
4
5
*1
0
6
0
7
1
8
A7
1
9
10
A5
A6
11
14
A4
A1
15
16
17
22
A0
High-Z
D7
D2
D6
D1
D0
Product
number
Address
length
BR25L010-W
A6-A0
BR25L020-W
A7-A0
BR25L040-W
A8-A0
Product
number
Address
length
Fig. 37 Read command (BR25L010/020/040-W) * 1 BR25L010/020-W=Don't care
BR25L040-W=A8
CS
SCK
0
0
SI
SO
1
2
0
3
0
4
0
5
0
6
0
7
1
23
8
*
1
*
*
A12
A1
24
30
A0
High-Z
D7
D2
D6
D1
D0
* =Don't care
Fig. 38 Read command (BR25L080/160/320/640-W)
BR25L080-W
A9-A0
BR25L160-W
A10-A0
BR25L320-W
A11-A0
BR25L640-W
A12-A0
By read command, data of EEPROM can be read. As for this command, set CS LOW, then input address after read ope
code. EEPROM starts data output of the designated address. Data output is started from SCK fall of 15/23*1 clock, and
from D7 to D0 sequentially. This IC has increment read function. After output of data for 1 byte (8 bits), by continuing input
of SCK, data of the next address can be read. Increment read can read all the addresses of EEPROM. After reading data
of the most significant address, by continuing increment read, data of the most insignificant address is read.
* =Don't care
* 1 BR25L010/020/040-W=15 clocks
BR25L080/160/320/640-W=23 clocks
3. Write command (WRITE)
CS
0
SCK
SI
SO
0
1
0
2
0
3
0
4
*1
5
0
6
1
7
8
A7
0
15
A6
A5
A4
A1
A0
16
D7
22
D6
D2
D1
23
D0
BR25L010-W
A6-A0
BR25L020-W
A7-A0
BR25L040-W
A8-A0
Product
number
Address
length
BR25L080-W
A9-A0
BR25L160-W
A10-A0
BR25L320-W
A11-A0
BR25L640-W
A12-A0
* 1 BR25L010/020-W=Don't care
BR25L040-W=A8
CS
0
SCK
0
SO
Address
length
High-Z
Fig.39 Write command (BR25L010/020/040-W)
SI
Product
number
1
0
2
0
3
0
4
0
5
0
6
1
7
0
8
*
23
*
*
A12
A1
A0
24
D7
30
D6
High-Z
D2
D1
31
D0
* =Don't care
Fig.40 Write command (BR25L080/160/320/640-W)
By write command, data of EEPROM can be written. As for this command, set CS LOW, then input address and data
after write ope code. Then, by making CS HIGH, the EEPROM starts writing. The write time of EEPROM requires time of
tE/W (Max 5ms). During tE/W, other than status read command is not accepted. Start CS after taking the last data (D0),
and before the next SCL clock starts. At other timing, write command is not executed, and this write command is
cancelled. This IC has page write function, and after input of data for 1 byte (8 bits), by continuing data input without
starting CS, data up to 16/32*1 bytes can be written for one tE/W. In page write, the insignificant 4/5*2 bit of the
designated address is incremented internally at every time when data of 1 byte is input, and data is written to respective
addresses. When data of the maximum bytes or higher is input, address rolls over, and previously input data is
overwritten.
* 1 BR25L010/020/040-W=16 bytes at maximum
BR25L080/160/320/640-W=32 bytes at maximum
* 2 BR25L010/020/040-W=Insignificant 4 bits
BR25L080/160/320/640-W=Insignificant 5 bits
8/16
4. Status register write / read command
CS
0
SCK
0
SI
SO
1
2
0
3
0
4
5
*
0
6
7
0
0
1
8
9
10
11
bit7
bit6
bit5
bit4
*
*
*
*
12
bit3
13
bit2
BP1 BP0
14
15
bit1
bit0
*
*
High-Z
* =Don't care
Fig.41 Status register write command (BR25L010/020/040-W)
CS
0
SCK
SI
SO
1
0
2
0
3
0
4
0
5
0
0
6
0
7
1
8
9
10
11
bit7
bit6
bit5
bit4
WPEN
*
*
*
12
bit3
13
bit2
BP1 BP0
14
15
bit1
bit0
*
*
High-Z
* =Don't care
Fig.42 Status register write command (BR25L080/160/320/640-W)
Write status register command can write status register data. The data the can be written by this command are 2 bits *1,
that is, BP1 (bit3) and BP0 (bit2) among 8 bits of status register. By BP1 and BP0, write disable block of EEPROM can be
set. As for this command, set CS LOW, and input ope code of write status register, and input data. Then, by making CS
HIGH, EEPROM starts writing. Write time requires time of tE/W as same as write. As for CS rise, start CS after taking the
last data bit (bit0), and before the next SCK clock starts. At other timing, command is cancelled. Write disable block is
determined by BP1 and BP0, and the block can be selected from 1/4 of memory array, 1/2, and entire memory array.
(Refer to the write disable block setting table.) To the write disabled block, write cannot be made, and only read can be
made.
* 3 bits including BR25L080, 160, 320, 640-W WPEN (bit7)
CS
0
SCK
SI
SO
0
1
0
2
0
3
4
*
0
5
1
6
0
7
8
9
10
11
12
13
14
15
1
High-Z
bit7
bit6
bit5
bit4
1
1
1
1
bit3
bit2
bit1
bit0
BP1 BP0 WEN R/B
* =Don't care
Fig.43 Status register read command (BR25L010/020/040-W)
CS
0
SCK
SI
SO
0
1
0
2
0
3
0
4
0
5
1
6
0
7
8
9
10
11
bit7
bit6
bit5
bit4
WPEN
0
0
0
12
13
14
15
bit3
bit2
bit1
bit0
BP1 BP0 WEN
R/B
1
High-Z
Fig.44 Status register read command (BR25L080/160/320/640-W)
9/16
At standby
Current at standby
Set CS "H", and be sure to set SCK, SI, WP, HOLD input "L" or "H". Do not input intermediate electric potential.
Timing
As shown in Fig. 45, at standby, when SCK is "H", even if CS is fallen, SI status is not read at fall edge. SI status is read
at SCK rise edge after fall of CS. At standby and at power ON/OFF, set CS "H" status.
Even if CS is fallen at SCL = SI = "H",
SI status is not read at that edge.
CS
Command start here. SI is read.
0
SCK
1
2
SI
Fig.45 Operating timing
WP cancel valid area
WP is normally fixed to "H" or "L" for use, but when WP is controlled so as to cancel write status register command and write
command, pay attention to the following WP valid timing.
While write or write status register command is executed, by setting WP = "L" in cancel valid area, command can be
cancelled. The area from command ope code before CS rise at internal automatic write start becomes the cancel valid area.
However, once write is started, any input cannot be cancelled. WP input becomes Don't Care, and cancellation becomes
invalid.
SCK
15
16
CS
Ope code
Data
tE/W
data write time
WP cancel invalid area
WP cancel invalid area
WP cancel invalid area
invalid
Fig.46 WP valid timing (WRSR)
Ope code
Address
Data
WP cancel invalid area
WP cancel invalid area
invalid
valid
tE/W
data write time
WP cancel invalid area
Fig.47 WP valid timing (WRITE)
HOLD pin
By HOLD pin, command communication can be stopped temporarily. (HOLD status) The HOLD pin carries out command
communications normally when it is HIGH. To get in HOLD status, at command communication, when SCK = LOW, set
the HOLD pin LOW. At HOLD status, SCK and SI become Don't Care, and SO becomes high impedance (High-Z). To
release the HOLD status, set the HOLD pin HIGH when SCK = LOW. After that, communication can be restarted from the
point before the HOLD status. For example, when HOLD status is made after A5 address input at read, after release of
HOLD status, by starting A4 address input, read can be restarted. When in HOLD status, leave CS LOW. When it is set
CS = HIGH in HOLD status, the IC is reset, therefore communication after that cannot be restarted.
10/16
Method to cancel each command
READ
･ Method to cancel : cancel by CS = "H"
Ope code
Address
Data
8 bits
8 bits /16bits
8 bits
Cancel available in all areas of read mode
Fig.48 READ cancel valid timing
RDSR
･ Method to cancel : cancel by CS = "H"
Ope code
Data
8 bits
8 bits
Cancel available in all
areas of read mode
Fig.49 RDSR cancel valid timing
WRITE, PAGE WRITE
a : Ope code, address input area.
Cancellation is available by CS = "H".
b : Data input area (D7 ~ D1 input area)
Cancellation is available by CS = "H".
c : Data input area (D0 area)
When CS is started, write starts.
After CS rise, cancellation cannot be made by any
means.
d : tE/W area
Cancellation is available by CS = "H". However, when
write starts (CS is started) in the area c, cancellation
cannot be made by any means. And, by inputting on
SCK clock, cancellation cannot be made. In page write
mode, there is write enable area at every 8 clocks.
Ope code
Address
Data (n)
8 bits
8 bits
8 bits
a
b
tE/W
d
c
Fig.50 WRITE cancel valid timing
SCK
SI
D7
D6
D5
D4
D2
D3
D1
D0
b
c
Note 1) If Vcc is made OFF during write execution, designated address data is not guaranteed, therefore write it once
again.
Note 2) If CS is started at the same timing as that of the SCK rise, write execution / cancel becomes unstable,
therefore, it is recommended to fall in SCK = "L" area. As for SCK rise, assure timing of tCSS / tCSH or higher.
WRSR
a : From ope code to 15 clock rise
Cancel by CS = "H".
b : From 15 clock rise to 16 clock rise (write enable area)
When CS is started, write starts.
After CS rise, cancellation cannot be made by any
means.
c : After 16 clock rise
Cancel by CS = "H". However, when write starts (CS is
started) in the area b, cancellation cannot be made by
any means. And, by inputting on SCK clock, cancellation
cannot be made.
SCK
SI
14
D1
15
b
c
Address
8 bit
17
D0
a
Ope code
16
tE/W
8 bit
a
c
b
Fig.51 WRSR cancel valid timing
Note 1) If Vcc is made OFF during write execution, designated address data is not guaranteed, therefore write it once
again.
Note 2) If CS is started at the same timing as that of the SCK rise, write execution / cancel becomes unstable,
therefore, it is recommended to fall in SCK = "L" area. As for SCK rise, assure timing of tCSS/tCSH or higher.
WREN/WRDI
a : From ope code to clock rise, cancel by CS = "H".
b : Cancellation is not available when CS is started after 7 clock.
SCK
7
a
8
9
b
Ope code
8 bit
a
b
Fig.52 WREN / WRDI cancel valid timing
11/16
High speed operation
In order to realize stable high speed operations, pay attention to the following input / output pin conditions.
Input pin pull up, pull down resistance
When to attach pull up, pull down resistance to EEPROM input pin, select an appropriate value for the microcontroller
VOL, IOL from VIL characteristics of this IC.
Pull up resistance
Microcontroller
IOHM
EEPROM
VOLM
VILE
"L" output
"L" input
RPU ≥
VCC - VOLM
IOLM
VOLM ≤
VILE
Example) When Vcc = 5V, VILM = 1.5V, VOLM = 0.4V, IOLM = 2mA,
from the equation
,
Fig.53 Pull up resistance
RPU≥
5-0.4
2 X 10-3
RPU≥
2.3[kΩ]
With the value of Rpu to satisfy the above equation, VOLM
becomes 0.4V or higher, and with VILE (= 1.5V), the equation
is also satisfied.
● VILM : EEPROM VIH specifications
● VOLM : Microcontroller VOL specifications
● IOLM : Microcontroller IOL specifications
And, in order to prevent malfunction, mistake write at power ON/OFF, be sure to make CS pull up.
Pull down resistance
EEPROM
RPD ≥
VOHM
IOHM
VOHM ≥
VIHE
VIHE
VOHM
IOHM
Example) When Vcc = 5V, VOHM = Vcc - 0.5V, IOHM = 0.4mA,
,
VIHM = Vcc X 0.7V, from the equation
Fig.54 Pull down resistance
RPD≥
5-0.5
0.4 X 10-3
RPD≥
11.3[kΩ]
Further, by amplitude VIHE, VILE of signal input to EEPROM, operation speed changes. By inputting signal of amplitude of
VCC / GND level to input, more stable high speed operations can be realized. On the contrary, when amplitude of 0.8VCC /
0.2VCC is input, operation speed becomes slow.
12/16
In order to realize more stable high speed operation, it is recommended to make the values of RPU, RPD as large as
possible, and make the amplitude of signal input to EEPROM close to the amplitude of VCC / GND level.
(*1 At this moment, operating timing guaranteed value is guaranteed.)
tPD-VIL characteristics
80
75
tPD [ns]
70
65
VCC=1.8V
Ta=25°C
VIH=VCC
CL=100pF
60
55
0
0.2
0.4
0.6
0.8
1
VIL[V]
Fig.55 VIL dependency of
data output delay time
SO load capacity condition
Load capacity of SO output pin affects upon delay characteristic of SO output. (Data output delay time, time from HOLD
to High-Z) In order to make output delay characteristic into higher speed, make SO load capacity small. In concrete, "Do
not connect many devices to SO bus", "Make the wire between the controller and EEPROM short", and so forth.
tPD-CL characteristics
80
VCC=1.8V Ta=25°C
VIH/VIL=0.8VCC/0.2VCC
EEPROM
tPD [ns]
70
SO
60
CL
50
40
0
20
40
60
80
100
120
CL [V]
Fig.56 SO load dependency of data output delay time
Other cautions
Make the wire length from the microcontroller to EEPROM input signal same length, in order to prevent setup / hold violation
to EEPROM, owing to difference of wire length of each input.
13/16
Equivalent circuit
Output circuit
SO
OEint.
Fig.57 SO output equivalent circuit
Input circuit
RESETint.
CS
Fig.58 CS input equivalent circuit
SCK
SI
Fig.59 SCK input equivalent circuit
Fig.60 SI input equivalent circuit
WP
HOLD
Fig.61 HOLD input equivalent circuit
Fig.62 WP input equivalent circuit
14/16
Notes on power ON/OFF
At power ON/OFF, set CS "H" (= VCC).
When CS is "L", this IC gets in input accept status (active). If power is turned on in this status, noises and the likes may cause
malfunction, mistake write or so. To prevent these, at power ON, set CS "H". (When CS is in "H" status, all inputs are canceled.)
Vcc
Vcc
GND
Vcc
CS
GND
Bad example
Good example
Fig.63 CS timing at power ON/OFF
(Good example)
(Bad example)
CS terminal is pulled up to VCC.
At power OFF, take 10ms or higher before re supply. If power is turned on without observing this condition, the IC internal
circuit may not be reset, which please note.
CS terminal is "L" at power ON/OFF.
In this case, CS always becomes "L" (active status), and EEPROM may have malfunction, mistake write owing to noises
and the likes.
Even when CS input is High-Z, the status becomes like this case, which please note.
PORcircuit
This IC has a POR (Power On Reset) circuit as mistake write countermeasure. After POR action, it gets in write disable status. The POR
circuit is valid only when power is ON, and does not work when power is OFF. When power is ON, if the recommended conditions of the
following tR, tOFF, and Vbot are not satisfied, it may become write enable status owing to noises and the likes.
tR
VCC
Recommended conditions of tR, tOFF, Vbot
tR
tOFF
tOFF
Vbot
10ms or below 10ms or higher 0.3V or below
Vbot
100ms or below 10ms or higher 0.2V or below
0
Fig.64 Rise waveform
Noise countermeasures
Vcc noise (bypass capacitor)
When noise or surge gets in the power source line, malfunction may occur, therefore, for removing these, it is recommended to attach a
by pass capacitor (0.1µF) between IC Vcc and GND. At that moment, attach it as close to IC as possible.
And, it is also recommended to attach a bypass capacitor between board Vcc and GND.
SCK noise
When the rise time (tR) of SCK is long, and a certain degree or more of noise exists, malfunction may occur owing to clock bit displacement.
To avoid this, a Schmitt trigger circuit is built in SCK input. The hysteresis width of this circuit is set about 0.2V, if noises exist at SCK input,
set the noise amplitude 0.2Vp-p or below. And it is recommended to set the rise time (tR) of SCK 100ns or below. In the case when the rise
time is 100ns or higher, take sufficient noise countermeasures. Make the clock rise, fall time as small as possible.
WP noise
During execution of write status register command, if there exist noises on WP pin, mistake in recognition may occur and forcible cancellation
may result, which please note. To avoid this, a Schmitt trigger circuit is built in WP input. In the same manner, a Schmitt trigger circuit is
built in SI input and HOLD input too.
Cautions on use
(1) Described numeric values and data are design representative values, and the values are not guaranteed.
(2) We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further sufficiently. In the case
of use by changing the fixed number of external parts, make your decision with sufficient margin in consideration of static characteristics
and transition characteristics and fluctuations of external parts and our LSI.
(3) Absolute maximum ratings
If the absolute maximum ratings such as impressed voltage and operating temperature range and so forth are exceeded, LSI may be destructed.
Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case of fear exceeding the absolute maximum
ratings, take physical safety countermeasures such as fuses, and see to it that conditions exceeding the absolute maximum ratings should
not be impressed to LSI.
(4) GND electric potential
Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is lower than that of GND terminal.
(5) Heat design
In consideration of permissible dissipation in actual use condition, carry out heat design with sufficient margin.
(6) Terminal to terminal short circuit and wrong packaging
When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may destruct LSI. And in
the case of short circuit between LSI terminals and terminals and power source, terminal and GND owing to foreign matter, LSI may be
destructed.
(7) Use in a strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently.
15/16
Selection of order type
B R
2 5
L
0 1 0
F
- W
E 2
BUS type Operating temperature Capacity Package type Double cell
25:SPI
010= 1 K F : SOP8
L : −40 〜＋85
020= 2 K FJ : SOP-J8
H : −40 〜＋125
040= 4 K FV : SSOP-B8
080= 8 K FVT :TSSOP-B8
160= 16K FVM : MSOP8
320= 32K FVJ : TSSOP-B8J
640= 64K
Package specifications
Rohm type
name
Package specifications
E2 : reel shape emboss taping
TR : reel shape emboss taping
(MSOP8 package only)
SOP8/SOP-J8/SSOP-B8/TSSOP-B8/TSSOP-B8J
<Package specifications>SOP8/SOP-J8/SSOP-B8/TSSOP-B8/TSSOP-B8J
<External appearance>
+0.05
-0.04
0.45±0.15
0.95±0.2
4.9±0.2
3.0±0.1
0.85±0.05
1.0±0.1
0.65
0.1±0.05
4.4±0.1
0.1±0.05
0.1
1.15±0.1
0.08 S
0.245
4
0.145
+0.05
-0.03
0.08 S
0.32
1234
0.65
1
+0.05
0.145 -0.03
1234
0.1
0.22±0.1
(0.52)
4
E2
(When the reel is gripped by the left hand, and the tape is pulled
out by the right hand, No.1 pin of the product is at the left top.)
1234
0.42±0.1
1
0.15±0.1
2500pcs
Package direction
1234
0.1
1.27
6.4±0.2
4.4±0.2
6.4±0.3
0.45Min.
0.3Min.
4
Emboss taping
Package quantity
1234
1.5±0.1
1
0.2±0.1
3.0±0.1
8 5
Package type
1234
0.1
5
3.0±0.1
8 5
1234
1.27
0.42±0.1
1 2 3 4
+0.1
-0.05
8
• TSSOP-B8J
1234
0.17
3.9±0.2
4
6.0±0.3
1
8 7 6 5
1.375±0.1
0.175
5
6.2±0.3
4.4±0.2
8
• TSSOP-B8
3.0±0.2
4.9±0.2
5.0±0.2
0.11
• SSOP-B8
0.5±0.15
1.0±0.2
• SOP-J8
0.3Min.
• SOP8
+0.05
-0.04
0.65
Pulling side
Pin No.1
Reel
(Unit : mm)
* For ordering, specify a number of multiples of the package quantity.
MSOP8
<Package specifications> MSOP8
<External appearance>
5
1
4
0.29 ± 0.15
0.6 ± 0.2
8
2.8 ± 0.1
4.0 ± 0.2
2.9 ± 0.1
0.9Max.
0.75 ± 0.05
0.08 ± 0.05
0.475
Emboss taping
Package quantity
3000pcs
Package direction
TR
(When the reel is gripped by the left hand, and the tape is pulled
out by the right hand, No.1 pin of the product is at the right top.)
0.145 +0.05
-0.03
0.22 +0.05
-0.04
0.65
Package type
0.08 M
0.08 S
Ｘ
Ｘ
Ｘ
(Unit : mm)
Ｘ
Ｘ
Ｘ
Ｘ
Reel
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Pin No.1
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Pulling side
* For ordering, specify a number of multiples of the package quantity.
Catalog No. 08T565A '08.10 ROHM©
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the
consent of ROHM Co.,Ltd.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing ROHM's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specifications,
which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
information, ROHM shall bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or
implicitly, any license to use or exercise intellectual property or other rights held by ROHM and
other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the
use of such technical information.
The Products specified in this document are intended to be used with general-use electronic
equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices).
The Products specified in this document are not designed to be radiation tolerant.
While ROHM always makes efforts to enhance the quality and reliability of its Products, a
Product may fail or malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard
against the possibility of physical injury, fire or any other damage caused in the event of the
failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM
shall bear no responsibility whatsoever for your use of any Product outside of the prescribed
scope or not in accordance with the instruction manual.
The Products are not designed or manufactured to be used with any equipment, device or
system which requires an extremely high level of reliability the failure or malfunction of which
may result in a direct threat to human life or create a risk of human injury (such as a medical
instrument, transportation equipment, aerospace machinery, nuclear-reactor controller,
fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of
any of the Products for the above special purposes. If a Product is intended to be used for any
such special purpose, please contact a ROHM sales representative before purchasing.
If you intend to export or ship overseas any Product or technology specified herein that may
be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to
obtain a license or permit under the Law.
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More detail product informations and catalogs are available, please contact us.
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http://www.rohm.com/contact/
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© 2009 ROHM Co., Ltd. All rights reserved.
R0039A