W162 Spread Aware™, Zero Delay Buffer Features Table 1. Input Logic • Spread Aware™—designed to work with SSFTG reference signals • Two banks of four outputs, plus the fed back output • Outputs may be three-stated • Available in 16-pin SOIC or SSOP package • Extra strength output drive available (-19 version) • Internal feedback Key Specifications SEL1 SEL0 QA0:3 QB0:3 PLL QFB 0 0 ThreeState ThreeState Shutdown Active 0 1 Active ThreeState Active, Utilized Active 1 0 Active Active Shutdown, Bypassed Active 1 1 Active Active Active, Utilized Active Operating Voltage: ............................................... 3.3V±10% Operating Range: ................................15 < fOUT < 133 MHz Cycle-to-Cycle Jitter: .................................................. 250 ps Output to Output Skew: ............................................. 150 ps Propagation Delay: ..................................................... 150 ps Block Diagram Pin Configuration QFB REF PLL MUX QA0 QA1 QA2 SEL0 QA3 REF 1 16 QFB QA0 2 15 QA3 QA1 3 14 QA2 VDD 4 13 VDD GND 5 12 GND QB0 6 11 QB3 QB1 7 10 QB2 SEL1 8 9 SEL0 QB0 SEL1 QB1 QB2 QB3 Spread Aware is a trademark of Cypress Semiconductor Corporation. Cypress Semiconductor Corporation Document #: 38-07150 Rev. *A • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 14, 02 W162 Pin Definitions Pin No. Pin Type REF 1 I Reference Input: The output signals QA0:3 through QB0:3 will be synchronized to this signal unless the device is programmed to bypass the PLL. QFB 16 O Feedback Output: This signal is used as the feedback internally to establish the propagation delay of nearly 0. QA0:3 2, 3, 14, 15 O Outputs from Bank A: The frequency of the signals provided by these pins is equal to the signal connected to REF. QB0:3 6, 7, 10, 11 O Outputs from Bank B: The frequency of the signals provided by these pins is equal to the signal connected to REF. VDD 4, 13 P Power Connections: Connect to 3.3V. Use ferrite beads to help reduce noise for optimal jitter performance. GND 5, 12 P Ground Connections: Connect all grounds to the common system ground plane. SEL0:1 9, 8 I Function Select Inputs: Tie to VDD (HIGH, 1) or GND (LOW, 0) as desired per Table 1. Pin Name Pin Description Overview The W162 products are nine-output zero delay buffers. A Phase-Locked Loop (PLL) is used to take a time-varying signal and provide eight copies of that same signal out. Internal feedback is used to maximize the number of output signals provided in the 16-pin package. Spread Aware Many systems being designed now utilize a technology called Spread Spectrum Frequency Timing Generation. Cypress has been one of the pioneers of SSFTG development, and we designed this product so as not to filter off the Spread Spectrum feature of the Reference input, assuming it exists. When a zero delay buffer is not designed to pass the SS feature through, the result is a significant amount of tracking skew which may cause problems in systems requiring synchronization. Document #: 38-07150 Rev. *A For more details on Spread Spectrum timing technology, please see the Cypress Application note titled, “EMI Suppression Techniques with Spread Spectrum Frequency Timing Generator (SSFTG) ICs.” Functional Description Logic inputs provide the user the ability to turn off one or both banks of clocks when not in use, as described in Table 1. Disabling a bank of unused outputs will reduce jitter and power consumption, and will also reduce the amount of EMI generated by the W162. These same inputs allow the user to bypass the PLL entirely if so desired. When this is done, the device no longer acts as a zero delay buffer, it simply reverts to a standard nine-output clock driver. Page 2 of 7 W162 Absolute Maximum Ratings[1] Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability . Parameter Description Rating Unit V VDD, VIN Voltage on any pin with respect to GND –0.5 to +7.0 –65 to +150 °C 0 to +70 °C –55 to +125 °C 0.5 W TSTG Storage Temperature TA Operating Temperature TB Ambient Temperature under Bias PD Power Dissipation DC Electrical Characteristics: TA =0°C to 70°C, VDD = 3.3V ±10% Parameter Description Test Condition IDD Supply Current VIL Input Low Voltage VIH Input High Voltage VOL Output Low Voltage IOL = 12 mA (-19) IOL = 8 mA (-9) VOH Output High Voltage IOL = 12 mA (-19) IOL = 8 mA (-9) IIL Input Low Current VIN = 0V IIH Input High Current VIN = VDD Min Typ Max Unit 40 mA 0.8 V Unloaded, 100 MHz 2.0 V 0.4 V 2.4 V –500 µA µA 10 AC Electrical Characteristics: TA = 0°C to +70°C, VDD = 3.3V ±10% Parameter fIN fOUT tR tF Description Test Condition Max Unit 15 133 MHz 15 133 MHz 2.5 ns 1.5 ns 2.5 ns 2.0 to 0.8V, 20-pF load 1.5 ns Input Frequency [6] Output Frequency 15-pF load Output Rise Time (-09) [2] 2.0 to 0.8V, 15-pF load Output Rise Time (-19) [2] 2.0 to 0.8V, 20-pF load [2] Output Fall Time (-09) Output Rise Time (-19)[2] [3, 4] Min Typ 2 2.0 to 0.8V, 15-pF load 2 tPD FBIN to REF Skew Measured at VDD/2 150 ps tSK Output to Output Skew All outputs loaded equally 150 ps 55 % 1.0 ms 250 ps [5] tD Duty Cycle 15-pF load tLOCK PLL Lock Time Power supply stable tJC Jitter, Cycle-to-Cycle 45 50 Notes: 1. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 2. Long input rise and fall time will degrade skew and jitter performance. 3. All AC specifications are measured with a 50Ω transmission line, load terminated with 50Ω to 1.4V. 4. Skew is measured at VDD/2 on rising edges. 5. Duty cycle is measured at VDD/2 6. For the higher drive -19, the load is 20 pF. Document #: 38-07150 Rev. *A Page 3 of 7 W162 Schematic 1 Output Output Output 3 Output Output 14 4 Power Power 13 5 Ground Ground 12 6 Output Output 11 7 Output Output 10 8 Logic In Logic In 9 2 Ferrite Bead VDD 10µ F 0.1µF VDD or GND (for desired operation mode) 16 Ref In 15 Ferrite Bead 0.1µ F10µF VDD VDD or GND (for desired operation mode) Ordering Information Ordering Code W162 Option -09, -19 Document #: 38-07150 Rev. *A Package Name G H Package Type 16-pin Plastic SOIC (150-mil) 16-pin Plastic SSOP (150-mil) Page 4 of 7 W162 Package Diagrams 16-pin SSOP Small Shrunk Outline Package (SSOP, 150-mil) Document #: 38-07150 Rev. *A Page 5 of 7 W162 Package Diagrams (continued) 16-Pin Small Outlined Integrated Circuit (SOIC, 150-mil) Document #: 38-07150 Rev. *A Page 6 of 7 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. W162 Document Title: W162 Spread Aware™. Zero Delay Buffer Document Number: 38-07150 ECN NO. Issue Date Orig. of Change ** 110590 12/19/01 DSG Change from Spec number: 38-00788 to 38-07150 *A 122799 12/14/02 RBI Add Power up Requirements to Operating Conditions Information REV. Document #: 38-07150 Rev. *A Description of Change Page 7 of 7