CYPRESS CY23S02

02
CY23S02
Spread Aware™, Frequency Multiplier and Zero Delay Buffer
Features
Table 1. Configuration Options
• Spread Aware™—designed to work with SSFTG
reference signals
• Two outputs
• Configuration options allow various multiplication of
the reference frequency, refer to Table 1 to determine
the specific option which meets your multiplication
needs
• Available in 8-pin SOIC package
Key Specifications
Operating Voltage: ..........................3.3V ±5% or 5.0V ±10%
Operating Range: ......................20 MHz < fOUT1 < 133 MHz
FBIN
FS0
FS1
OUT1
OUT2
OUT1
0
0
2 X REF
REF
OUT1
1
0
4 X REF
2 X REF
OUT1
0
1
REF
REF/2
OUT1
1
1
8 X REF
4 X REF
OUT2
0
0
4 X REF
2 X REF
OUT2
1
0
8 X REF
4 X REF
OUT2
0
1
2 X REF
REF
OUT2
1
1
16 X REF
8 X REF
Absolute Jitter: ......................................................... ±500 ps
Output to Output Skew: ............................................. 250 ps
Propagation Delay: ................................................... ±350 ps
Propagation delay is affected by input rise time.
Block Diagram
Pin Configuration
External feedback connection to
OUT1 or OUT2, not both
FBIN
FS0
FS1
IN
Reference
Input
÷Q
Phase
Detector
FBIN
1
8
OUT2
IN
2
7
VDD
GND
3
6
OUT1
FS0
4
5
FS1
Charge
Pump
Loop
Filter
Output
Buffer
OUT1
Output
Buffer
OUT2
VCO
÷2
Spread Aware is a trademark of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation
Document #: 38-07155 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised September 25, 2001
CY23S02
Pin Definitions
Pin No.
Pin
Type
IN
2
I
Reference Input: The output signals will be synchronized to this signal.
FBIN
1
I
Feedback Input: This input must be fed by one of the outputs (OUT1 or OUT2) to
ensure proper functionality. If the trace between FBIN and the output pin being used
for feedback is equal in length to the traces between the outputs and the signal destinations, then the signals received at the destinations will be synchronized to the REF
signal input (IN).
OUT1
6
O
Output 1: The frequency of the signal provided by this pin is determined by the feedback signal connected to FBIN, and the FS0:1 inputs (see Table 1).
OUT2
8
O
Output 2: The frequency of the signal provided by this pin is one-half of the frequency
of OUT1. See Table 1.
VDD
7
P
Power Connections: Connect to 3.3V or 5V. This pin should be bypassed with a
0.1-µF decoupling capacitor. Use ferrite beads to help reduce noise for optimal jitter
performance.
GND
3
P
Ground Connection: Connect all grounds to the common system ground plane.
FS0:1
4, 5
I
Function Select Inputs: Tie to VDD (HIGH, 1) or GND (LOW, 0) as desired per
Table 1.
Pin Name
Pin Description
Overview
Spread Aware
The CY23S02 is a two-output zero delay buffer and frequency
multiplier. It provides an external feedback path allowing maximum flexibility when implementing the Zero Delay feature.
This is explained further in the sections of this data sheet titled
“How to Implement Zero Delay,” and “Inserting Other Devices
in Feedback Path.”
Many systems being designed now utilize a technology called
Spread Spectrum Frequency Timing Generation. Cypress has
been one of the pioneers of SSFTG development, and we designed this product so as not to filter off the Spread Spectrum
feature of the Reference input, assuming it exists. When a
zero delay buffer is not designed to pass the SS feature
through, the result is a significant amount of tracking skew
which may cause problems in systems requiring synchronization.
The CY23S02 is a pin-compatible upgrade of the Cypress
W42C70-01. The CY23S02 addresses some application dependent problems experienced by users of the older device.
Most importantly, it addresses the tracking skew problem induced by a reference that has Spread Spectrum Timing enabled on it.
Document #: 38-07155 Rev. **
For more details on Spread Spectrum timing technology,
please see the Cypress application note titled, “EMI Suppression Techniques with Spread Spectrum Frequency Timing
Generator (SSFTG) ICs.”
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CY23S02
CA
Ferrite
Bead
G
V+
10 µF
Power Supply Connection
C8
G
0.01 µF
OUT 2
FBIN
1
7
IN
22Ω
OUTPUT 2
8
VDD
C9 = 0.1 µF
G
2
OUT 1
3
GND
FS0
G
4
22Ω
OUTPUT 1
6
5
FS1
Figure 1. Schematic/Suggested Layout
How to Implement Zero Delay
some other device. This implementation can be applied to any
device (ASIC, multiple output clock buffer/driver, etc.) which is
put into the feedback path.
Typically, zero delay buffers (ZDBs) are used because a designer wants to provide multiple copies of a clock signal in
phase with each other. The whole concept behind ZDBs is that
the signals at the destination chips are all going HIGH at the
same time as the input to the ZDB. In order to achieve this,
layout must compensate for trace length between the ZDB and
the target devices. The method of compensation is described
below.
Referring to Figure 2, if the traces between the ASIC/Buffer
and the destination of the clock signal(s) (A) are equal in length
to the trace between the buffer and the FBIN pin, the signals
at the destination(s) device will be driven HIGH at the same
time the Reference clock provided to the ZDB goes HIGH.
Synchronizing the other outputs of the ZDB to the outputs from
the ASIC/Buffer is more complex however, as any propagation
delay in the ASIC/Buffer must be accounted for.
External feedback is the trait that allows for this compensation.
The PLL on the ZDB will cause the feedback signal to be in
phase with the reference signal. When laying out the board,
match the trace lengths between the output being used for
feed back and the FBIN input to the PLL.
Reference
Signal
Zero
Delay
Buffer
ASIC/
Buffer
If it is desirable to either add a little delay, or slightly precede
the input signal, this may also be affected by either making the
trace to the FBIN pin a little shorter or a little longer than the
traces to the devices being clocked.
Feedback
Input
Inserting Other Devices in Feedback Path
Figure 2. Six Output Buffer in the Feedback Path
A
Another nice feature available due to the external feedback is
the ability to synchronize signals up to the signal coming from
Document #: 38-07155 Rev. **
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CY23S02
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating
only. Operation of the device at these or any other conditions
above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability.
.
Parameter
Description
Rating
Unit
V
VDD, VIN
Voltage on any pin with respect to GND
–0.5 to +7.0
–65 to +150
°C
0 to +70
°C
–55 to +125
°C
0.5
W
TSTG
Storage Temperature
TA
Operating Temperature
TB
Ambient Temperature under Bias
PD
Power Dissipation
DC Electrical Characteristics: TA =0°C to 70°C or –40° to 85°C, VDD = 3.3V ±5%
Parameter
Description
Test Condition
Min.
IDD
Supply Current
Unloaded, 133 MHz
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
IOL = 8 mA
VOH
Output High Voltage
IOH = 8 mA
2.4
IIL
Input Low Current
VIN = 0V
–40
IIH
Input High Current
VIN = VDD
Typ.
Max.
Unit
17
35
mA
0.8
V
2.0
V
0.4
V
V
5
µA
5
µA
Typ.
Max.
Unit
31
50
mA
0.8
V
DC Electrical Characteristics: TA =0°C to 70°C or –40° to 85°C, VDD = 5V ±10%
Parameter
Description
Test Condition
Min.
IDD
Supply Current
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
IOL = 8 mA
VOH
Output High Voltage
IOH = 8 mA
2.4
IIL
Input Low Current
VIN = 0V
-80
IIH
Input High Current
VIN = VDD
Document #: 38-07155 Rev. **
Unloaded, 133 MHz
2.0
V
0.4
V
V
5
µA
5
µA
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CY23S02
AC Electrical Characteristics: TA = 0°C to +70°C or –40° to 85°C, VDD = 3.3V±5%
Parameter
Description
Test Condition
[1]
Min.
Typ.
Max.
Unit
fIN
Input Frequency
OUT2 = REF
10
133
MHz
fOUT
Output Frequency
OUT1
20
133
MHz
tR
Output Rise Time
0.8V to 2.0V, 15-pF load
3.5
ns
tF
Output Fall Time
2.0V to 0.8V, 15-pF load
2.5
ns
10
ns
10
ns
300
ps
60
%
[2]
tICLKR
Input Clock Rise Time
tICLKF
Input Clock Fall Time[2]
[3, 4]
tPD
FBIN to IN (Reference Input) Skew
Note 4
tD
Duty Cycle
Note 5
tLOCK
PLL Lock Time
Power supply stable
1.0
ms
tJC
Jitter, Cycle-to-Cycle
Note 6
250
ps
Max.
Unit
40
50
AC Electrical Characteristics: TA = 0°C to +70°C or –40° to 85°C, VDD = 5V±10%
Parameter
Description
Test Condition
[1]
Min.
Typ.
fIN
Input Frequency
OUT2 = REF
10
133
MHz
fOUT
Output Frequency
OUT1
20
133
MHz
tR
Output Rise Time
0.8V to 2.0V, 15-pF load
3.5
ns
tF
Output Fall Time
2.0V to 0.8V, 15-pF load
2.5
ns
tICLKR
Input Clock Rise Time[2]
10
ns
10
ns
300
ps
60
%
tICLKF
Input Clock Fall Time
[2]
[3, 4]
tPD
FBIN to IN (Reference Input) Skew
Note 4
tD
Duty Cycle
Note 7, 8
tLOCK
PLL Lock Time
Power supply stable
1.0
ms
tJC
Jitter, Cycle-to-Cycle
Note 6
200
ps
40
50
Ordering Information
Ordering Code
Package
Name
Option
CY23S02
-01
S
Package Type
8-pin SOIC (150 mil)
Temperature Grade
C = Commercial (0° to 70°C)
I = Industrial (–40° to 85°C)
Notes:
1. Input frequency is limited by output frequency range and input to output frequency multiplication factor (which is determined by circuit configuration).
2. Longer input rise and fall time will degrade skew and jitter performance.
3. All AC specifications are measured with a 50Ω transmission line, load terminated with 50Ω to 1.4V.
4. Skew is measured at 1.4V on rising edges.
5. Duty cycle is measured at 1.4V.
6. Jitter is measured on 133-MHz signal at 1.4V, low frequency jitter = 350 ps.
7. Duty cycle is measured at 1.4V, 120 MHz.
8. Duty cycle at 133 MHz is 35/65 worst case.
Document #: 38-07155 Rev. **
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CY23S02
Package Diagram
8-Pin Small Outlined Integrated Circuit (SOIC, 150 mil)
Document #: 38-07155 Rev. **
Page 6 of 7
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY23S02
Document Title: CY23S02 Spread Aware™, Frequency Multiplier and Zero Delay Buffer
Document Number: 38-07155
REV.
ECN NO.
Issue
Date
Orig. of
Change
**
110265
12/18/01
SZV
Document #: 38-07155 Rev. **
Description of Change
Change from Spec number: 38-00795 to 38-07155
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