FUJITSU SEMICONDUCTOR FACT SHEET NP501-00014-3v0-E FRAM MB85RC64V MB85RC64V is a 64K-bits FRAM LSI with serial interface (I2C), using the ferroelectric process and CMOS process technologies for forming the nonvolatile memory cells. Because FRAM is able to write high-speed even though a nonvolatile memory, it is suitable for the log management and the storage of the resume data, etc. ■ FEATURES Bit configuration Two-wire serial interface : 8,192 words × 8 bits : Fully controllable by two ports: serial clock (SCL) and serial data (SDA) ：1 MHz (Max) : 1012 times / byte : 10 years (+85℃), 95 years (+55℃), over 200 years (+35 ℃) : 3.0V to 5.5V : Operating power supply current 90 μA (Typ @1 MHz) Standby current 5μA (Typ) Operation ambient temperature range：-40℃ to +85℃ Package ：8-pin plastic SOP (FPT-8P-M02) RoHS compliant Operating frequency Read/write endurance Data retention Operating power supply voltage Low power consumption ■ ORDERING INFORMATION Product name Package Remarks MB85RC64VPNF-G-JNE1 8-pin plastic SOP (FPT-8P-M02) 3.90mm×5.05mm,1.27mm pitch Tube MB85RC64VPNF-G-JNERE1 8-pin plastic SOP (FPT-8P-M02) 3.90mm×5.05mm,1.27mm pitch Embossed Carrier tape ■ PACKAGE EXAMPLE OF REFERENCE 8-pin plastic SOP (FPT-8P-M02) May 2013 1/2 Copyright©2011-2013 FUJITSU SEMICONDUCTOR LIMITED All rights reserved MB85RC64V ■ PIN ASSIGNMENT Pin No. Pin name Description Device Address pins (TOP VIEW) A0 1 8 VDD A1 2 7 WP 1 to 3 A0 to A2 4 VSS 5 SDA 6 SCL 7 WP 8 VDD The MB85RC64V can be connected to the same data bus up to 8 devices. Device addresses are used in order to identify each of these devices. Connect these pins to VDD pin or VSS pin externally. Only if the combination of VDD and VSS pins matches Device Address Code inputted from the SDA pin, the device operates. In the open pin state, A0, A1, and A2 pins are internally pulled-down and recognized as the "L" level. Ground pin Serial Data I/O pin A2 3 6 SCL VSS 4 5 SDA (FPT-8P-M02) This is an I/O pin which performs bidirectional communication for both memory address and writing/reading data. It is possible to connect multiple devices. It is an open drain output, so a pull-up resistor is required to be connected to the external circuit. Serial Clock pin This is a clock input pin for input/output timing serial data. Data is sampled on the rising edge of the clock and output on the falling edge. Write Protect pin When the Write Protect pin is the "H" level, the writing operation is disabled. When the Write Protect pin is the "L" level, the entire memory region can be overwritten. The reading operation is always enabled regardless of the Write Protect pin input level. The Write Protect pin is internally pulled down to the VSS pin and that is recognized as the "L" level (write enabled) when the pin is the open state. Supply Voltage pin ■ BLOCK DIAGRAM Control Circuit SCL WP Row Decoder Serial/Parallel Converter Address Counter SDA FRAM Array 8,192 × 8 Column Decoder/Sense Amp/ Write Amp A0, A1, A2 ■ I2C The MB85RC64V has the two-wire serial interface; the I2C bus,and operates as a slave device. The I2C bus defines communication roles of “master” and “slave” devices, with the master side holding the authority to initiate control. Furthermore, the I2C bus connection is possible where a single master device is connected to multiple slave devices in a party-line configuration. In this case, it is necessary to assign a unique VDD device address to the slave device, the master side starts communication after specifying the slave Pull-up Resistors SCL SDA I2C Bus Master I2C Bus MB85RC64V A2 0 A1 0 A0 0 I2C Bus MB85RC64V A2 0 A1 0 A0 1 I2C Bus MB85RC64V A2 0 A1 1 ... A0 0 Device address NP501-00014-3v0-E May 2013 2/2 Copyright©2011-2013 FUJITSU SEMICONDUCTOR LIMITED All rights reserved