GA50JT12-247 Normally – OFF Silicon Carbide Junction Transistor Features Package RoHS Compliant 175 °C Maximum Operating Temperature Gate Oxide Free SiC Switch Exceptional Safe Operating Area Excellent Gain Linearity Temperature Independent Switching Performance Low Output Capacitance Positive Temperature Coefficient of RDS,ON Suitable for Connecting an Anti-parallel Diode VDS = 1200 V RDS(ON) = 20 mΩ ID (Tc = 25°C) = 100 A ID (Tc > 125°C) = 50 A hFE (Tc = 25°C) = 104 D G D S TO-247 Advantages Applications Compatible with Si MOSFET/IGBT Gate Drive ICs > 20 µs Short-Circuit Withstand Capability Lowest-in-class Conduction Losses High Circuit Efficiency Minimal Input Signal Distortion High Amplifier Bandwidth Down Hole Oil Drilling, Geothermal Instrumentation Hybrid Electric Vehicles (HEV) Solar Inverters Switched-Mode Power Supply (SMPS) Power Factor Correction (PFC) Induction Heating Uninterruptible Power Supply (UPS) Motor Drives Table of Contents Section I: Absolute Maximum Ratings ...........................................................................................................1 Section II: Static Electrical Characteristics ....................................................................................................2 Section III: Dynamic Electrical Characteristics .............................................................................................2 Section IV: Figures ...........................................................................................................................................3 Section V: Driving the GA50JT12-247.............................................................................................................7 Section VI: Package Dimensions ................................................................................................................. 11 Section VII: SPICE Model Parameters ......................................................................................................... 12 Section I: Absolute Maximum Ratings Parameter Drain – Source Voltage Continuous Drain Current Continuous Drain Current Continuous Gate Current Symbol VDS ID ID IG Turn-Off Safe Operating Area RBSOA Short Circuit Safe Operating Area SCSOA Reverse Gate – Source Voltage Reverse Drain – Source Voltage Power Dissipation Storage Temperature VSG VSD Ptot Tstg Jan 2015 Conditions VGS = 0 V TC = 25°C TC = 145°C TVJ = 175 oC, Clamped Inductive Load TVJ = 175 oC, IG = 1 A, VDS = 800 V, Non Repetitive TC = 25 °C / 145 °C, tp > 100 ms Value 1200 100 50 3.5 ID,max = 50 @ VDS ≤ VDSmax Unit V A A A >20 µs 30 25 583 / 116 -55 to 175 V V W °C http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ A Notes Fig. 17 Fig. 17 Fig. 19 Fig. 16 Pg 1 of 11 GA50JT12-247 Section II: Static Electrical Characteristics Parameter Symbol Conditions Min. Value Typical Max. Unit Notes mΩ Fig. 4 V Fig. 7 – Fig. 5 μA Fig. 8 A: On State Drain – Source On Resistance RDS(ON) ID = 50 A, Tj = 25 °C ID = 50 A, Tj = 150 °C ID = 50 A, Tj = 175 °C Gate – Source Saturation Voltage VGS,SAT ID = 50 A, ID/IG = 40, Tj = 25 °C ID = 50 A, ID/IG = 30, Tj = 175 °C hFE VDS = 8 V, ID = 50 A, Tj = 25 °C VDS = 8 V, ID = 50 A, Tj = 125 °C VDS = 8 V, ID = 50 A, Tj = 175 °C Drain Leakage Current IDSS VDS = 1200 V, VGS = 0 V, Tj = 25 °C VDS = 1200 V, VGS = 0 V, Tj = 150 °C VDS = 1200 V, VGS = 0 V, Tj = 175 °C Gate Leakage Current ISG VSG = 20 V, Tj = 25 °C DC Current Gain 20 36 42 3.42 3.23 104 65 58 B: Off State 0.1 0.1 0.2 20 nA C: Thermal Thermal resistance, junction - case 0.26 RthJC °C/W Fig. 20 Unit Notes 7209 124 51 pF pF µJ Fig. 9 Fig. 9 Fig. 10 Section III: Dynamic Electrical Characteristics Parameter Symbol Conditions Min. Value Typical Max. A: Capacitance and Gate Charge Input Capacitance Reverse Transfer/Output Capacitance Output Capacitance Stored Energy Effective Output Capacitance, time related Effective Output Capacitance, energy related Gate-Source Charge Gate-Drain Charge Gate Charge - Total B: Switching VGS = 0 V, VDS = 800 V, f = 1 MHz VDS = 800 V, f = 1 MHz VGS = 0 V, VDS = 800 V, f = 1 MHz Coss,tr ID = constant, VGS = 0 V, VDS = 0…800 V 231 pF Coss,er VGS = 0 V, VDS = 0…800 V 160 pF QGS QGD QG VGS = -5…3 V VGS = 0 V, VDS = 0…800 V 55 184 239 nC nC nC 0.58 Ω 0.09 16 45 33 21 16 45 42 19 1063 357 1420 1032 317 1349 Ω ns ns ns ns ns ns ns ns µJ µJ µJ µJ µJ µJ 1 Internal Gate Resistance – zero bias Internal Gate Resistance – ON Turn On Delay Time Fall Time, VDS Turn Off Delay Time Rise Time, VDS Turn On Delay Time Fall Time, VDS Turn Off Delay Time Rise Time, VDS Turn-On Energy Per Pulse Turn-Off Energy Per Pulse Total Switching Energy Turn-On Energy Per Pulse Turn-Off Energy Per Pulse Total Switching Energy 1 Ciss Crss/Coss EOSS f = 1 MHz, V = 50 mV, V = 0 V, DS RG(INT-ZERO) V = 0 V, T AC GS j = 175 ºC RG(INT-ON) VGS > 2.5 V, VDS = 0 V, Tj = 175 ºC td(on) Tj = 25 ºC, VDS = 800 V, tf ID = 50 A, Inductive Load Refer to Section V for additional td(off) driving information. tr td(on) tf Tj = 175 ºC, VDS = 800 V, ID = 50 A, Inductive Load td(off) tr Eon Tj = 25 ºC, VDS = 800 V, ID = 50 A, Inductive Load Eoff Refer to Section V. Etot Eon Tj = 175 ºC, VDS = 800 V, Eoff ID = 50 A, Inductive Load Etot Fig. 11, 13 Fig. 12, 14 Fig. 11 Fig. 12 Fig. 11, 13 Fig. 12, 14 Fig. 11 Fig. 12 – All times are relative to the Drain-Source Voltage VDS Jan 2015 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 2 of 11 GA50JT12-247 Section IV: Figures A: Static Characteristic Figures Figure 1: Typical Output Characteristics at 25 °C Figure 2: Typical Output Characteristics at 150 °C Figure 3: Typical Output Characteristics at 175 °C Figure 4: On-Resistance vs. Gate Current Figure 5: DC Current Gain and Normalized On-Resistance vs. Temperature Figure 6: DC Current Gain vs. Drain Current Jan 2015 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 3 of 11 GA50JT12-247 Figure 7: Typical Gate – Source Saturation Voltage Figure 8: Typical Blocking Characteristics B: Dynamic Characteristic Figures Figure 9: Input, Output, and Reverse Transfer Capacitance Figure 10: Energy Stored in Output Capacitance Figure 11: Typical Switching Times and Turn On Energy Losses vs. Temperature Figure 12: Typical Switching Times and Turn Off Energy Losses vs. Temperature Jan 2015 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 4 of 11 GA50JT12-247 Figure 13: Typical Switching Times and Turn On Energy Losses vs. Drain Current Figure 14: Typical Switching Times and Turn Off Energy Losses vs. Drain Current C: Device Derating Figures 2 Figure 15: Typical Hard Switched Device Power Loss vs. Switching Frequency 2 Figure 16: Power Derating Curve Figure 17: Drain Current Derating vs. Temperature Figure 18: Forward Bias Safe Operating Area at Tc= 25 oC – Representative values based on device conduction and switching loss. Actual losses will depend on gate drive conditions, device load, and circuit topology. Jan 2015 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 5 of 11 GA50JT12-247 Figure 19: Turn-Off Safe Operating Area Figure 20: Transient Thermal Impedance Figure 21: Drain Current Derating vs. Pulse Width Jan 2015 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 6 of 11 GA50JT12-247 Section V: Driving the GA50JT12-247 Drive Topology TTL Logic Constant Current High Speed – Boost Capacitor High Speed – Boost Inductor Proportional Pulsed Power Gate Drive Power Consumption High Medium Medium Low Lowest Medium Switching Frequency Low Medium High High High N/A Application Emphasis Availability Wide Temperature Range Wide Temperature Range Fast Switching Ultra Fast Switching Wide Drain Current Range Pulse Power Coming Soon Coming Soon Production Coming Soon Coming Soon Coming Soon A: Static TTL Logic Driving The GA50JT12-247 may be driven using direct (5 V) TTL logic after current amplification. The (amplified) current level of the supply must meet or exceed the steady state gate current (I G,steady) required to operate the GA50JT12-247. The power level of the supply can be estimated from the target duty cycle of the particular application. IG,steady is dependent on the anticipated drain current ID through the SJT and the DC current gain hFE, it may be calculated from the following equation. An accurate value of the hFE may be read from Figure 6. 5V SiC SJT TTL Gate Signal D G 5/0V TTL i/p IG,steady S Figure 22: TTL Gate Drive Schematic B: High Speed Driving The SJT is a current controlled transistor which requires a positive gate current for turn-on as well as to remain in on-state. An ideal gate current waveform for ultra-fast switching of the SJT, while maintaining low gate drive losses, is shown in Figure 23 which features a positive current peak during turn-on, a negative current peak during turn-off, and continuous gate current to remain on. Figure 23: An idealized gate current waveform for fast switching of an SJT. An SJT is rapidly switched from its blocking state to on-state, when the necessary gate charge, QG, for turn-on is supplied by a burst of high gate current, IG,on, until the gate-source capacitance, CGS, and gate-drain capacitance, CGD, are fully charged. Jan 2015 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 7 of 11 GA50JT12-247 Ideally, IG,on should terminate when the drain voltage falls to its on-state value in order to avoid unnecessary drive losses during the steady onstate. In practice, the rise time of the I G,on pulse is affected by the parasitic inductances, Lpar in the device package and drive circuit. A voltage developed across the parasitic inductance in the source path, L s, can de-bias the gate-source junction, when high drain currents begin to flow through the device. The voltage applied to the gate pin should be maintained high enough, above the V GS,sat (see Figure 7) level to counter these effects. A high negative peak current, -IG,off is recommended at the start of the turn-off transition, in order to rapidly sweep out the injected carriers from the gate, and achieve rapid turn-off. While satisfactory turn off can be achieved with V GS = 0 V, a negative gate voltage VGS may be used in order to speed up the turn-off transition. Two high-speed drive topologies for the SiC SJTs are presented below. B:1: High Speed, Low Loss Drive with Boost Capacitor, GA03IDDJT30-FR4 The GA50JT12-247 may be driven using a High Speed, Low Loss Drive with Boost Capacitor topology in which multiple voltage levels, a gate resistor, and a gate capacitor are used to provide fast switching current peaks at turn-on and turn-off and a continuous gate current while in on-state. A 3 kV isolated evaluation gate drive board (GA03IDDJT30-FR4) utilizing this topology is commercially available for high and lowside driving, its datasheet provides additional details about this drive topology. C2 +12 V GA03IDDJT30-FR4 Gate Driver Board VGL VCC High U3 C5 VCC High RTN CG1 VGL VGH Signal R1 R2 U1 CG2 U5 R4 C9 VEE C6 Gate Signal VEE C10 VGL R3 U2 VEE VCC Low RTN G SiC SJT RG2 S C8 VGH VCC Low C1 VEE IG RG1 U6 D1 Signal RTN +12 V D Gate VGL U4 C3 C4 Source VEE Voltage Isolation Barrier Figure 24: Topology of the GA03IDDJT30-FR4 Two Voltage Source gate driver. The GA03IDDJT30-FR4 evaluation board comes equipped with two on board gate drive resistors (RG1, RG2) pre-installed for an effective gate resistance3 of RG = 3.75 Ω. It may be necessary for the user to reduce RG1 and RG2 under high drain current conditions for safe operation of the GA50JT12-247. The steady state current supplied to the gate pin of the GA50JT12-247 with on-board RG = 3.75 Ω, is shown in Figure 25. The maximum allowable safe value of RG for the user’s required drain current can be read from Figure 26. For the GA50JT12-247, RG must be reduced for ID ≥ ~14 A for safe operation with the GA03IDDJT30-FR4. For operation at ID ≥ ~14 A, RG may be calculated from the following equation, which contains the DC current gain hFE (Figure 6) and the gatesource saturation voltage VGS,sat (Figure 7). Jan 2015 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 8 of 11 GA50JT12-247 Figure 25: Typical steady state gate current supplied by the GA03IDDJT30-FR4 board for the GA50JT12-247 with the on board resistance of 3.75 Ω Figure 26: Maximum gate resistance for safe operation of the GA50JT12-247 at different drain currents using the GA03IDDJT30-FR4 board. B:2: High Speed, Low Loss Drive with Boost Inductor A High Speed, Low-Loss Driver with Boost Inductor is also capable of driving the GA50JT12-247 at high-speed. It utilizes a gate drive inductor instead of a capacitor to provide the high-current gate current pulses IG,on and IG,off. During operation, inductor L is charged to a specified I G,on current value then made to discharge IL into the SJT gate pin using logic control of S1, S2, S3, and S4, as shown in Figure 27. After turn on, while the device remains on the necessary steady state gate current IG,steady is supplied from source VCC through RG. Please refer to the article “A current-source concept for fast and efficient driving of silicon carbide transistors” by Dr. Jacek Rąbkowski for additional information on this driving topology.4 VCC S1 VCC S2 L VEE S3 SiC SJT D G RG S4 S VEE Figure 27: Simplified Inductive Pulsed Drive Topology 3 – RG = (1/RG1 +1/RG2)-1. Driver is pre-installed with RG1 = RG2 = 7.5 Ω 4 – Archives of Electrical Engineering. Volume 62, Issue 2, Pages 333–343, ISSN (Print) 0004-0746, DOI: 10.2478/aee-2013-0026, June 2013 Jan 2015 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 9 of 11 GA50JT12-247 C: Proportional Gate Current Driving For applications in which the GA50JT12-247 will operate over a wide range of drain current conditions, it may be beneficial to drive the device using a proportional gate drive topology to optimize gate drive power consumption. A proportional gate driver relies on instantaneous drain current ID feedback to vary the steady state gate current IG,steady supplied to the GA50JT12-247 C:1: Voltage Controlled Proportional Driver The voltage controlled proportional driver relies on a gate drive IC to detect the GA50JT12-247 drain-source voltage VDS during on-state to sense ID. The gate drive IC will then increase or decrease IG,steady in response to ID. This allows IG,steady, and thus the gate drive power consumption, to be reduced while ID is relatively low or for IG,steady to increase when is ID higher. A high voltage diode connected between the drain and sense protects the IC from high-voltage when the driver and GA50JT12-247 are in off-state. A simplified version of this topology is shown in Figure 29, additional information will be available in the future at http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ HV Diode Sense Gate Signal Proportional Gate Current Driver Signal D G Output IG,steady SiC SJT S Figure 28: Simplified Voltage Controlled Proportional Driver C:2: Current Controlled Proportional Driver The current controlled proportional driver relies on a low-loss transformer in the drain or source path to provide feedback ID of the GA50JT12247 during on-state to supply IG,steady into the device gate. IG,steady will then increase or decrease in response to ID at a fixed forced current gain which is set be the turns ratio of the transformer, hforce = ID / IG = N2 / N1. GA50JT12-247 is initially tuned-on using a gate current pulse supplied into an RC drive circuit to allow ID current to begin flowing. This topology allows IG,steady, and thus the gate drive power consumption, to be reduced while ID is relatively low or for IG,steady to increase when is ID higher. A simplified version of this topology is shown in Figure 29, additional information will be available in the future at http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/. N2 SiC SJT Gate Signal D G S N3 N1 N2 Figure 29: Simplified Current Controlled Proportional Driver Jan 2015 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 10 of 11 GA50JT12-247 Section VI: Package Dimensions TO-247 (4.318 REF.) 0.170 REF. (5.486) 0.216 PACKAGE OUTLINE (15.748) (16.256) 0.620 0.640 0.55 (13.97) 0.236 (5.99) 0.171 (4.699) 0.208 (5.283) 0.045 (1.14) 0.054 (1.36) 0.059 (1.498) 0.098 (2.489) 0.22 (5.59) 0.242 BSC. (6.147 BSC.) 0.819 0.844 (20.803) (21.438) 0.012 (0.3) 0.652 (16.56) Ø 0.140 (3.556) 0.143 (3.632) Ø 0.118 (3.00) Ø 0.283 (7.19) GA50JT12-247 XXXXXX Lot code 0.780 0.800 (19.812) (20.320) 0.177 MAX (4.496) 0.065 (1.651) 0.083 (2.108) 0.040 (1.016) 0.055 (1.397) 0.2146 (5.451) BSC. 0.016 (0.406) 0.031 (0.787) 0.075 (1.905) 0.115 (2.921) NOTE 1. CONTROLLED DIMENSION IS INCH. DIMENSION IN BRACKET IS MILLIMETER. 2. DIMENSIONS DO NOT INCLUDE END FLASH, MOLD FLASH, MATERIAL PROTRUSIONS Revision History Date Revision Comments 2015/01/29 2014/12/18 3 2 Updated Electrical Characteristics Updated Electrical Characteristics 2014/11/12 2014/08/25 1 0 Updated Electrical Characteristics Initial release Supersedes Published by GeneSiC Semiconductor, Inc. 43670 Trade Center Place Suite 155 Dulles, VA 20166 GeneSiC Semiconductor, Inc. reserves right to make changes to the product specifications and data in this document without notice. GeneSiC disclaims all and any warranty and liability arising out of use or application of any product. No license, express or implied to any intellectual property rights is granted by this document. Unless otherwise expressly indicated, GeneSiC products are not designed, tested or authorized for use in life-saving, medical, aircraft navigation, communication, air traffic control and weapons systems, nor in applications where their failure may result in death, personal injury and/or property damage. Jan 2015 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 11 of 11 GA50JT12-247 Section VII: SPICE Model Parameters This is a secure document. Please copy this code from the SPICE model PDF file on our website (http://www.genesicsemi.com/images/products_sic/sjt/GA50JT12-247_SPICE.pdf) into LTSPICE (version 4) software for simulation of the GA50JT12-247. * MODEL OF GeneSiC Semiconductor Inc. * * $Revision: 2.2 $ * $Date: 29-JAN-2015 $ * * GeneSiC Semiconductor Inc. * 43670 Trade Center Place Ste. 155 * Dulles, VA 20166 * * COPYRIGHT (C) 2015 GeneSiC Semiconductor Inc. * ALL RIGHTS RESERVED * * These models are provided "AS IS, WHERE IS, AND WITH NO WARRANTY * OF ANY KIND EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED * TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * PARTICULAR PURPOSE." * Models accurate up to 2 times rated drain current. * .model GA50JT12 NPN + IS 9.833E-48 + ISE 1.073E-26 + EG 3.23 + BF 110 + BR 0.55 + IKF 9000 + NF 1 + NE 2 + RB 0.95 + IRB 0.005 + RBM 0.073 + RE 0.005 + RC 0.014 + CJC 2.398E-9 + VJC 2.8346 + MJC 0.4846 + CJE 6.026E-09 + VJE 3.1791 + MJE 0.5295 + XTI 3 + XTB -1.5 + TRC1 9.00E-3 + VCEO 1200 + ICRATING 50 + MFG GeneSiC_Semiconductor * * End of GA50JT12 SPICE Model Jan 2015 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 1 of 1