データシート

[AK4621]
AK4621
24-Bit 192kHz Stereo Audio CODEC
AK4621
192kHz
24bit CODEC
DAC
AK4621
ADC
(SCF)
,
□ 24-bit 2-channel ADC
- Full Differential Inputs
- Selectable Digital Filters
1. ADC Sharp Roll Off Filter (GD=39/fs)
Passband: 0 ~ 21.8kHz (@fs=48kHz)
Stopband Attenuation: 100dB
2. ADC Short Delay Sharp Roll Off Filter (GD=14/fs)
Passband: 0 ~ 21.7kHz (@fs=48kHz)
Stopband Attenuation: 80dB
- S/(N+D): 102dB
- S/N: 115dB
- Digital High-pass Filter for Offset Cancellation
- Overflow Flag
2
- Audio Interface Format: MSB justified or I S
□ 24-bit 2-channel DAC
- Selectable Digital Filters
1. DAC Sharp Roll Off Filter (GD=27/fs)
Passband: 0 ~ 21.8kHz (@fs=48kHz)
Stopband Attenuation: 70dB
2. DAC Slow Roll Off Filter (GD=27/fs)
Passband: 0 ~ 8.9kHz (@fs=48kHz)
Stopband Attenuation: 73dB
3. DAC Short Delay Sharp Roll Off Filter (GD=7/fs)
Passband: 0 ~ 21.8kHz (@fs=48kHz)
Stopband Attenuation: 70dB
- Switched-cap Low Pass Filter
- Differential Outputs
- S/(N+D): 100dB
- S/N: 115dB
- De-emphasis for 32kHz, 44.1kHz, 48kHz Sampling
- Output Digital Attenuator: 0dB ~ – 72dB, Linear 256 + 16steps
- Zero Detection Function
2
- Audio Interface Format: MSB justified, LSB justified, I S
□ High Jitter Tolerance
□ Sampling Rate: 32kHz ~ 216kHz
□ μP Interface: 3-wire Serial Interface
□ Master Clock: 128fs/192fs/256fs/384fs/512fs/768fs/1024fs
MS1258-J-01
2011/01
-1-
[AK4621]
□ Power Supply
Analog: 4.75 ~ 5.25V (typ. 5.0V)
Digital: 3.0 ~ 3.6V (typ. 3.3V)
Digital I/O: DVDD ~ 5.25V (typ. 5.0V)
□ Package: 30pin VSOP
□ Ta: -10 ~ 70 °C
■
AVDD VSS1 VCOM VREF
DVDD TVDD VSS2
AINL+
AINLADC
PDN
HPF
AINR+
LRCK
AINR-
BICK
OVFL/DZFL
OVF
Audio
Interface
SDTO
SDTI
OVFR/DZFR
MCLK
AOUTL+
DATT
SMUTE
AOUTL-
DFS0
DAC
AOUTR+
AOUTR-
Control
Register I/F
P/S
SDFIL DEM0 CSN/ CCLK/ CDTI/
DIF CKS1 CKS0
Figure 1. Block Diagram
MS1258-J-01
2011/01
-2-
[AK4621]
■
AK4621EF
AKD4621
−10 ∼ +70°C
AK4621
30pin VSOP 0.65mm pitch
■
VCOM
1
30
AOUTR+
AINR+
2
29
AOUTR-
AINR-
3
28
AOUTL+
AINL+
4
27
AOUTL-
AINL-
5
26
VSS2
VREF
6
25
DVDD
VSS1
7
24
TVDD
AVDD
8
23
SDFIL
P/S
9
22
DEM0
MCLK
10
21
PDN
LRCK
11
20
DFS0
BICK
12
19
CSN/DIF
SDTO
13
18
CCLK/CKS1
SDTI
14
17
CDTI/CKS0
OVFR/DZFR
15
16
OVFL/DZFL
Top View
MS1258-J-01
2011/01
-3-
[AK4621]
■ AK4620B
1. Function
Function
Max fs
ADC Inputs
Input analog PGA
Input digital ATT
ADC S/(N+D)
ADC DR, S/N
AK4620B
AK4621
216kHz
Differential
←
Differential
-
-
Single-ended
0 ~ +18dB
0.5dB/step
Mute,-63.5dB ~ 0dB
0.5dB/step
90dB
110dB
Mute,-63.5dB ~ 0dB
0.5dB/step
100dB
113dB
ADC Digital Filter Type
Sharp Roll-off
ADC Digital Filter SA
ADC Digital Filter GD
DAC S/(N+D)
DAC DR, S/N
100dB
43.2/fs
97dB (0dBFS)
115dB
102dB
115dB
Sharp Roll-off
100dB
39/fs
100dB (-1dBFS)
←
DAC Digital Filter Type
Sharp Roll-off
Slow Roll-off
Sharp Roll-off
DAC Digital Filter SA
DAC Digital Filter GD
75dB
28/fs
Mute, -48dB ~ 0dB
Linear 256 steps
72dB
28/fs
Mute, -48dB ~ 0dB
Linear 256 steps
70dB
27/fs
Output digital Attenuator
DAC DSD mode
DAC Zero-data detection
Parallel Mode
X
X
X
Short Delay
Sharp Roll-off
80dB
14/fs
Slow Roll-off
73dB
27/fs
Mute, -72dB ~ 0dB
Linear 16 + 256 steps
←
←
Short Delay
Sharp Roll-off
70dB
7/fs
X: Available, -: Not Available
2.
(AK4620B
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
Register Name
Power Down Control
Reset Control
Clock and Format Control
Deem and Volume Control
Reserved
Reserved
Lch DATT Control
Rch DATT Control
Lch Extension DATT Control
Rch Extension DATT Control
)
D7
SLOW
D/P
DIF2
SMUTE
IATTL7
IATTR7
DATTL7
DATTR7
0
0
D6
DZFB
DCKS
DIF1
HPRN
IATTL6
IATTR6
DATTL6
DATTR6
0
0
D5
ZOE
DCKB
DIF0
HPLN
IATTL5
IATTR5
DATTL5
DATTR5
EXTE
0
D4
ZOS
SDAD
CMODE
ZCEI
IATTL4
IATTR4
DATTL4
DATTR4
0
0
D3
SDDA
AML
CKS1
ZTM1
IATTL3
IATTR3
DATTL3
DATTR3
EATTL3
EATTR3
D2
PWVR
AMR
CKS0
ZTM0
IATTL2
IATTR2
DATTL2
DATTR2
EATTL2
EATTR2
D1
PWAD
RSTAD
DFS1
DEM1
IATTL1
IATTR1
DATTL1
DATTR1
EATTL1
EATTR1
D0
PWDA
RSTDA
DFS0
DEM0
IATTL0
IATTR0
DATTL0
DATTR0
EATTL0
EATTR0
AK4621
AK4621
MS1258-J-01
2011/01
-4-
[AK4621]
No.
Pin Name
I/O
1
VCOM
O
2
3
4
5
AINR+
AINRAINL+
AINL-
I
I
I
I
6
VREF
I
7
8
VSS1
AVDD
-
9
P/S
I
10
11
12
13
14
MCLK
LRCK
BICK
SDTO
SDTI
OVFR
DZFR
OVFL
DZFL
CDTI
CKS0
CCLK
CKS1
CSN
I
I
I
O
I
O
O
O
O
I
I
I
I
I
DIF
I
20
DFS0
I
21
PDN
I
22
DEM0
I
23
SDFIL
I
15
16
17
18
19
24 TVDD
25 DVDD
26 VSS2
27 AOUTLO
28 AOUTL+
O
29 AOUTRO
30 AOUTR+
O
Note 1.
DEM0 and SDFIL)
Function
Common Voltage Output Pin, (AVDD)/2
Bias voltage of ADC inputs and DAC outputs.
Rch Positive Input Pin
Rch Negative Input Pin
Lch Positive Input Pin
Lch Negative Input Pin
Voltage Reference Input Pin, AVDD
Used as a voltage reference by ADC & DAC. VREF is connected externally to filtered
AVDD.
Analog Ground Pin
Analog Power Supply Pin, 4.75 ∼ 5.25V
Parallel/Serial Mode Select Pin
“L”: Serial Mode, “H”: Parallel Mode
Do not change this pin during PDN pin = “H”.
Master Clock Input Pin
Input/Output Channel Clock Pin
Audio Serial Data Clock Pin
Audio Serial Data Output Pin
Audio Serial Data Input Pin
Rch Over Flow Flag Pin (in Parallel mode or when ZOS bit=“0” in Serial Mode)
Rch Zero Detection Flag Pin (when ZOS bit=“1” in Serial Mode)
Lch Over Flow Flag Pin (in Parallel mode or when ZOS bit=“0” in Serial Mode)
Lch Zero Detection Flag Pin (when ZOS bit=“1” in Serial Mode)
Control Data Input Pin (in Serial Mode)
Master Clock Select Pin (in Parallel Mode)
Control Data Clock Pin (in Serial Mode)
Master Clock Select Pin (in Parallel Mode)
Chip Select Pin in Serial Mode (in Serial Mode)
Digital Audio Interface Select Pin (in Parallel Mode)
“L”: 24bit MSB justified, “H”: I2S compatible
Double Speed Sampling Mode Pin
Power-Down Mode Pin
“L”: Power down reset and initialize the control register, “H”: Power up
De-emphasis Control Pin
Digital Filter Select Pin
“L”: Short Delay Sharp Roll Off Filter (ADC), Short Delay Sharp Roll Off Filter (DAC)
“H”: Sharp Roll Off Filter (ADC), Sharp Roll Off Filter (DAC)
Digital I/O Power Supply Pin, DVDD ∼ 5.25V
Digital Power Supply Pin, 3.0 ∼ 3.6V
Digital Ground Pin
Lch Negative Analog Output Pin
Lch Positive Analog Output Pin
Rch Negative Analog Output Pin
Rch Positive Analog Output Pin
(P/S, MCLK, LRCK, BICK, SDTI, CDTI/CKS0, CCLK/CKS1, CSN/DIF, DFS0, PDN,
MS1258-J-01
2011/01
-5-
[AK4621]
■
Analog Input
Analog Output
Digital Output
AINL+, AINLAINR+, AINRAOUTL+, AOUTL-, AOUTR+, AOUTROVFL/DZFL, OVFR/DZFR
AINL+ pin
AINR+ pin
AINL- pin
AINR- pin
(VSS1=VSS2=0V; Note 2, Note 3)
Parameter
Symbol
min
max
Units
Power Supplies:
Analog
AVDD
-0.3
6.0
V
Digital
DVDD
-0.3
6.0
V
Digital I/O
TVDD
-0.3
6.0
V
Input Current, Any Pin Except Supplies
IIN
mA
±10
Analog Input Voltage
(Note 4)
VINA
-0.3
AVDD+0.3
V
Digital Input Voltage
(Note 5)
VIND
-0.3
TVDD+0.3
V
Ambient Temperature (powered applied)
Ta
-10
70
°C
Storage Temperature
Tstg
-65
150
°C
Note 2.
Note 3. VSS1
VSS2
Note 4. AINL+, AINL-, AINR+ and AINR- pins
Note 5. P/S, MCLK, LRCK, BICK, SDTI, CDTI/CKS0, CCLK/CKS1, CSN/DIF, DFS0, PDN, DEM0 and SDFIL pins.
:
VSS1=VSS2=0V; Note 2
Parameter
Power Supplies
Analog
(Note 6) Digital
Digital I/O
Voltage Reference
Note 6: AVDD, DVDD, TVDD
Symbol
AVDD
DVDD
TVDD
VREF
min
4.75
3.0
DVDD
3.0
typ
5.0
3.3
5.0
-
max
5.25
3.6
5.25
AVDD
Units
V
V
V
V
:
MS1258-J-01
2011/01
-6-
[AK4621]
(Ta=25°C; AVDD=5V, DVDD=3.3V, TVDD=5V; VSS1=VSS2=0V; VREF=AVDD; fs=48kHz; Signal Frequency
=1kHz; 24bit Data; Measurement frequency=20Hz ∼ 20kHz; unless otherwise specified)
Parameter
min
typ
max
Units
ADC Analog Input Characteristics:
Resolution
24
Bits
Input Voltage
(Note 7)
Vpp
±2.62
±2.82
±3.02
Input Resistance
fs=48kHz
13
kΩ
fs=96kHz
13
kΩ
fs=192kHz
13
kΩ
S/(N+D)
fs=48kHz
-1dBFS
92
102
dB
BW=20kHz
-60dBFS
52
dB
fs=96kHz
-1dBFS
101
dB
BW=40kHz
-60dBFS
48
dB
fs=192kHz
-1dBFS
101
dB
BW=40kHz
-60dBFS
48
dB
Dynamic Range
(-60dBFS with A-weighted)
115
dB
S/N
(A-weighted)
105
115
dB
Interchannel Isolation
90
110
dB
Interchannel Gain Mismatch
0
0.3
dB
Gain Drift
(Note 12)
20
ppm/°C
Power Supply Rejection
(Note 8)
50
dB
DAC Analog Output Characteristics:
Parameter
min
typ
max
Units
Resolution
24
Bits
Dynamic Characteristics
S/(N+D)
fs=48kHz
−1dBFS
90
100
dB
BW=20kHz
52
dB
−60dBFS
fs=96kHz
−1dBFS
97
dB
BW=40kHz
49
dB
−60dBFS
fs=192kHz
−1dBFS
97
dB
BW=40kHz
49
dB
−60dBFS
115
dB
Dynamic Range (−60dBFS with A-weighted) (Note 9, Note 10)
S/N
(A-weighted) (Note 10, Note 11)
107
115
dB
Interchannel Isolation (1kHz)
90
110
dB
DC Accuracy
Interchannel Gain Mismatch
0
0.3
dB
Gain Drift
(Note 12)
20
ppm/°C
Output Voltage
(Note 13)
Vpp
±2.6
±2.8
±3.0
Load Capacitance
25
pF
Load Resistance
(Note 14)
2
kΩ
Note 7.
(0dB). Vin (typ) = ±2.82Vpp x VREF/5.
Note 8. VREF pin
AVDD, DVDD, TVDD 1kHz, 50mVpp
Note 9. 100dB at 16bit data and 114dB at 20bit data.
Note 10. Figure 20. External LPF Circuit Example 2
Note 11. S/N
bit
Note 12. VREF
+5V
Note 13.
VREF
AOUT (typ.@0dB) = (AOUT+) - (AOUT-) = 5.6Vpp x VREF/5.
Note 14. AC
MS1258-J-01
2011/01
-7-
[AK4621]
Parameter
Power Supplies
Power Supply Current
Normal Operation (PDN pin = “H”)
AVDD
DVDD+TVDD (fs=48kHz)
(fs=96kHz)
(fs=192kHz)
Power-down mode (PDN pin = “L”)
AVDD
DVDD+TVDD
Note 15.
min
typ
max
Units
-
34
11
20
27
51
30
41
mA
mA
mA
mA
10
10
100
100
μA
μA
(Note 15)
TVDD or VSS2
MS1258-J-01
2011/01
-8-
[AK4621]
ADC
(fs=48kHz)
(Ta=25°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 3.6V, TVDD=DVDD ∼ 5.25V; Normal Speed Mode; SDAD bit = “0”)
Parameter
Symbol
min
typ
max
Units
ADC Digital Filter (Decimation LPF):
PB
Passband
(Note 16) −0.005dB
0
21.8
kHz
−0.02dB
22.0
kHz
22.3
kHz
−0.06dB
24.0
kHz
−6.0dB
Stopband
(Note 16)
SB
26.5
kHz
Passband Ripple
PR
dB
±0.005
Stopband Attenuation
SA
100
dB
Group Delay
(Note 17)
GD
39
1/fs
Group Delay Distortion
0
ΔGD
μs
ADC Digital Filter (HPF):
Frequency Response (Note 16) −3dB
FR
1.0
Hz
6.5
Hz
−0.1dB
ADC
(fs=96kHz)
(Ta=25°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 3.6V, TVDD=DVDD ∼ 5.25V; Double Speed Mode; SDAD bit = “0”)
Parameter
Symbol
min
typ
max
Units
ADC Digital Filter (Decimation LPF):
PB
Passband
(Note 16) −0.005dB
0
43.7
kHz
−0.02dB
44.1
kHz
44.5
kHz
−0.06dB
48.0
kHz
−6.0dB
Stopband
(Note 16)
SB
53.0
kHz
Passband Ripple
PR
dB
±0.005
Stopband Attenuation
SA
100
dB
Group Delay
(Note 17)
GD
39
1/fs
Group Delay Distortion
0
ΔGD
μs
ADC Digital Filter (HPF):
Frequency Response (Note 16) −3dB
FR
2.0
Hz
13.0
Hz
−0.1dB
MS1258-J-01
2011/01
-9-
[AK4621]
ADC
(fs=192kHz)
(Ta=25°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 3.6V, TVDD=DVDD ∼ 5.25V; Quad Speed Mode; SDAD bit = “0”)
Parameter
Symbol
min
typ
max
Units
ADC Digital Filter (Decimation LPF):
PB
Passband
(Note 16) −0.005dB
0
87.0
kHz
−0.02dB
88.2
kHz
89.0
kHz
−0.06dB
96.0
kHz
−6.0dB
Stopband
(Note 16)
SB
106.0
kHz
Passband Ripple
PR
dB
±0.01
Stopband Attenuation
SA
100
dB
Group Delay
(Note 17)
GD
36
1/fs
Group Delay Distortion
0
ΔGD
μs
ADC Digital Filter (HPF):
Frequency Response (Note 16) −3dB
FR
4.0
Hz
26.0
Hz
−0.1dB
Note 16:
fs(
)
1kHz
Note 17:
ADC
24bit
SDTO pin
0.5/fs
MS1258-J-01
2011/01
- 10 -
[AK4621]
ADC
(fs=48kHz)
(Ta=25°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 3.6V, TVDD=DVDD ∼ 5.25V; Normal Speed Mode; SDAD bit = “1”)
Parameter
Symbol
min
typ
max
Units
ADC Digital Filter (Decimation LPF):
PB
Passband
(Note 16) −0.01dB
0
21.7
kHz
−0.1dB
22.1
kHz
23.8
kHz
−3.0dB
24.4
kHz
−6.0dB
Stopband
(Note 16)
SB
28.2
kHz
Passband Ripple
PR
dB
±0.01
Stopband Attenuation
SA
80
dB
Group Delay
(Note 17)
GD
14
1/fs
Group Delay Distortion
±0.01
ΔGD
μs
ADC Digital Filter (HPF):
Frequency Response (Note 16) −3dB
FR
1.0
Hz
6.5
Hz
−0.1dB
ADC
(fs=96kHz)
(Ta=25°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 3.6V, TVDD=DVDD ∼ 5.25V; Double Speed Mode; SDAD bit = “1”)
Parameter
Symbol
min
typ
max
Units
ADC Digital Filter (Decimation LPF):
PB
Passband
(Note 16) −0.01dB
0
43.3
kHz
−0.1dB
44.2
kHz
47.6
kHz
−3.0dB
48.9
kHz
−6.0dB
Stopband
(Note 16)
SB
55.9
kHz
Passband Ripple
PR
dB
±0.01
Stopband Attenuation
SA
80
dB
Group Delay
(Note 17)
GD
14
1/fs
Group Delay Distortion
±0.013
ΔGD
μs
ADC Digital Filter (HPF):
Frequency Response (Note 16) −3dB
FR
2.0
Hz
13.0
Hz
−0.1dB
ADC
(fs=192kHz)
(Ta=25°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 3.6V, TVDD=DVDD ∼ 5.25V; Quad Speed Mode; SDAD bit = “1”)
Parameter
Symbol
min
typ
max
Units
ADC Digital Filter (Decimation LPF):
PB
Passband
(Note 16) −0.01dB
0
76.1
kHz
−0.1dB
81.1
kHz
99.9
kHz
−3.0dB
106.7
kHz
−6.0dB
Stopband
(Note 16)
SB
141.1
kHz
Passband Ripple
PR
dB
±0.01
Stopband Attenuation
SA
79
dB
Group Delay
(Note 17)
GD
11
1/fs
Group Delay Distortion
0
ΔGD
μs
ADC Digital Filter (HPF):
Frequency Response (Note 16) −3dB
FR
4.0
Hz
26.0
Hz
−0.1dB
MS1258-J-01
2011/01
- 11 -
[AK4621]
DAC
(fs = 48kHz)
(Ta = 25°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 3.6V, TVDD=DVDD ∼ 5.25V; Normal Speed Mode; DEM = OFF;
SLOW bit = “0”, SDDA bit = “0”)
Parameter
Symbol
min
typ
max
Units
Digital Filter
Passband
(Note 18) -0.04dB
PB
0
21.8
kHz
-6.0dB
24.0
kHz
Stopband
(Note 18)
SB
26.2
kHz
Passband Ripple
PR
±0.06
dB
Stopband Attenuation
SA
70
dB
Group Delay
(Note 19)
GD
27
1/fs
Digital Filter + SCF
dB
Frequency Response: 0 ∼ 20.0kHz
± 0.2
DAC
(fs = 96kHz)
(Ta = 25°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 3.6V, TVDD=DVDD ∼ 5.25V; Double Speed Mode; DEM = OFF;
SLOW bit = “0”, SDDA bit = “0”)
Parameter
Symbol
min
typ
max
Units
Digital Filter
Passband
(Note 18) -0.03dB
PB
0
43.5
kHz
-6.0dB
48.0
kHz
Stopband
(Note 18)
SB
52.4
kHz
Passband Ripple
PR
±0.06
dB
Stopband Attenuation
SA
70
dB
Group Delay
(Note 19)
GD
27
1/fs
Digital Filter + SCF
dB
Frequency Response: 0 ∼ 40.0kHz
± 0.3
DAC
(fs = 192kHz)
(Ta = 25°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 3.6V, TVDD=DVDD ∼ 5.25V; Quad Speed Mode; DEM = OFF;
SLOW bit = “0”, SDDA bit = “0”)
Parameter
symbol
min
typ
max
Units
Digital Filter
Passband
(Note 18) -0.02dB
PB
0
87.0
kHz
-6.0dB
95.9
kHz
Stopband
(Note 18)
SB
105
kHz
Passband Ripple
PR
±0.06
dB
Stopband Attenuation
SA
70
dB
Group Delay
(Note 19)
GD
27
1/fs
Digital Filter + SCF
+0/-1
dB
Frequency Response: 0 ∼ 80.0kHz
Note 18.
fs(
)
1kHz
Note 19.
16/20/24bit
MS1258-J-01
2011/01
- 12 -
[AK4621]
DAC
(fs = 48kHz)
(Ta = 25°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 3.6V, TVDD=DVDD ∼ 5.25V; Normal Speed Mode; DEM = OFF;
SLOW bit = “1”, SDDA bit = “0”)
Parameter
Symbol
min
typ
max
Units
Digital Filter
Passband
(Note 18) -0.07dB
PB
0
8.9
kHz
-3.0dB
19.8
kHz
Stopband
(Note 18)
SB
42.6
kHz
Passband Ripple
PR
±0.07
dB
Stopband Attenuation
SA
73
dB
Group Delay
(Note 19)
GD
27
1/fs
Digital Filter + SCF
+0/-5
dB
Frequency Response: 0 ∼ 20.0kHz
DAC
(fs = 96kHz)
(Ta = 25°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 3.6V, TVDD=DVDD ∼ 5.25V; Double Speed Mode; DEM = OFF;
SLOW bit = “1”, SDDA bit = “0”)
Parameter
Symbol
min
typ
max
Units
Digital Filter
Passband
(Note 18) -0.07dB
PB
0
17.7
kHz
-3.0dB
39.5
kHz
Stopband
(Note 18)
SB
85.1
kHz
Passband Ripple
PR
±0.07
dB
Stopband Attenuation
SA
73
dB
Group Delay
(Note 19)
GD
27
1/fs
Digital Filter + SCF
+0/-4
dB
Frequency Response: 0 ∼ 40.0kHz
DAC
(fs = 192kHz)
(Ta = 25°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 3.6V, TVDD=DVDD ∼ 5.25V; Quad Speed Mode; DEM = OFF;
SLOW bit = “1”, SDDA bit = “0”)
Parameter
Symbol
min
typ
max
Units
Digital Filter
Passband
(Note 18) -0.07dB
PB
0
35.5
kHz
-3.0dB
79.0
kHz
Stopband
(Note 18)
SB
170.7
kHz
Passband Ripple
PR
±0.07
dB
Stopband Attenuation
SA
73
dB
Group Delay
(Note 19)
GD
27
1/fs
Digital Filter + SCF
+0/-5
dB
Frequency Response: 0 ∼ 80.0kHz
MS1258-J-01
2011/01
- 13 -
[AK4621]
DAC
(fs = 48kHz)
(Ta = 25°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 3.6V, TVDD=DVDD ∼ 5.25V; Normal Speed Mode; DEM = OFF;
SLOW bit = “0”, SDDA bit = “1”)
Parameter
Symbol
min
typ
max
Units
Digital Filter
Passband
(Note 18) -0.04dB
PB
0
21.8
kHz
-6.0dB
24.0
kHz
Stopband
(Note 18)
SB
26.2
kHz
Passband Ripple
PR
±0.06
dB
Stopband Attenuation
SA
70
dB
Group Delay
(Note 19)
GD
7
1/fs
Digital Filter + SCF
dB
Frequency Response: 0 ∼ 20.0kHz
± 0.2
DAC
(fs = 96kHz)
(Ta = 25°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 3.6V, TVDD=DVDD ∼ 5.25V; Double Speed Mode; DEM = OFF;
SLOW bit = “0”, SDDA bit = “1”)
Parameter
Symbol
min
typ
max
Units
Digital Filter
Passband
(Note 18) -0.03dB
PB
0
43.5
kHz
-6.0dB
48.0
kHz
Stopband
(Note 18)
SB
52.4
kHz
Passband Ripple
PR
±0.06
dB
Stopband Attenuation
SA
70
dB
Group Delay
(Note 19)
GD
7
1/fs
Digital Filter + SCF
dB
Frequency Response: 0 ∼ 40.0kHz
± 0.3
DAC
(fs = 192kHz)
(Ta = 25°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 3.6V, TVDD=DVDD ∼ 5.25V; Quad Speed Mode; DEM = OFF;
SLOW bit = “0”, SDDA bit = “1”)
Parameter
symbol
min
typ
max
Units
Digital Filter
Passband
(Note 18) -0.02dB
PB
0
87.0
kHz
-6.0dB
96.2
kHz
Stopband
(Note 18)
SB
104.9
kHz
Passband Ripple
PR
±0.06
dB
Stopband Attenuation
SA
70
dB
Group Delay
(Note 19)
GD
7
1/fs
Digital Filter + SCF
+0/-1
dB
Frequency Response: 0 ∼ 80.0kHz
MS1258-J-01
2011/01
- 14 -
[AK4621]
DC
(Ta=25°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 3.6V, TVDD=DVDD ∼ 5.25V)
Parameter
Symbol
min
High-Level Input Voltage
VIH
70%DVDD
Low-Level Input Voltage
VIL
High-Level Output Voltage (Iout=-100μA)
VOH
DVDD-0.5
VOL
Low-Level Output Voltage (Iout=100μA)
Input Leakage Current
Iin
-
typ
-
(Ta=25°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 3.6V, TVDD=DVDD ∼ 5.25V; CL=20pF)
Parameter
Symbol
min
typ
Master Clock Timing
Frequency
fCLK
8.192
Pulse Width Low
tCLKL
0.4/fCLK
Pulse Width High
tCLKH
0.4/fCLK
LRCK Frequency
(Note 20)
fsn
32
Normal Speed Mode (DFS0=“0”, DFS1=“0”)
fsd
54
Double Speed Mode (DFS0=“1”, DFS1=“0”)
fsq
108
Quad Speed Mode (DFS0=“0”, DFS1=“1”)
45
Duty Cycle
PCM Audio Interface Timing
BICK Period
Normal Speed Mode
tBCK
1/128fsn
Double Speed Mode
tBCK
1/64fsd
Quad Speed Mode
tBCK
1/64fsq
BICK Pulse Width Low
tBCKL
33
Pulse Width High
tBCKH
33
LRCK Edge to BICK “↑”
(Note 21)
tLRB
20
tBLR
20
BICK “↑” to LRCK Edge
(Note 21)
tLRS
LRCK to SDTO (MSB) (Except I2S mode)
tBSD
BICK “↓” to SDTO
tSDH
20
SDTI Hold Time
tSDS
20
SDTI Setup Time
Note 20. Normal Speed Mode, Double Speed Mode, Quad Speed Mode
Note 21.
LRCK
BICK
max
TVDD
30%DVDD
0.5
±10
Units
V
V
V
V
μA
max
Units
55.296
-
MHz
ns
ns
54
108
216
55
kHz
kHz
kHz
%
20
20
PDN pin
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RSTN bit
“↑”
MS1258-J-01
2011/01
- 15 -
[AK4621]
Parameter
Control Interface Timing
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
Reset Timing
PDN Pulse Width
RSTAD “↑” to SDTO Valid
Note 22. AK4621 PDN pin =“L”
Note 23. RSTAD bit
(Note 22)
(Note 23)
LRCK
Symbol
min
typ
max
Units
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
200
80
80
50
50
150
50
50
-
-
ns
ns
ns
ns
ns
ns
ns
ns
tPD
tPDV
150
-
516
-
ns
1/fs
“↑”
MS1258-J-01
2011/01
- 16 -
[AK4621]
■
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK
VIL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Figure 2. Clock Timing
VIH
VIL
LRCK
tBLR
tLRB
VIH
VIL
BICK
tLRS
tBSD
SDTO
50%TVDD
tSDS
tSDH
VIH
VIL
SDTI
Figure 3. Audio Interface Timing
MS1258-J-01
2011/01
- 17 -
[AK4621]
VIH
CSN
VIL
tCSH
tCSS
tCCKL tCCKH
VIH
CCLK
VIL
tCDS
C1
CDTI
tCDH
C0
R/W
A4
VIH
VIL
Figure 4. WRITE Command Input Timing
tCSW
VIH
CSN
VIL
tCSH
tCSS
VIH
CCLK
CDTI
VIL
D3
D2
D1
D0
VIH
VIL
Figure 5. WRITE Data Input Timing
tPD
PDN
VIL
Figure 6. Power Down & Reset Timing
MS1258-J-01
2011/01
- 18 -
[AK4621]
■
AK4621
ADC
MCLK, BICK, LRCK
(PDN pin = “H”)
“0”
DAC
MCLK LRCK
MCLK 9.38µs
(Hi-Z)
ON
MCLK LRCK
(PDN pin = “L” → “H”)
MCLK
AK4621
LRCK
1.
(P/S pin= “L”)
MCLK
CMODE, CKS1-0, DFS1-0 bits
(Table 1, Table 2, Table 3)
DFS1 bit
0
0
1
1
DFS0 bit
Mode
Sampling Rate
0
Normal speed
32kHz-54kHz
1
Double speed
54kHz-108kHz
0
Quad speed
108kHz-216kHz
1
N/A
Table 1. Sampling Speed in Serial Mode (N/A: Not Available)
(default)
MCLK
MCLK
MCLK
Normal Speed
Double Speed
Quad Speed
(DFS1-0 = “00”)
(DFS1-0 = “01”)
(DFS1-0 = “10”)
0
0
256fs
N/A
N/A
(default)
0
1
512fs
256fs
128fs
1
0
1024fs
512fs
256fs
1
1
N/A
Auto Setting Mode (*)
N/A
0
0
384fs
N/A
N/A
0
1
768fs
384fs
192fs
Table 2. Master Clock Frequency in Serial Mode (“*”; refer to Table 3.) (N/A: Not Available)
CMODE bit
0
0
0
0
1
1
DFS1-0 bits
RSTAD bit = RSTDA bit= “0”
CKS1 bit
CKS0 bit
Auto Setting Mode
MCLK
(Table 3)
LRCK
Normal/Double/Quad speed mode
MCLK/LRCK ratio
Mode
Sampling Rate
512 or 768
Normal speed
32kHz-54kHz
256 or 384
Double speed
54kHz-108kHz
128 or 192
Quad speed
108kHz-216kHz
Table 3. Auto Setting Mode in Serial Mode (DFS1-0 bits = “01”, CMODE bit = “0”, CKS1-0 bits = “11”)
MS1258-J-01
2011/01
- 19 -
[AK4621]
2.
(P/S pin= “H”)
Table 4, Table 5, Table 6
pin = “L”
MCLK
DFS0 pin
L
H
CKS0-1 and DFS0 pin
PDN
Mode
Sampling Rate
Normal speed
32kHz-54kHz
Double speed
54kHz-108kHz
Table 4. Sampling Speed in Parallel Mode
MCLK
MCLK
Normal Speed
Double Speed
(DFS0 pin = “L”)
(DFS0 pin = “H”)
L
L
256fs
N/A
L
H
512fs
256fs
H
L
384fs
Auto Setting Mode (*)
H
H
1024fs
512fs
Table 5. Master Clock Frequency in Parallel Mode (“*”; refer to Table 6.) (N/A: Not Available)
CKS1 pin
Auto Setting Mode
MCLK
(Table 6)
CKS0 pin
LRCK
Normal/Double/Quad speed mode
MCLK/LRCK ratio
Mode
Sampling Rate
512 or 768
Normal speed
32kHz-54kHz
256 or 384
Double speed
54kHz-108kHz
128 or 192
Quad speed
108kHz-216kHz
Table 6. Auto Setting Mode in Parallel Mode (DFS0 pin = “H”, CKS1 pin = “H”, CKS0 pin = “L”)
MCLK (Normal speed)
256fs
512fs
1024fs
384fs
768fs
MCLK (Quad speed)
128fs
256fs
192fs
fs=44.1kHz
11.2896MHz
22.5792MHz
45.1584MHz
16.9344MHz
33.8688MHz
fs=48kHz
12.288MHz
24.576MHz
49.152MHz
18.432MHz
36.864MHz
MCLK (Double speed)
N/A
256fs
512fs
N/A
384fs
fs=88.2kHz
N/A
22.5792MHz
45.1584MHz
N/A
33.8688MHz
fs=96kHz
N/A
24.576MHz
49.152MHz
N/A
36.864MHz
fs=176.4kHz
fs=192kHz
22.5792MHz 24.576MHz
45.1584MHz 49.152MHz
33.8688MHz 36.864MHz
Table 7. Master Clock Frequency Example (N/A: Not Available)
MS1258-J-01
2011/01
- 20 -
[AK4621]
■
5
)
(
2’s complement
MSB
SDTI BICK
LSB
“0”
2
Table 8 Table 9
SDTO BICK
Mode 2 16bit 20bit
DIF2-0 bit
DIF pin
Mode
0
1
2
3
4
DIF2
0
0
0
0
1
DIF1
0
0
1
1
0
Mode
2
3
DIF0
0
1
0
1
0
DIF pin
L
H
SDTO
SDTI
24bit, MSB justified
16bit, LSB justified
24bit, MSB justified
20bit, LSB justified
24bit, MSB justified
24bit, MSB justified
24bit, I2S
24bit, I2S
24bit, MSB justified
24bit, LSB justified
Table 8. Audio Data Format (Serial Mode)
LRCK
H/L
H/L
H/L
L/H
H/L
SDTO
SDTI
LRCK
24bit, MSB justified
24bit, MSB justified
H/L
24bit, I2S
24bit, I2S
L/H
Table 9. Audio Data Format (Parallel Mode)
BICK
≥ 48fs
≥ 48fs
≥ 48fs
≥ 48fs
≥ 48fs
(default)
BICK
≥ 48fs
≥ 48fs
LRCK
0
1
2
3
17
18
19
20
30
31
0
1
2
3
17
18
19
20
31
0
1
BICK(64fs)
SDTO(o)
23 22 21
SDTI(i)
7
Don’t Care
6
5
4
3
15 14 13 12 11
23 22 21
2
1
7
Don’t Care
0
6
5
4
3
15 14 13 12 11
SDTO-19:MSB, 0:LSB; SDTI-15:MSB, 0:LSB
Lch Data
23
2
1
0
Rch Data
Figure 7. Mode 0 Timing
LRCK
0
1
2
12
13
14
24
25
31
0
1
2
12
13
14
24
25
31
0
1
BICK(64fs)
SDTO(o)
SDTI(i)
23 22
12 11 10
Don’t Care
19 18
0
8
23 22
7
1
0
12 11 10
Don’t Care
SDTO-23:MSB, 0:LSB; SDTI-19:MSB, 0:LSB
Lch Data
19 18
0
8
23
7
1
0
Rch Data
Figure 8. Mode 1 Timing
MS1258-J-01
2011/01
- 21 -
[AK4621]
LRCK
0
1
2
18
19
20
21
22
23
24
25
0
1
2
18
19
20
21
22
23
24
25
0
1
BICK(64fs)
SDTO(o)
23 22
5
4
3
2
1
0
23 22
5
4
3
2
1
0
SDTI(i)
23 22
5
4
3
2
1
0
Don’t Care 23 22
5
4
3
2
1
0 Don’t Care
23:MSB, 0:LSB
Lch Data
23
Rch Data
Figure 9. Mode 2 Timing
LRCK
0
1
2
3
19
20
21
22
23
24
25
0
1
2
3
19
20
21
22
23
24
25
0
1
BICK(64fs)
SDTO(o)
23 22
5
4
3
2
1
0
23 22
5
4
3
2
1
0
SDTI(i)
23 22
5
4
3
2
1
0
Don’t Care 23 22
5
4
3
2
1
0 Don’t Care
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 10. Mode 3 Timing
LRCK
0
1
2
8
9
10
20
21
31
0
1
2
8
9
10
20
21
31
0
1
BICK(64fs)
SDTO(o)
SDTI(i)
23 22
16 15 14
Don’t Care
23:MSB, 0:LSB
23 22
0
12 11
23 22
1
0
16 15 14
Don’t Care
Lch Data
23 22
0
12 11
23
1
0
Rch Data
Figure 11. Mode 4 Timing
MS1258-J-01
2011/01
- 22 -
[AK4621]
■
AK4621 MUTE
(EATT)
DAC
256
(DATT) 16
EXTE bit
0dB
“1”
0dB
−48dB
−72dB
1
256+16
Sampling Speed
Transition Time
255 to 0
(EXTE bit = “0”)
1020LRCK
2040LRCK
4080LRCK
1 Level
Normal Speed Mode
4LRCK
Double Speed Mode
8LRCK
Quad Speed Mode
16LRCK
Table 10.
DATTL7-0 bits
DATTR7-0 bits
FFH
FEH
FDH
:
02H
01H
00H
Table 11.
DATTL7-0 bits
DATTR7-0 bits
FFH
FEH
FDH
:
02H
01H
256
Table 13
Table 10
DATT_DATA
255
254
253
:
2
1
-
DATT_DATA
00H
EATTL3-0 bits
EATTR3-0 bits
255
254
253
:
2
1
-
Note 24. DATT
EATT
Normal Speed Mode
4LRCK
FH
255+15 to 0
(EXTE bit = “1”)
1080LRCK
2160LRCK
4320LRCK
GAIN(0dB)
+0
-0.034
-0.068
:
-42.11
-48.13
Mute
(EXTE bit = “0”)
EATTL3-0 bits
EATT_DATA
EATTR3-0 bits
FH
FH
EH
:
2H
1H
0H
EATT
-
15
14
:
2
1
DATT
(default)
GAIN(0dB)
+0
-0.034
-0.068
:
-42.11
-48.13
-48.72
-49.32
:
-66.22
-72.25
Mute
4LRCK
Table 12.
(EXTE bit = “1”)
MS1258-J-01
2011/01
- 23 -
[AK4621]
DATTL7-0 bits
DATTR7-0 bits
FFH
:
01H
EATTL3-0 bits
EATTR3-0 bits
GAIN(dB)
FH
20 log10 (DATT_DATA / 255)
FH
:
1H
20 log10 (EATT_DATA / 4095)
00H
Table 13.
■
ADC
ch
Lch/Rch
(PDN pin = “H”)
ZOS bit =ZOE bit = “0”
(-0.3dBFS
)
OVF
ADC
516/fs(=10.8ms@fs=48kHz)
OVFL/R pin
“L”
OVFL/R pin
“H”
■
AK4621
ZOE bit = “0”
DZF pin
“H”
DZF pin “L”
“0”
DZFE bit
ZOS bit = “1”
RSTDA bit
“0”
8192
“0”
“0”
DZF pin “H”
DZF pin 2 ∼ 3LRCK
“L”
DZF pin
“L”
DZF pin
DZFB bit
■
ADC
DC
HPLN bit, HPRN bit
HPF
fs
L/R
HPF
MS1258-J-01
HPF
ON
fc
fs=48kHz
1.0Hz
2011/01
- 24 -
[AK4621]
■
ADC
1/2
DAC
SDFIL pin, SDAD, SDDA, SLOW bits
SDFIL pin
L
H
1/2/3
ADC
DAC
Short Delay Sharp Roll Off Filter
Short Delay Sharp Roll Off Filter
Sharp Roll Off Filter
Sharp Roll Off Filter
Table 14. Digital Filter Selection in Parallel Mode
SDAD bit
ADC
0
Sharp Roll Off Filter
(default)
1
Short Delay Sharp Roll Off Filter
Table 15. ADC Digital Filter Selection in Serial Mode
SDDA bit
SLOW bit
DAC
0
0
Sharp Roll Off Filter
(default)
0
1
Slow Roll Off Filter
1
0
Short Delay Sharp Roll Off Filter
1
1
N/A
Table 16. DAC Digital Filter Selection in Serial Mode (N/A: Not Available)
■
DAC
IIR
OR
OFF)
2
3
(32kHz, 44.1kHz, 48kHz)
DEM1-0 bits
DEM0 pin
DEM1 ”0”
4
(50/15μs
)
DEM0 bit DEM0 pin
DEM0 pin
(44.1kHz or
OFF
No
0
1
2
3
DEM1
DEM0
Mode
0
0
44.1kHz
(default)
0
1
OFF
1
0
48kHz
1
1
32kHz
Table 17. De-emphasis Control (Normal Speed Mode)
MS1258-J-01
2011/01
- 25 -
[AK4621]
■
× ATT
−∞
−∞
SMUTE bit “1”
−∞ (“0”)
× ATT
ATT
(Table 10)
−∞
ATT
ATT
SMUTE bit
ATT
“0”
ATT
S M U T E bit
(1)
(1)
AT T _Level
(3)
A ttenuation
-∞
GD
(2)
GD
(2)
AOUT
(4)
8192/fs
D ZF pin
:
(1)ATT
× ATT
(Table 10)
1080LRCK
(EXTE bit = “1”)
(2)
(3)
−∞
ATT
(4)
8192
“0”
(EXTE bit = “0”)
−∞
(GD)
“0”
Normal Speed Mode
1020LRCK
DZF pin “H”
DZF pin “L”
Figure 12. Soft Mute and Zero Detection
MS1258-J-01
2011/01
- 26 -
[AK4621]
■
AK4621
ADC
DAC
PDN pin
“L”
PDN pin=“L”
1
(RSTAD
ADC, DAC
bit = RSTDA bit =“0”)
ADC
SDTO 516 x LRCK
DAC
(PWAD bit, PWDA bit)
Power Supply
PDN pin
RSTAD/RSTDA bit
PWAD/PWDA bit
PWVR bit
(1)
ADC Internal State
PD
Reset
(1)
(1)
INITA
Normal
GD (2)
PD
INITA
Normal
GD (2)
PD
INITA
Normal
GD (2)
ADC In (Analog)
ADC Out (Digital)
“0” data (3)
“0” data (3)
DAC Internal State
PD
Reset
Normal
PD
Normal
(4)
DATT
FFH
DAC In (Digital)
PD
(4)
FFH*1 FFH=>XXH
XXH
Normal
(4)
XXH*2 XXH=>YYH
YYH*3 YYH=>ZZH
YYH
ZZH
“0”data
(5)
VCOM
Hi-Z
DAC Out (Analog)
(6)
External Mute
Example
(5)
Hi-Z
GD (2)
(6)
(6)
FADE
Mute On (7)
Clock In
(6)
(5)
Hi-Z
GD (2)
(6)
FADE
(1) ADC
(2)
(3)
(4)
*1 RSTDA bit
*2 PWDA bit
GD (2)
(6)
FADE
Mute On (7)
Mute On (7)
(8)
Stop
Don’t care
MCLK, LRCK, BICK
*3 Clock
“0” data (3)
(516/fs)
ADC
“0”
“L”
DATT
“L”
DATT
(MCLK, LRCK, BICK)
(5)
DAC
(6) RSTDA bit
PWDA bit
(7)
(6)
(8) MCLK 9.38µs
(Hi-Z)
DATT
“XXH”
DATT
“YYH”
DATT
DATT
VCOM
FFH
XXH
XXH
YYH
“ZZH”
DAC
DATT
YYH
ZZH
Hi-Z
ADC
“0”
DAC
Figure 13. Reset & Power Down Sequence in Serial Mode
MS1258-J-01
2011/01
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[AK4621]
PDN pin
“H”
“0”
516/fs
ADC, DAC
DAC
PDN pin
“L”
Power Supply
PDN pin
(1)
ADC Internal State
PD
(1)
(1)
INITA
Normal
GD (2)
PD
INITA
Normal
GD (2)
PD
INITA
Normal
GD (2)
ADC In (Analog)
ADC Out (Digital)
DAC Internal State
DAC In (Digital)
DAC Out (Analog)
External Mute
Example
Clock In
MCLK, LRCK, BICK
(1) ADC
(2)
(3)
(4)
(5) PDN pin
(6)
(5)
(7) MCLK 9.38µs
“0” data (3)
“0” data (3)
PD
Normal
“0”data
(4)
Hi-Z
PD
(5)
(5)
Mute On (6)
PD
Normal
(4)
Hi-Z
GD (2)
“0” data (3)
GD (2)
Normal
GD (2)
(4)
Hi-Z
(5)
(5)
(5)
Mute On (6)
Mute On (6)
(7)
Stop
Don’t care
(516/fs)
ADC
DAC
“0”
Hi-Z
PDN pin
ADC
“0”
DAC
(Hi-Z)
Figure 14. Reset & Power Down Sequence in Parallel Mode
MS1258-J-01
2011/01
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[AK4621]
■
3
I/F pin: CSN, CCLK, CDTI
Read/Write(1bit) Register address(MSB first, 5bits)
CCLK
bit
16
CCLK
CSN
I/F
Control data(MSB first, 8bits)
CSN
CCLK
“10”
Chip address(2bits, C0/1)
5MHz(max)
“10”
PDN pin=“L”
Function
Parallel mode
Serial mode
Overflow detection
X
X
DAC Slow Roll Off Filter
X
Zero detection
X
Soft Mute
X
DATT
X
HPF OFF
X
16/20/24 bit LSB justified format of DAC
X
MCLK = 256fs @ Quad Speed
X
De-emphasis: 32kHz, 48kHz
X
Table 18. Function List (X: available, -: not available)
CSN
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0:
R/W:
A4-A0:
D7-D0:
Chip Address (Fixed to “10”)
READ/WRITE (Fixed to “1”:WRITE)
Register Address
Control data
Figure 15. Control I/F Timing
* READ
* CSN pin = “L”
CCLK
↑
15
17
MS1258-J-01
2011/01
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[AK4621]
■
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
Register Name
Power Down Control
Reset Control
Clock and Format Control
Deem and Volume Control
Reserved
Reserved
Lch DATT Control
Rch DATT Control
Lch Extension DATT Control
Rch Extension DATT Control
D7
SLOW
0
DIF2
SMUTE
0
0
DATTL7
DATTR7
0
0
D6
DZFB
0
DIF1
HPRN
0
0
DATTL6
DATTR6
0
0
D5
ZOE
0
DIF0
HPLN
0
0
DATTL5
DATTR5
EXTE
0
D4
ZOS
SDAD
CMODE
0
0
0
DATTL4
DATTR4
0
0
D3
SDDA
0
CKS1
0
0
0
DATTL3
DATTR3
EATTL3
EATTR3
D2
PWVR
0
CKS0
0
0
0
DATTL2
DATTR2
EATTL2
EATTR2
D1
PWAD
RSTAD
DFS1
DEM1
0
0
DATTL1
DATTR1
EATTL1
EATTR1
D0
PWDA
RSTDA
DFS0
DEM0
0
0
DATTL0
DATTR0
EATTL0
EATTR0
Note 25: 0AH
1FH
PDN pin=“L”
■
PDN pin
“L”
“H”
AK4621
(1)
(2) RSTAD bit, RSTDA bit
(3) ADC
DAC
“1”
Reset Control Register (01H)
RSTAD bit
RSTDA bit
“0”
ADC
DAC
MS1258-J-01
2011/01
- 30 -
[AK4621]
■
Addr
00H
Register Name
Power Down Control
Default
D7
SLOW
0
D6
DZFB
0
D5
ZOE
0
PWDA: DAC power down
0: Power down
1: Power up (default)
“0” DAC
D4
ZOS
0
D3
SDDA
0
AOUT
D2
PWVR
1
D0
PWDA
1
Hi-Z
ATT
(06H, 07H, 08H, 09H)
PWAD: ADC power down
0: Power down
1: Power up (default)
“0” ADC
SDTO pin
516LRCK
D1
PWAD
1
“L”
“0”
PWVR: Vref power down
0: Power down
1: Power up (default)
“0”
ADC
PWAD = PWDA bit = “0”
DAC
PWVR bit = “1”
VREF
SDDA: DAC Short Delay Sharp Roll Off Filter Enable (Table 16)
Default: Disable
ZOS: Zero-detection/ Overflow-detection control for OVFL/DZFL and OVFR/DZFR pins.
0: Overflow detection for ADC input (default)
1: Zero detection for DAC input.
ZOE: Zero-detection / Overflow-detection Disable
0: Enable (default)
1: Disable. Outputs “L”.
DZFB: Inverting Enable of DZF
0: DZF goes “H” at Zero Detection (default)
1: DZF goes “L” at Zero Detection
SLOW: DAC Slow Roll Off Filter Enable (Table 16)
Default: Disable
MS1258-J-01
2011/01
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[AK4621]
Addr
01H
Register Name
Reset Control
Default
D7
0
0
D6
0
0
D5
0
0
D4
SDAD
0
RSTDA: DAC reset
0: Reset (default)
1: Normal Operation
“0” DAC
D3
0
0
D2
0
0
AOUT pin
D1
D0
RSTAD
RSTDA
0
0
VCOM
ATT
(06H, 07H, 08H,
09H)
RSTAD: ADC reset
0: Reset (default)
1: Normal Operation
“0” ADC
SDTO pin
516LRCK
“L”
“0”
SDAD: ADC Short Delay Sharp Roll Off Filter (Table 15)
Default: Disable
Addr
02H
Register Name
Clock and Format Control
Default
D7
DIF2
0
D6
DIF1
1
D5
DIF0
0
D4
CMODE
0
D3
CKS1
0
D2
CKS0
0
D1
DFS1
0
D0
DFS0
0
DFS1-0: Sampling Speed Control (Table 1)
Default: Normal speed
CMODE, CKS1-0: Master Clock Frequency Select (Table 2)
Default: 256fs
DIF2-0: Audio data interface modes (Table 8)
000: Mode 0
001: Mode 1
010: Mode 2 (default)
011: Mode 3
100: Mode 4
Default: 24bit MSB justified for both ADC and DAC
MS1258-J-01
2011/01
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[AK4621]
Addr
03H
Register Name
D7
Deem and Volume Control
D6
HPRN
0
SMUTE
Default
0
D5
HPLN
0
D4
0
0
D3
0
0
D2
0
0
D1
DEM1
0
D0
DEM0
1
DEM1-0: De-emphasis response (Table 17)
00: 44.1kHz
01: OFF (default)
10: 48kHz
11: 32kHz
HPLN/RN: Left/Right channel Digital High Pass Filter Disable
0: Enable (default)
1: Disable
SMUTE: DAC Input Soft Mute control
0: Normal operation (default)
1: DAC outputs soft-muted
The soft mute is independent of the output ATT and performed digitally.
Addr
06H
07H
Register Name
Lch DATT Control
Rch DATT Control
Default
D7
D6
D5
D4
D3
D2
D1
D0
DATTL7
DATTR7
DATTL6
DATTR6
DATTL5
DATTR5
DATTL4
DATTR4
DATTL3
DATTR3
DATTL2
DATTR2
DATTL1
DATTR1
DATTL0
DATTR0
1
1
1
1
1
1
1
1
D2
EATTL2
EATTR2
1
D1
EATTL1
EATTR1
1
D0
EATTL0
EATTR0
1
DATT7-0: DAC Output Attenuation Level; Linear step (Table 12, Table 13)
FFH: 0dB (Default)
Addr
08H
09H
Register Name
Lch Extension DATT Control
Rch Extension DATT Control
Default
D7
0
0
0
D6
0
0
0
D5
EXTE
0
0
D4
0
0
0
D3
EATTL3
EATTR3
1
EATT3-0: DAC Output Extension Attenuation Level; Linear step (Table 12, Table 13)
Default: FH
EXTE: Extension DATT Enable
0: Disable (default)
1: Enable
MS1258-J-01
2011/01
- 33 -
[AK4621]
Figure 16
0.1u
(AKD4621)
10u
+
1
VCOM
AOUTR+
30
Rch
Input
Buffer
2
AINR +
AOUTR-
29
3
AINR -
AOUTL+
28
Lch
Input
Buffer
4
AINL+
AOUTL-
27
5
AINL-
VSS2
26
6
VREF
DVDD
25
7
VSS1
TVDD
24
8
AVDD
SDFIL
23
9
P/S
DEM0
22
10 MCLK
PDN
21
11 LRCK
DFS0
20
CSN/DIF
19
13 SDTO
CCLK/CKS1
18
14 SDTI
CDTI/CKS0
17
15 OVFR/DZFR
OVFL/DZFL
16
4.75 ∼ 5.25V
Analog Supply +
10u
0.1u
Audio
DSP
AK4621
12 BICK
0.1u
Rch
LPF
Rch Out
Lch
LPF
Lch Out
0.1u
3.0 ∼ 3.6V
Digital Supply
DVDD ∼ 5.25V
Digital Supply
Mode
Setting/
uP
:
- AK4621 VSS1, VSS2
- AOUT+/−
Figure 16. Typical Connection Diagram
MS1258-J-01
2011/01
- 34 -
[AK4621]
Digital Ground
Analog Ground
System
Controller
1
VCOM
AOUTR+
30
2
AINR+
AOUTR-
29
3
AINR-
AOUTL+
28
4
AINL+
AOUTL-
27
5
AINL-
VSS2
26
6
VREF
DVDD
25
7
VSS1
TVDD
24
8
AVDD
SDFIL
23
9
P/S
DEM0
22
10
MCLK
PDN
21
11
LRCK
DFS0
20
12
BICK
CSN/DIF
19
13
SDTO
CCLK/CKS1
18
14
SDTI
CDTI/CKS0
17
15
OVFR/DZFR
OVFL/DZFL
16
AK4621
Figure 17. Ground Layout
1.
AVDD, DVDD, TVDD
DVDD, TVDD
AVDD
AVDD, DVDD, TVDD
AVDD, DVDD, TVDD
VSS1
VSS2
AK4621
2.
VREF pin VSS1
0.1μF
VREF pin
VSS1
VCOM
10μF
VSS1
VCOM pin
VREF pin
AVDD
0.1μF
VCOM pin
3. ADC
2’s complement
DC
ADC
(ADC
DC
)
128fs (@Normal Speed Mode), 64fs
HPF (fc=1.0Hz@fs=48kHz)
(@Double Speed Mode) or 32fs (@Quad Speed Mode)
128fs (@Normal Speed Mode), 64fs (@Double Speed Mode) or 32fs (@Quad Speed Mode)
MS1258-J-01
2011/01
- 35 -
[AK4621]
4.
VSS1
AVDD
Figure 18
AINL+/−(AINR+/−)
360kHz
2.82Vpp (typ. VREF=5V)
−10dB
10nF
LPF
22Ω
LPF
370kHz
910
4.7k
Analog In
4.7k
470p
VP+
47μ
VP9.3Vpp
3k
22
910
10k
0.1μ 10μ
47μ
Bias
VA = 5V
VP+ = 15V
VP- = -15V
3k
AK4621
10n
470p
10k
AIN+
Bias
NJM5532
VA
2.82Vpp
22
Bias
AIN2.82Vpp
Figure 18. Input Buffer example
MS1258-J-01
2011/01
- 36 -
[AK4621]
5.
(
VREF =5V)
(AOUT−)
1
800000H(@24bit)
ΔΣ
Figure 19
(
AVDD/2)
2.8Vpp (typ.
Vout = (AOUT+) −
AOUT+ AOUT−
5.6Vpp (typ@VREF=5V)
2’s complement
7FFFFFH(@24bit)
000000H(@24bit)
AOUT
)
1
0V
(SCF)
LPF
Figure 20
3
LPF
AK4621
AOUT-
4.7k
4.7k
200
330p
+Vop
AOUT+
2.2n
4.7k
4.7k
Analog
Out
200
330p
-Vop
Figure 19. External LPF Circuit Example 1 (fc = 136kHz, Q=0.694)
Frequency Response
Gain
20kHz
−0.01dB
40kHz
−0.06dB
80kHz
−0.59dB
Table 19. Frequency Response of External LPF Circuit Example 1
MS1258-J-01
2011/01
- 37 -
[AK4621]
+15
3.3n
+
AOUTL- +
3.9n
10k
330
180
7
3
2 +
4
-15
10u
0.1u
6
NJM5534D
+
0.1u
620
620
3.3n
+
100u
180
AOUT L+ +
3.9n
10k
330
7
3
+
2 4
2 - 4
3 + 7
100
6
Lch
1.0n NJM5534D
10u
0.1u
6
NJM5534D
+
0.1u
10u
+
10u
0.1u
1.2k
680
+10u
1.0n
1.2k
680
0.1u
560
10u
560
100u
Figure 20. External LPF Circuit Example 2
1st Stage
2nd Stage
Total
Cut-off Frequency
182kHz
284kHz
Q
0.637
Gain
+3.9dB
-0.88dB
+3.02dB
20kHz
-0.025
-0.021
-0.046dB
Frequency
40kHz
-0.106
-0.085
-0.191dB
Response
80kHz
-0.517
-0.331
-0.848dB
Table 20. Frequency Response of External LPF Circuit Example 2
MS1258-J-01
2011/01
- 38 -
[AK4621]
30pin VSOP (Unit: mm)
*9.7±0.1
1. 5MAX
0.3
30
16
7.6± 0.2
5.6±0.1
A
15
1
0.24± 0. 06
+0.06
0.65
0.12 M
0.17 -0.05
0.45± 0.2
0.10
0.08 S
+0.1 0
-0 .05
1.2± 0.10
D etail A
0° ~ 8°
N OTE: Dimension "* " does not include mold flash.
■
:
(
:
:
(
)
)
MS1258-J-01
2011/01
- 39 -
[AK4621]
AKM
AK4621EF
XXXXYYYYZ
YYYY:
XXXX, Z:
Date code
Internal control code
MS1258-J-01
2011/01
- 40 -
[AK4621]
Date (YY/MM/DD)
10/12/07
11/01/26
Revision
00
01
Reason
Page
Contents
MS1258-J-01
2011/01
- 41 -