[AK4452] AK4452 115dB 768kHz 32-bit 2ch Premium DAC 1. General Description The AK4452 is a 32-bit 2ch Premium DAC, which achieves industry’s best low distortion characteristics by a newly developed low distortion technology. It corresponds to a 768kHz PCM input and an 11.2MHz DSD input at maximum, suitable for play backing high resolution audio sources that are becoming widespread in network audios, USB-DACs and Car Audio Systems. In addition, “OSR-Doubler” technology is newly adopted, making the AK4452 capable of supporting wide range signals and achieving low out-of-band noise while realizing low power consumption. Moreover, the AK4452 has five types of 32-bit digital filters, realizing simple and flexible sound making in wide range of applications. Application: AV Receivers, CD/SACD Players, Network Audios, USB DACs, USB Headphones, Sound Plate/Bars, Car Audios, Automotive External Amplifiers, Measuring Instruments and Control Systems. 2. Features (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) DR, S/N: 115dB THD+N: -107dB 256x Over sampling Sampling Rate: 8kHz 768kHz 32Bit 8x Digital Filter - Ripple: 0.0032dB, Attenuation: 80dB (Sharp Roll-Off Filter Setting) - Five Types of High Quality Sound Filter Option - Sharp Roll-Off Filter - Slow Roll-Off Filter - Short Delay Sharp Roll-Off Filter (GD=5.8/fs) - Short Delay Slow Roll-Off Filter (GD=4.8/fs) - Super Slow Roll-Off Filter High Tolerance to Clock Jitter Low Distortion Differential Output DSD data input Daisy Chain Digital De-emphasis for 32, 44.1, 48kHz sampling Soft Mute Digital Attenuator (255 levels and 0.5dB step) I/F Format: - 24/32bit MSB justified - 16/20/24/32bit - LSB justified - I2S - DSD - TDM 3-wire Serial and I2C μP I/F Master Clock: - 30kHz ~ 32kHz: 1152fs - 30kHz ~ 54kHz: 512fs or 768fs - 30kHz ~ 108kHz: 256fs or 384fs - 108kHz ~ 216kHz: 128fs or 192fs ~ 384kHz: 64fs or 128fs ~ 768kHz: 64fs 015002211-E-02 2015/08 -1- [AK4452] (16) Digital Input Level: CMOS (17) Power Supply: - TVDD= 1.7 3.6V - AVDD=3.0 5.5V (18) Supporting 105°C Temperature (Exposed pad is connected to ground) (19) Package: 32-pin QFN 015002211-E-02 2015/08 -2- [AK4452] 3. Table of Contents 1. 2. 3. 4. General Description ................................................................................................................................... 1 Features ...................................................................................................................................................... 1 Table of Contents ....................................................................................................................................... 3 Block Diagram and Functions ................................................................................................................... 5 ■ Block Diagram.......................................................................................................................................... 5 ■ Functions .................................................................................................................................................. 6 5. Pin Configurations and Functions .............................................................................................................. 7 ■ Ordering Guide ......................................................................................................................................... 7 ■ Pin Configurations .................................................................................................................................... 7 ■ Pin Functions ............................................................................................................................................ 8 ■ Handling of Unused Pin ........................................................................................................................... 9 6. Absolute Maximum Ratings .................................................................................................................... 10 7. Recommended Operation Conditions ...................................................................................................... 10 8. Electrical Characteristics ......................................................................................................................... 11 ■ Analog Characteristics............................................................................................................................ 11 ■ Sharp Roll-Off Filter Characteristics ...................................................................................................... 13 ■ Slow Roll-Off Filter Characteristics ....................................................................................................... 14 ■ Short Delay Sharp Roll-Off Filter Characteristics.................................................................................. 15 ■ Short Delay Slow Roll-Off Filter Characteristics................................................................................... 16 ■ DSD Mode Characteristics ..................................................................................................................... 17 ■ DC Characteristics .................................................................................................................................. 17 ■ Switching Characteristics ....................................................................................................................... 18 ■ Timing Diagram ..................................................................................................................................... 22 9. Functional Descriptions ........................................................................................................................... 26 ■ D/A Conversion Mode (PCM mode, DSD mode) .................................................................................. 26 ■ System Clock .......................................................................................................................................... 26 ■ Audio Interface Format .......................................................................................................................... 30 ■ D/A Conversion Mode (PCM Mode, DSD Mode) Switching Timing ................................................... 42 ■ Digital Filter (PCM mode) ..................................................................................................................... 43 ■ De-emphasis Filter (PCM mode) ............................................................................................................ 43 ■ Output Volume (PCM mode, DSD mode) ............................................................................................. 44 ■ Out of Band Noise Reduction Filter (PCM mode, DSD mode) ............................................................. 45 ■ Zero Detection (PCM mode, DSD mode) .............................................................................................. 51 ■ LR Channel Output Signal Select (PCM mode, DSD mode) ................................................................. 51 ■ Sound Quality Adjustment (PCM mode, DSD mode)............................................................................ 52 ■ DSD Full Scale (FS) Signal Detection Function .................................................................................... 53 ■ Soft Mute Operation (PCM mode, DSD mode) ..................................................................................... 54 ■ Error Detection ....................................................................................................................................... 55 ■ System Reset .......................................................................................................................................... 55 ■ Power Down Function ............................................................................................................................ 56 ■ Power Off and Reset Functions .............................................................................................................. 57 ■ Clock Synchronization and BICK Edge Detection Functions ................................................................ 60 ■ Parallel Mode.......................................................................................................................................... 61 ■ Serial Control Interface .......................................................................................................................... 61 ■ Function List........................................................................................................................................... 66 ■ Register Map .......................................................................................................................................... 67 ■ Register Definitions ................................................................................................................................ 68 10. Recommended External Circuits.......................................................................................................... 75 015002211-E-02 2015/08 -3- [AK4452] ■ Typical Connection Diagram.................................................................................................................. 75 11. Package ................................................................................................................................................ 79 ■ Outline Dimensions ................................................................................................................................ 79 ■ Material & Lead finish ........................................................................................................................... 79 ■ Marking .................................................................................................................................................. 80 12. Revision History .................................................................................................................................. 80 IMPORTANT NOTICE ................................................................................................................................ 82 015002211-E-02 2015/08 -4- [AK4452] 4. Block Diagram and Functions ■ Block Diagram LDOE TVDD VDD18 DVSS PDN AVDD AVSS Bias LDO BICK/DCLK DATT Soft Mute LRCK/DSDL1 8X Interpolator SCF AOUTL1P AOUTL1N SDTI1/DSDR1 PCM Data Interface TDMO1 De-empha sis Modulator DATT Soft Mute DSD Filter Vref VREFH1 VREFL1 Noise Rejection Filter SCF AOUTR1P AOUTR1N TST1 DSD Data Interface TST2 TST3 TST4 DZF/SMUTE TST5 CAD1/DCHAIN TST6 TST7 I2C CAD0_I2C/CSN/DIF Control Register SCL/CCLK/TDM1 Clock Divider SDA/CDTI/TDM0 PS/CAD0_SPI MCLK Figure 1. Block Diagram 015002211-E-02 2015/08 -5- [AK4452] ■ Functions Block Functions This block executes serial/parallel conversion of SDTI input audio data by PCM Data Interface synchronizing with LRCK and BICK. 1-bit data that is input from DSDL1 and DSDR1 pins is received by synchronizing DSD Data Interface with DCLK. Apply DATT and Soft Mute process to input data. DATT、Soft Mute De-emphasis Apply De-emphasis process to input data. 8x Interpolator FIR filters that over sample 1fs rate data to 8fs rate. Output multi-bit data to SCF. This block consists of a third-order digital delta-sigma ΔΣ Modulator modulator. Noise Rejection Filter Attenuate out of band noise to prevent degradation of analog characteristics. A primary switched capacitor filter that converts a multi-bit output of delta-sigma SCF modulator to an analog signal. LDO Generate power for internal digital circuit (1.8V typ.). Control Register Clock Divider Keep register settings for each mode. Divide Master Clock In PCM mode, master clock is divided automatically by fs rate auto detection function. In DSD mode, the master clock frequency is set by DCKS bit. 015002211-E-02 2015/08 -6- [AK4452] 5. Pin Configurations and Functions ■ Ordering Guide 40 +105°C (Exposed pad is connected to ground) 40 +85°C (Exposed pad is open) 32-pin QFN Evaluation Board for AK4452 AK4452VN AKD4452 TST4 TST3 TST2 AVDD AVSS AOUTR1P AOUTR1N VREFH1 24 23 22 21 20 19 18 17 ■ Pin Configurations TST5 25 16 VREFL1 TST6 26 15 AOUTL1N TST7 27 14 AOUTL1P LDOE 28 13 I2C TVDD 29 12 PS/CAD0_SPI DVSS 30 11 CAD0_I2C/CSN/DIF VDD18 31 10 SCL/CCLK/TDM1 PDN 32 9 SDA/CDTI/TDM0 Top View 1 2 3 4 5 6 7 8 MCLK BICK/DCLK LRCK/DSDL1 SDTI1/DSDR1 TST1 TDMO1 DZF/SMUTE CAD1/DCHAIN Back Tab:Note1 Note 1. The exposed pad at back face of the package must be open or connected to the ground. 015002211-E-02 2015/08 -7- [AK4452] ■ Pin Functions No . 1 Pin Name I/O Function PD Status 5 MCLK BICK DCLK LRCK DSDL1 SDTI1 DSDR1 TST1 I I I I I I I I External Master Clock Input Pin Audio Serial Data Clock Pin in PCM mode DSD Clock Pin in DSD mode Input Channel Clock Pin in PCM mode Audio Serial Data Input in DSD mode Audio Serial Data Input in PCM mode Audio Serial Data Input in DSD mode Test Pin. This pin must be connected to DVSS 6 TDMO1 O Audio Serial Data Output in Daisy Chain mode DZF O Zero Input Detect in I2C Bus or 3-wire serial control mode Soft Mute Pin in Parallel control mode. When this pin is changed to “H”, soft mute cycle is initiated. When returning “L”, the output mute releases. Chip Address 0 Pin in I2C Bus or 3-wire serial control mode Daisy Chain Mode select pin in Parallel control mode. Control Data Input Pin in I2C Bus serial control mode Control Data Input Pin in 3-wire serial control mode TDM Mode select pin in Parallel control mode. Control Data Clock Pin in I2C Bus serial control mode Control Data Clock Pin in 3-wire serial control mode TDM Mode select pin in Parallel control mode. Chip Address 0 Pin in I2C Bus serial control mode Chip Select Pin in 3-wire serial control mode Audio Data Format Select in Parallel control mode. “L”：32-bit MSB, “H”：32-bit I2S (I2C pin = “H”) Control Mode Select Pin “L”: I2C Bus serial control mode ,“H”: Parallel control mode. (I2C pin = “L”) Chip Address 0 Pin in 3-wire serial control mode Control Mode Select Pin “L”: 3-wire serial control mode “H”: I2C Bus serial control mode or Parallel control mode. L ch Positive Analog Output 1 Pin L ch Negative Analog Output 1 Pin Negative Voltage Reference Input Pin, AVSS Positive Voltage Reference Input Pin, AVDD R ch Negative Analog Output 1 Pin R ch Positive Analog Output 1 Pin Analog Ground Pin Analog Power Supply Pin, 3.0V5.5V Test Pin. This pin must be connected to AVSS. Test Pin. This pin must be connected to AVSS. Test Pin. This pin must be connected to AVSS. Test Pin. This pin must be connected to AVSS. 2 3 4 7 8 9 10 11 SMUTE CAD1 DCHAIN SDA CDTI TDM0 SCL CCLK TDM1 CAD0_I2C CSN I I I I/O I I I I I I I DIF I PS I 12 CAD0_SPI I 13 I2C I 14 15 16 17 18 19 20 21 22 23 24 25 AOUTL1P AOUTL1N VREFL1 VREFH1 AOUTR1N AOUTR1P AVSS AVDD TST2 TST3 TST4 TST5 O O I I O O I I I I 015002211-E-02 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 100kΩ Pull down 100kΩ Pull down Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z － － Hi-Z Hi-Z Hi-Z Hi-Z 2015/08 -8- [AK4452] No . 26 27 Pin Name TST6 TST7 I/O Function PD Status I I Test Pin. This pin must be connected to AVSS. Hi-Z Test Pin. This pin must be connected to AVSS. Hi-Z Internal LDO Enable Pin. 28 LDOE I Hi-Z “L”: Disable, “H”: Enable 29 TVDD Digital Power Supply Pin, 3.0V3.6V － Digital Ground Pin 30 DVSS － (LDOE pin = “H”) O LDO Output Pin This pin should be connected to DVSS with 1.0µF. 31 VDD18 (Note 4) (LDOE pin = “L”) I 1.8V Power Input Pin Power-Down & Reset Pin 32 PDN I When “L”, the AK4452 is powered-down and the control Hi-Z registers are reset to default state. Note 2. All input pins except internal pull-up/down pins must not be allowed to float. Note 3. PCM mode and DSD mode are controlled by registers. Daisy Chain mode is controlled by both registers and pins. Note 4. This pin outputs DVSS when the LDOE pin = “H” and Hi-z when the LDOE pin = “L”. ■ Handling of Unused Pin The unused I/O pins must be connected appropriately. Classification Pin Name Setting Analog AOUTL1P/N, AOUTR1P/N These pins must be open. Digital TDMO1, DZF This pin must be open. 015002211-E-02 2015/08 -9- [AK4452] 6. Absolute Maximum Ratings (AVSS =DVSS =0V; Note 5) Parameter Symbol Min. 0.3 Power Supplies: Analog AVDD Digital TVDD 0.3 |AVSS DVSS| GND Input Current, Any Pin Except Supplies IIN Digital Input Voltage VIND 0.3 Ambient Temperature (Power applied) When the back tab is connected to VSS Ta 40 When the back tab is open Ta 40 Storage Temperature Tstg 65 Note 5. All voltages with respect to ground. Note 6. AVSS and DVSS must be connected to the same analog ground plane. Max. 6.0 4.0 0.3 10 TVDD+0.3 Unit V V V mA V 105 85 150 C C C WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 7. Recommended Operation Conditions (AVSS =DVSS =0V; Note 5) Parameter Symbol Min. Typ. Max. Unit Analog AVDD 3.0 5.0 5.5 V (LDOE pin= “L”) (Note 7) Power Supplies I/O buffer TVDD VDD18 1.8 3.6 V Digital VDD18 1.7 1.8 1.98 V (LDOE pin = “H”)(Note 8) I/O buffer TVDD 3.0 3.3 3.6 V Voltage Reference “H” voltage reference “L” VREFH1 AVDD0.5 AVDD V voltage reference VREFL1 AVSS V Note 7. When the LDOE pin = “L” VDD18 must be powered up either at the same time or after TVDD is powered up. The power up sequence between AVDD and TVDD or AVDD and VDD18 is not critical. Note 8. When LDOE pin = “H”, the internal LDO supplies 1.8V (typ). The power up sequences between AVDD and TVDD, AVDD and VDD18 are not critical. * AKM assumes no responsibility for the usage beyond the conditions in this data sheet. 015002211-E-02 2015/08 - 10 - [AK4452] 8. Electrical Characteristics ■ Analog Characteristics (1) AVDD = 5.0V (Ta=25C: TVDD=3.3V, AVDD=5.0V: AVSS= DVSS=0V: VREFH1=AVDD, VREFL1= AVSS: fs=44.1kHz: BICK=64fs: Signal Frequency=1kHz: 24-bit Input Data: RL 2k: measurement bandwidth = 20Hz ~ 20kHz: External Circuit: (Figure 72), unless otherwise specified.) Parameter Min. Typ. Max. Unit Resolution 32 bit Dynamic Characteristics (Note 9) 0dBFS fs=44.1kHz -107 -100 dB THD+N -52 dB BW=20kHz 60dBFS 0dBFS fs=96kHz -104 dB -48 dB BW=40kHz 60dBFS 0dBFS fs=192kHz -104 dB BW=40kHz 60dBFS -48 dB -44 dB BW=80kHz 60dBFS Dynamic Range (60dBFS with A-weighted) (Note 10) 110 115 dB S/N (A-weighted) (Note 11) 110 115 dB Interchannel Isolation (1kHz) 100 110 dB DC Accuracy Interchannel Gain Mismatch 0 0.3 dB Gain Drift (Note 12) 20 ppm/C Output Voltage (Note 13) 2.65 2.8 2.95 Vpp Load Resistance (Note 14) 2 k 30 pF Load Capacitance (Note 14) Power Supplies Power Supply Current Normal operation (PDN pin = “H”) AVDD TVDD (fs = 44.1kHz) TVDD (fs = 96kHz) TVDD (fs = 192kHz) Power down (PDN pin = “L”) AVDD+TVDD - 8 3 5 7 11 4 7 10 mA mA mA mA - 1 100 A (Note 15) 015002211-E-02 2015/08 - 11 - [AK4452] (2) AVDD = 3.3V (Ta=25°C: TVDD=3.3V, AVDD=3.3V: AVSS= DVSS=0V: VREFH1=AVDD, VREFL1= AVSS: fs=44.1kHz: BICK=64fs: Signal Frequency=1kHz: 24-bit Input Data: RL 2k: measurement bandwidth = 20Hz ~ 20kHz: External Circuit: (Figure 72), unless otherwise specified.) Parameter Min. Typ. Max. Unit Resolution 32 bit Dynamic Characteristics (Note 9) 0dBFS fs=44.1kHz dB -93 -86 THD+N -48 BW=20kHz dB 60dBFS 0dBFS fs=96kHz dB -92 -45 BW=40kHz dB 60dBFS 0dBFS fs=192kHz dB -92 -45 BW=40kHz 60dBFS dB -41 BW=80kHz dB 60dBFS Dynamic Range(60dBFS with A-weighted) (Note 10) 106 111 dB S/N (A-weighted) (Note 11) 106 111 dB Inter channel Isolation (1kHz) 100 110 dB DC Accuracy Inter channel Gain Mismatch 0 0.3 dB Gain Drift (Note 12) 20 ppm/°C Output Voltage (Note 13) Vpp 1.66 1.85 2.04 Load Resistance (Note 14) 2 k Load Capacitance (Note 14) 30 pF Power Supplies Power Supply Current Normal operation (PDN pin = “H”) AVDD 6 mA TVDD (fs = 44.1kHz) 3 mA TVDD (fs = 96kHz) 5 mA TVDD (fs = 192kHz) 7 mA Power down (PDN pin = “L”) (Note 15) AVDD+TVDD 1 100 A Note 9. Measured by Audio Precision, System Two. Averaging mode. Note 10. Figure 72 External LPF Circuit Example 1. 100dB for 16-bit data. Note 11. Figure 72 External LPF Circuit Example 1. S/N does not depend on input data size. Note 12. The voltage on (VREFH1 VREFL1) is held +5V externally. Note 13. The full scale voltage when applying a 1kHz sine wave (0dB) in PCM mode, or when applying a 1kHz sine wave (25~75% duty) in DSD mode. Output voltage scales with the voltage of (VREFH1 VREFL1). DAC: AOUT (typ.@0dB) = (AOUT+) (AOUT) = 2.8Vpp (VREFH1 VREFL1)/5 Note 14. Regarding Load Resistance, AC load is 2k (min) with a DC cut capacitor (Figure 72). DC load is 2 k (min) without a DC cut capacitor (Figure 72). The load resistance value is with respect to ground. Analog characteristics are sensitive to capacitive load that is connected to the output pin. Therefore the capacitive load must be minimized. Note 15. In the power down mode. All other digital input pins including clock pins (MCLK, BICK and LRCK) are held DVSS. 015002211-E-02 2015/08 - 12 - [AK4452] ■ Sharp Roll-Off Filter Characteristics Sharp Roll-Off Filter Characteristics (fs= 44.1kHz) (Ta=-40 105C; AVDD=3.0 5.5V, TVDD=1.7 3.6V; Normal Speed Mode; DEM=OFF, SLOW bit = “0”, SD bit=“0”) Parameter Symbol Min. Typ. Max. Digital Filter 0.05dB PB 0 20.0 Pass band (Note 16) 3.0dB PB 21.5 Pass band Ripple (Note 17) PR -0.0032 0.0032 Stop band (Note 16) SB 24.1 Stop band Attenuation (Note 19) SA 80 Group Delay (Note 18) 26.8 GD Frequency Response (Note 19) 0.07dB 0 20.0 Digital Filter + SCF (Note 19) Frequency Response: 0 20.0kHz -0.2 0.1 Unit kHz kHz dB kHz dB 1/fs kHz dB Sharp Roll-Off Filter Characteristics (fs= 96kHz) (Ta=-40 105C; AVDD=3.0 5.5V, TVDD=1.7 3.6V; Double Speed Mode; DEM=OFF, SLOW bit = “0”, SD bit=“0”) Parameter Symbol Unit Min. Typ. Max. Digital Filter 0.05dB PB 0 43.5 kHz Pass band (Note 16) 3.0dB PB 46.8 kHz Pass band Ripple (Note 17) PR -0.0032 0.0032 dB Stop band (Note 16) SB 52.5 0 43.5 Stop band Attenuation (Note 19) SA 80 dB Group Delay (Note 18) GD 26.8 1/fs Frequency Response (Note 19) 0.07dB 0 43.5 kHz Digital Filter + SCF (Note 19) Frequency Response: 0 40.0kHz -0.3 0.1 dB Sharp Roll-Off Filter Characteristics (fs= 192kHz) (Ta=-40 105C; AVDD=3.0 5.5V, TVDD=1.7 3.6V; Quad Speed Mode; DEM=OFF, SLOW bit = “0”, SD bit=“0”) Parameter Symbol Min. Typ. Max. Unit Digital Filter 0.05dB PB 0 87.0 kHz Pass band (Note 16) 3.0dB PB 93.6 kHz Pass band Ripple (Note 17) PR -0.0032 0.0032 dB Stop band (Note 16) SB 105 kHz Stop band Attenuation (Note 19) SA 80 dB Group Delay (Note 18) 26.8 GD 1/fs Frequency Response (Note 19) 0.07dB 0 87.0 kHz Digital Filter + SCF (Note 19) Frequency Response: 0 80.0kHz -1 0.1 dB Note 16. The pass band and stop band frequencies scale with fs. For example, PB=0.4535×fs, SB=0.546×fs. Note 17. It is the pass band gain amplitude of the double over sampling filter at the first step of the Interpolator. Note 18. The calculating delay time which occurred by digital filtering. This time is from setting the 16/20/24/32bit data of both channels to input register to the output of analog signal. Note 19. The output level is assumed as 0dB when inputting a 1kHz 0dB sine wave. *Digital filter characteristics are based on simulation results. 015002211-E-02 2015/08 - 13 - [AK4452] ■ Slow Roll-Off Filter Characteristics Slow Roll-Off Filter Characteristics (fs = 44.1kHz) (Ta=-40 105C; AVDD=3.0 5.5V, TVDD=1.7 3.6V; Normal Speed Mode; DEM=OFF; SLOW bit = “1”, SD bit=“0”) Parameter Symbol Min. Typ. Max. Digital Filter 0.05dB PB 0 8.1 Pass band (Note 20) 3.0dB PB 18.2 Pass band Ripple (Note 17) PR -0.043 0.043 Stop band (Note 20) SB 39.2 Stop band Attenuation (Note 19) SA 73 Group Delay (Note 18) 6.3 GD Frequency Response (Note 19) 0.05dB 0 8.1 Digital Filter + SCF (Note 19) Frequency Response: 0 20.0kHz -5 0.1 Unit kHz kHz dB dB 1/fs kHz dB Slow Roll-Off Filter Characteristics (fs = 96kHz) (Ta=-40 105C; AVDD=3.0 5.5V, TVDD=1.7 3.6V; Double Speed Mode; DEM=OFF; SLOW bit = “1”, SD bit=“0”) Parameter Symbol Unit Min. Typ. Max. Digital Filter 0.05dB PB 0 17.7 kHz Pass band (Note 20) 3.0dB PB 39.5 kHz Pass band Ripple (Note 17) PR -0.043 0.043 dB Stop band (Note 20) SB 85.3 Stop band Attenuation (Note 19) SA 73 dB Group Delay (Note 18) GD 6.3 1/fs Frequency Response (Note 19) 0.05dB PB 0 17.7 kHz Digital Filter + SCF (Note 19) Frequency Response: 0 40.0kHz -5 0.1 dB Slow Roll-Off Filter Characteristics (fs = 192kHz) (Ta=-40 105C; AVDD=3.0 5.5V, TVDD=1.7 3.6V; Quad Speed Mode; DEM=OFF; SLOW bit = “1”, SD bit=“0”) Parameter Symbol Unit Min. Typ. Max. Digital Filter 0.05dB PB 0 35.5 kHz Pass band (Note 20) 3.0dB PB 79.0 kHz Pass band Ripple (Note 17) PR -0.043 0.043 dB Stop band (Note 20) SB 171 kHz Stop band Attenuation (Note 19) SA 73 dB Group Delay (Note 18) GD 6.3 1/fs Frequency Response (Note 19) 0.05dB PB 0 35.5 kHz Digital Filter + SCF (Note 19) Frequency Response: 0 80.0kHz -5 0.1 dB Note 20. The pass band and stop band frequencies scale with fs. For example, PB=0.185×fs, SB=0.888×fs. 015002211-E-02 2015/08 - 14 - [AK4452] ■ Short Delay Sharp Roll-Off Filter Characteristics Short Delay Sharp Roll-Off Filter Characteristics (fs= 44.1kHz) (Ta=-40 105C; AVDD=3.0 5.5V, TVDD=1.7 3.6V; Normal Speed Mode; DEM=OFF; SLOW bit = “0”, SD bit=“1”) Parameter Symbol Min. Typ. Max. Digital Filter 0.05dB PB 0 20.0 Pass band (Note 16) 3.0dB PB 21.5 Pass band Ripple (Note 17) PR -0.0031 0.0031 Stop band (Note 16) SB 24.1 Stop band Attenuation (Note 19) SA 80 Group Delay (Note 18) 5.8 GD Frequency Response (Note 19) 0.07dB 0 20.0 Digital Filter + SCF (Note 19) Frequency Response: 0 20.0kHz -0.2 0.1 Unit kHz kHz dB kHz dB 1/fs kHz dB Short Delay Sharp Roll-Off Filter Characteristics (fs= 96kHz) (Ta=-40 105C; AVDD=3.0 5.5V, TVDD=1.7 3.6V; Double Speed Mode; DEM=OFF; SLOW bit = “0”, SD bit=“1”) Parameter Symbol Unit Min. Typ. Max. Digital Filter 0.05dB PB 0 43.5 kHz Pass band (Note 16) 3.0dB PB 46.8 kHz Pass band Ripple (Note 17) PR -0.0031 0.0031 dB Stop band (Note 16) SB 52.5 0 43.5 Stop band Attenuation (Note 19) SA 80 dB Group Delay (Note 18) GD 5.8 1/fs Frequency Response (Note 19) 0.07dB 0 43.5 kHz Digital Filter + SCF (Note 19) Frequency Response: 0 40.0kHz -0.3 0.1 dB Short Delay Sharp Roll-Off Filter Characteristics (fs= 192kHz) (Ta=-40 105C; AVDD=3.0 5.5V, TVDD=1.7 3.6V; Quad Speed Mode; DEM=OFF; SLOW bit = “0”, SD bit=“1”) Parameter Symbol Unit Min. Typ. Max. Digital Filter 0.05dB PB 0 87.0 kHz Pass band (Note 16) 3.0dB 93.6 PB kHz Pass band Ripple (Note 17) PR -0.0031 0.0031 dB Stop band (Note 16) SB 105 kHz Stop band Attenuation (Note 19) SA 80 dB Group Delay (Note 18) 5.8 GD 1/fs Frequency Response (Note 19) 0.07dB 0 87.0 kHz Digital Filter + SCF (Note 19) Frequency Response: 0 80.0kHz -1 0.1 dB 015002211-E-02 2015/08 - 15 - [AK4452] ■ Short Delay Slow Roll-Off Filter Characteristics Short Delay Slow Roll-Off Filter Characteristics (fs= 44.1kHz) (Ta=-40 105C; AVDD=3.0 5.5V, TVDD=1.7 3.6V; Normal Speed Mode; DEM=OFF; SLOW bit = “1”, SD bit=“1”) Parameter Symbol Min. Typ. Max. Digital Filter 0.05dB PB 0 11.1 Pass band (Note 21) 3.0dB PB 19.4 Pass band Ripple (Note 17) PR -0.05 0.05 Stop band (Note 21) SB 38.1 Stop band Attenuation (Note 19) SA 82 Group Delay (Note 18) GD 4.8 Frequency Response (Note 19) 0.05dB 0 11.1 Digital Filter + SCF (Note 19) Frequency Response: 0 20.0kHz -5 0.1 Unit kHz kHz dB kHz dB 1/fs kHz dB Short Delay Slow Roll-Off Filter Characteristics (fs= 96kHz) (Ta=-40 105C; AVDD=3.0 5.5V, TVDD=1.7 3.6V; Double Speed Mode; DEM=OFF; SLOW bit = “1”, SD bit=“1”) Parameter Symbol Unit Min. Typ. Max. Digital Filter 0.05dB PB 0 24.2 kHz Pass band (Note 21) 3.0dB 42.1 PB kHz Pass band Ripple (Note 17) PR -0.05 0.05 dB Stop band (Note 21) SB 83.0 43.5 Stop band Attenuation (Note 19) SA 82 dB Group Delay (Note 18) 4.8 GD 1/fs Frequency Response (Note 19) 0.05dB 0 24.2 kHz Digital Filter + SCF (Note 19) Frequency Response: 0 40.0kHz -5 0.1 dB Short Delay Slow Roll-Off Filter Characteristics (fs= 192kHz) (Ta=-40 105C; AVDD=3.0 5.5V, TVDD=1.7 3.6V; Quad Speed Mode; DEM=OFF; SLOW bit = “1”, SD bit=“1”) Parameter Symbol Unit Min. Typ. Max. Digital Filter 0.05dB PB 0 48.4 kHz Pass band (Note 21) 3.0dB PB 84.3 kHz Pass band Ripple (Note 17) PR -0.05 0.05 dB Stop band (Note 21) SB 165.9 kHz Stop band Attenuation (Note 19) SA 82 dB Group Delay (Note 18) GD 4.8 1/fs Frequency Response (Note 19) 0.05dB 0 48.4 kHz Digital Filter + SCF (Note 19) Frequency Response: 0 80.0kHz -5 0.1 dB Note 21. The pass band and stop band frequencies scale with fs. For example, PB=0.252×fs, SB=0.864×fs. 015002211-E-02 2015/08 - 16 - [AK4452] ■ DSD Mode Characteristics (1) DSDF bit= “0” (Ta=-40 105°C: AVDD=3.0 5.5V, TVDD=1.7 3.6V: fs=44.1kHz: D/P bit= “1”, DSDF bit= “0”) Parameter Min. Typ. Max. Unit Digital Filter Response DSDSEL[1:0] 20kHz -0.8 “00” 50kHz -5.5 dB Frequency 100kHz -19.9 Response 40kHz -0.8 (Note 22) “01”” 200kHz -5.5 dB 400kHz -19.9 80kHz -0.8 “10” 400kHz -5.5 dB 800kHz -19.9 (2) DSDF bit= “1” (Ta=-40 105C: AVDD=3.0 5.5V, TVDD=1.7 3.6V: fs=44.1kHz: D/P bit=“1”, DSDF bit= “1”) Parameter Min. Typ. Max. Unit Digital Filter Response DSDSEL[1:0] 20kHz -0.2 “00” 100kHz -6.3 dB Frequency 200kHz -23.7 Response 40kHz -0.2 (Note 22) “01”” 200kHz -6.3 dB 400kHz -23.7 80kHz -0.2 “10” 400kHz -6.3 dB 800kHz -23.7 Note 22. In DSD mode, the signal level is ranging from 25% to 75%. Peak levels of DSD signal above this duty are not recommended by SACD format book (Scarlet Book). Note 23. It is assumed that the output level is 0dB when the input signal is 1kHz and the duty range is between 25 ~ 75%.The output level is assumed as 0dB when applying a 1kHz sine wave in 25~ 75% duty. *Digital filter characteristics are based on simulation results. ■ DC Characteristics (Ta=-40 105C; AVDD=3.0 5.5V, TVDD=1.7 3.6V) Parameter Symbol TVDD=1.7 3.0V High-Level Input Voltage VIH Low-Level Input Voltage VIL TVDD=3.0V 3.6V High-Level Input Voltage VIH Low-Level Input Voltage VIL High-Level Output Voltage (TDMO1, DZF pins: Iout=-100µA) VOH Low-Level Output Voltage (excpt SDA pin : Iout= 100µA) VOL (SDA pin, 2.0V TVDD 3.6V: Iout= 3mA) VOL (SDA pin, 1.7V TVDD 2.0V: Iout= 3mA) VOL Input Leakage Current Iin 015002211-E-02 Min. Typ. Max. Unit 80%TVDD - - 20%TVDD V V 70%TVDD - - 30%TVDD V V TVDD0.5 - - V - - 0.5 0.4 20%TVDD 10 V V V A - 2015/08 - 17 - [AK4452] ■ Switching Characteristics (Ta=-40 105°C: AVDD=3.0 5.5V, TVDD=1.7 3.6V, CL=20pF) Parameter Symbol Min. Master Clock Timing 2.048 Frequency fCLK 45 Duty Cycle dCLK Minimum Pulse Width 9.155 tCLKH tCLKL 9.155 LRCK Frequency (Note 24) Normal Mode (TDM1-0 bits = “00”) Normal Speed Mode fsn 8 Double Speed Mode fsd 54 Quad Speed Mode fsq 108 Oct speed mode fso Hex speed mode fsh Duty Cycle Duty 45 TDM128 mode (TDM1-0 bits = “01”) Normal Speed Mode fsn 8 Double Speed Mode fsd 54 Quad Speed Mode fsq 108 High time tLRH 1/128fs Low time tLRL 1/128fs TDM256 mode (TDM1-0 bits = “10”) Normal Speed Mode High time fsn 8 Double Speed Mode fsd 54 High time tLRH 1/256fs Low time tLRL 1/256fs TDM512 mode (TDM1-0 bits = “11”) Normal Speed Mode fsn 8 High time tLRH 1/512fs Low time tLRL 1/512fs PCM Audio Interface Timing Normal Mode (TDM1-0 bits = “00”) BICK Period Normal Speed Mode tBCK 1/256fsn Double Speed Mode tBCK 1/128fsd Quad Speed Mode tBCK 1/64fsq Oct speed mode tBCK 1/64fso Hex speed mode tBCK 1/64fsh BICK Pulse Width Low tBCKL 9 BICK Pulse Width High tBCKH 9 BICK “” to LRCK Edge (Note 25) tBLR 5 tLRB 5 LRCK Edge to BICK “” (Note 25) tSDH 5 SDTI1 Hold Time tSDS 5 SDTI1 Setup Time 015002211-E-02 Typ. Max. Unit 49.152 55 MHz % ns ns 54 108 216 kHz kHz kHz kHz kHz % 384 768 55 54 108 216 kHz kHz kHz nsec ns 54 108 kHz kHz nsec nsec 54 kHz nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec 2015/08 - 18 - [AK4452] Parameter TDM128 mode (TDM1-0 bits = “01”) BICK Period Normal Speed Mode Double Speed Mode Quad Speed Mode BICK Pulse Width Low BICK Pulse Width High BICK “” to LRCK Edge (Note 25) LRCK Edge to BICK “” (Note 25) SDTI1 Hold Time SDTI1 Setup Time TDM256 mode (TDM1-0 bits = “10”) BICK Period Normal Speed Mode Double Speed Mode (Note 26) BICK Pulse Width Low BICK Pulse Width High BICK “” to LRCK Edge (Note 25) LRCK Edge to BICK “” (Note 25) TDMO1 Setup time BICK “” TDMO1 Hold time BICK “”(Note 28) SDTI1 Hold Time SDTI1 Setup Time TDM512 mode (TDM1-0 bits = “11”) BICK Period Normal Speed Mode (Note 27) BICK Pulse Width Low BICK Pulse Width High BICK “” to LRCK Edge (Note 25) LRCK Edge to BICK “” (Note 25) TDMO1 Setup time BICK “” TDMO1 Hold time BICK “” (Note 28) SDTI1 Hold Time SDTI1 Setup Time Symbol Min. tBCK tBCK tBCK tBCKL tBCKH tBLR tLRB tSDH tSDS 1/128fsn 1/128fsd 1/128fsq 14 14 14 14 5 5 nsec nsec nsec nsec nsec nsec nsec nsec nsec tBCK tBCK tBCKL tBCKH tBLR tLRB tBSS tBSH tSDH tSDS 1/256fsn 1/256fsd 14 14 14 14 5 5 5 5 nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec tBCK tBCKL tBCKH tBLR tLRB tBSS tBSH tSDH tSDS 1/512fsn 14 14 14 14 5 5 5 5 nsec nsec nsec nsec nsec nsec nsec nsec nsec 015002211-E-02 Typ. Max. Unit 2015/08 - 19 - [AK4452] Parameter DSD Audio Interface Timing (64 mode, DSDSEL 1-0 bits = “00”) DCLK Period DCLK Pulse Width Low DCLK Pulse Width High DCLK Edge to DSDL/R (Note 29) (128 mode, DSDSEL 1-0 bits = “01”) DCLK Period DCLK Pulse Width Low DCLK Pulse Width High DCLK Edge to DSDL/R (Note 29) Symbol Min. tDCK tDCKL tDCKH tDDD 144 144 20 tDCK tDCKL tDCKH tDDD 72 72 10 Typ. Max. Unit 20 nsec nsec nsec nsec 10 nsec nsec nsec nsec 1/64fs 1/128fs (256 mode, DSDSEL 1-0 bits = “10”) DCLK Period tDCK 1/256fs nsec DCLK Pulse Width Low tDCKL 36 nsec DCLK Pulse Width High tDCKH 36 nsec DCLK Edge to DSDL/R (Note 29) tDDD 5 5 nsec Note 24. When the 1152fs, 512fs or 768fs /256fs or 384fs /128fs or 192fs are switched, the AK4452 should be reset by the PDN pin or RSTN bit. Note 25. BICK rising edge must not occur at the same time as LRCK edge. Note 26. fsd (max) = 96kHz when TVDD < 3.0V in Daisy Chain mode. Note 27. fsn (max) = 48kHz when TVDD < 3.0V in Daisy Chain mode. Note 28. tBSH (min) = 4 nsec when TVDD > 2.6V and the LDOE pin = “L”. Note 29. DSD data transmitting device must meet this time. tDDD is defined from a falling edge of DCLK “↓” to a DSDL/R edge when DCKB bit = “0” and it is defined from a rising edge of DCLK “↑” to a DSDL/R edge when DCKB bit = “1” 015002211-E-02 2015/08 - 20 - [AK4452] (Ta=-40 105°C: AVDD=3.0 5.5V, TVDD=1.7 3.6V) Parameter Symbol Min. Typ. Control Interface Timing (3-wire Serial mode): CCLK Period 200 tCCK CCLK Pulse Width Low 80 tCCKL Pulse Width High 80 tCCKH CDTI Setup Time 40 tCDS CDTI Hold Time 40 tCDH CSN “H” Time 150 tCSW 50 CSN “” to CCLK “” tCSS 50 tCSH CCLK “” to CSN “” Control Interface Timing (I2C Bus mode): SCL Clock Frequency fSCL Bus Free Time Between Transmissions tBUF 1.3 Start Condition Hold Time (prior to first clock pulse) tHD:STA 0.6 Clock Low Time tLOW 1.3 Clock High Time tHIGH 0.6 Setup Time for Repeated Start Condition tSU:STA 0.6 SDA Hold Time from SCL Falling (Note 30) tHD:DAT 0 SDA Setup Time from SCL Rising tSU:DAT 0.1 Rise Time of Both SDA and SCL Lines tR Fall Time of Both SDA and SCL Lines tF Setup Time for Stop Condition tSU:STO 0.6 Pulse Width of Spike Noise Suppressed by Input Filter tSP 0 Capacitive load on bus Cb Power-down & Reset Timing (Note 31) PDN Accept Pulse Width tAPD 150 PDN Reject Pulse Width tRPD Note 30. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. Note 31.The AK4452 can be reset by bringing the PDN pin to “L”. Note 32. I2C is a trademark of NXP B.V. 015002211-E-02 Max. Unit nsec nsec nsec nsec nsec nsec nsec nsec 400 1.0 0.3 50 400 kHz sec sec sec sec sec sec sec sec sec nsec pF 30 nsec nsec 2015/08 - 21 - [AK4452] ■ Timing Diagram 1/fCLK VIH MCLK VIL tCLKH tCLKL dCLK=tCLKH x fCLK, tCLKL x fCLK 1/fs VIH LRCK VIL tLRH tLRL Duty=tLRH x fs, tLRL x fs tBCK VIH BICK VIL tBCKH tBCKL Figure 2. Clock Timing VIH LRCK VIL tBLR tLRB VIH BICK VIL tBSS tBSH TDMO 50%TVDD tSDS tSDH VIH SDTI VIL Figure 3. Audio Interface Timing (PCM Mode) 015002211-E-02 2015/08 - 22 - [AK4452] tDCK tDCKL tDCKH VIH DCLK VIL tDDD VIH DSDL1 DSDR1 VIL tDDD VIH DSDL1 DSDR1 VIL Figure 4. Audio Serial Interface Timing (DSD Normal Mode, DCKB bit = “0”) tDCK tDCKL tDCKH VIH DCLK VIL tDDD tDDD VIH DSDL1 DSDR1 VIL tDDD tDDD VIH DSDL1 DSDR1 VIL Figure 5. Audio Serial Interface Timing (DSD Phase Modulation Mode, DCKB bit = “0”) 015002211-E-02 2015/08 - 23 - [AK4452] VIH CSN VIL tCSS tCCKL tCCKH VIH CCLK VIL tCDS CDTI C1 tCDH C0 R/W VIH A4 VIL Figure 6. WRITE Command Input Timing (3-wire Serial Mode) tCSW VIH CSN VIL tCSH VIH CCLK CDTI VIL D3 D2 D1 D0 VIH VIL Figure 7. WRITE Data Input Timing (3-wire Serial Mode) 015002211-E-02 2015/08 - 24 - [AK4452] VIH SDA VIL tLOW tBUF tR tHIGH tF tSP VIH SCL VIL tHD:STA Stop tHD:DAT Start tSU:DAT tSU:STA tSU:STO Start Stop Figure 8. I2C Bus mode Timing tAPD tRPD PDN VIL Figure 9. Power-down & Reset Timing 015002211-E-02 2015/08 - 25 - [AK4452] 9. Functional Descriptions ■ D/A Conversion Mode (PCM mode, DSD mode) The AK4452 can perform D/A conversion for either PCM data or DSD data. The DP bit controls PCM/DSD mode. When DSD mode, DSD data can be input from DCLK, DSDL and DSDR pins. When PCM mode, PCM data can be input from BICK, LRCK and SDTI pins. When PCM/DSD mode is changed by DP bit, the AK4452 should be reset by RSTN bit. It takes about 2/fs to 3/fs to change the mode. Only PCM data is supported in parallel mode. DP bit Interface 0 PCM 1 DSD Table 1. PCM/DSD Mode Control ■ System Clock [1] PCM Mode The external clocks, which are required to operate the AK4452, are MCLK, BICK and LRCK. MCLK should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the delta - sigma modulator. There are two methods to set MCLK frequency. In Manual Setting Mode (ACKS bit= “0”: Default), the sampling speed is set by the DFS0, DFS1 (Table 2) bits. The frequency of MCLK at each sampling speed is set automatically. When reset is released (PDN pin = “↑”), the AK4452 is in Manual Setting Mode. In Auto Setting Mode (ACKS bit= “1”), as MCLK frequency is detected automatically (Table 5) and the internal master clock attains the appropriate frequency (Table 6, Table 7), so it is not necessary to set DFS bits. 015002211-E-02 2015/08 - 26 - [AK4452] 1. Manual Setting Mode (ACKS bit = “0”) MCLK frequency is detected automatically and the sampling rate is set by DFS2-0 bits (Table 2). The MCLK frequency corresponding to each sampling speed should be provided externally (Table 3, Table 4). The AK4452 is set to Manual Setting Mode at power-up (PDN pin = “L” →“H”). When DFS2-0 bits are changed, the AK4452 should be reset by RSTN bit. DFS2 0 0 DFS1 0 0 DFS0 0 1 0 1 0 0 1 1 1 1 1 0 0 1 1 LRCK Fs 32.0kHz 44.1kHz 48.0kHz 88.2kHz 96.0kHz 176.4kHz 192.0kHz 384kHz 768kHz LRCK fs 32.0kHz 44.1kHz 48.0kHz 88.2kHz 96.0kHz 176.4kHz 192.0kHz 384kHz 768kHz Sampling Rate (fs) Normal Speed Mode 8kHz 54kHz Double Speed Mode 54kHz 108kHz Quad Speed Mode (default) 120kHz 216kHz 1 Reserved (*) 0 Oct Speed Mode 384kHz 1 Hex Speed Mode 768kHz 0 Reserved (* Shift to 384kHz) 1 Reserved (* Shift to 768kHz) Table 2. Sampling Speed (Manual Setting Mode) MCLK(MHz) 16fs 32fs 48fs 64fs 96fs 128fs N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 22.5792 N/A N/A N/A N/A N/A 24.5760 N/A 12.288 18.432 24.576 36.864 49.152 12.288 24.576 36.864 49.152 N/A N/A Table 3. System Clock Example (Manual Setting Mode) Sampling Speed Normal Double Quad Quad Oct Hex MCLK(MHz) 192fs 256fs 384fs 512fs 768fs 1024fs 1152fs N/A 8.1920 12.2880 16.3840 24.5760 36.8640 36.8640 N/A 11.2896 16.9344 22.5792 33.8688 N/A N/A N/A 12.2880 18.4320 24.5760 36.8640 N/A N/A N/A 22.5792 33.8688 45.1584 N/A N/A N/A N/A 24.5760 36.8640 49.152 N/A N/A N/A 33.8688 45.1584 N/A N/A N/A N/A N/A 36.8640 49.152 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Table 4. System Clock Example (Manual Setting Mode) 015002211-E-02 Sampling Speed Normal Double Quad Quad Oct Hex 2015/08 - 27 - [AK4452] 2. Auto Setting Mode (ACKS bit = “1”) MCLK frequency and the sampling speed are detected automatically (Table 5) and DFS2-0 bits are ignored. The MCLK frequency corresponding to each sampling speed should be provided externally (Table 6, Table 7). MCLK Sampling Speed 1152fs Normal (fs32kHz) 512fs/256fs 768fs/384fs Normal 256fs 384fs Double 128fs 192fs Quad 64fs 96fs Oct 32fs 48fs Hex Table 5. Sampling Speed (Auto Setting Mode) LRCK fs 32.0kHz 44.1kHz 48.0kHz 88.2kHz 96.0kHz 176.4kHz 192.0kHz 384kHz 768kHz MCLK (MHz) 32fs 48fs 64fs 96fs 128fs N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 22.5792 N/A N/A N/A N/A 24.5760 N/A N/A 24.576 36.864 N/A 24.576 36.864 N/A N/A N/A Table 6. System Clock Example (Auto Setting Mode) LRCK fs 32.0kHz 44.1kHz 48.0kHz 88.2kHz 96.0kHz 176.4kHz 192.0kHz 384kHz 768kHz MCLK (MHz) 192fs 256fs 384fs 512fs 768fs N/A 8.1920 12.2880 16.3840 24.5760 N/A 11.2896 16.9344 22.5792 33.8688 N/A 12.2880 18.4320 24.5760 36.8640 N/A 22.5792 33.8688 N/A N/A N/A 24.5760 36.8640 N/A N/A 33.8688 N/A N/A N/A N/A 36.8640 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Table 7. System Clock Example (Auto Setting Mode) Sampling Speed Normal 1152fs 36.8640 N/A N/A N/A N/A N/A N/A N/A N/A Double Quad Quad Oct Hex Sampling Speed Normal Double Quad Quad Oct Hex MCLK= 256fs/384fs supports sampling rate of 8kHz~96kHz (Table 8). However, when the sampling rate is 8kHz~48kHz, DR and S/N will degrade by approximately 3dB as compared to when MCLK= 512fs/768fs. ACKS pin MCLK DR,S/N L 256fs/384fs/512fs/768fs 115dB H 256fs/384fs 112dB H 512fs/768fs 115dB Table 8. Relationship of DR, S/N and MCLK frequency (fs = 44.1kHz) 015002211-E-02 2015/08 - 28 - [AK4452] [2] DSD mode (Serial Control mode only) The AK4452 is capable to playback DSD data. The external clocks, which are required to operate the AK4452, are MCLK and DCLK. MCLK should be synchronized with DCLK but the phase is not critical. The frequency of MCLK is set by DCKS bit. (Table 9) After exiting reset (PDN pin = “L” → “H”, RSTN bit= “0” → “1”) upon power-up, the AK4452 is in power-down state until MCLK and DCLK are input. DCKS bit 0 1 MCLK Frequency DCLK Frequency 512fs 64fs/128fs/256fs 768fs 64fs/128fs/256fs Table 9. System Clock (DSD Mode) (default) The AK4452 supports 64fs, 128fs and 256fs data stream (fs= 32kHz, 44.1kHz, 48kHz). DSDSEL1-0 bits control this setting. (Table 10) DSDSEL1 DSDSEL0 0 0 1 0 1 0 1 1 DSD data stream fs=32kHz fs=44.1kHz 2.048MHz 2.8224MHz 4.096MHz 5.6448MHz 8.192MHz 11.2896MHz Reserved Reserved (8.192MHz) (11.2896MHz) Table 10. DSD Data Stream Select fs=48kHz 3.072MHz 6.144MHz 12.288MHz Reserved (12.288MHz) (default) DSDD bit selects DSD playback mode (Table 11). When DSDD bit= “1”, the output volume control is not available and the cut off filter value is fixed to 100kHz. DSDD bit Mode 0 Full function (default) 1 Volume pass Table 11. DSD Playback Mode Select The cut off filter characteristic in DSD mode can be selected by DSDF bit. (Table 12) DSDF bit Cut Off Filter 0 50kHz (default) 1 100kHz Table 12. DSD Filter Select 015002211-E-02 2015/08 - 29 - [AK4452] ■ Audio Interface Format The AK4452 supports both PCM and DSD formats for digital input signal. Mode settings are available by the pins (TDM1-0 pins, DIF pin and DCHAIN pin) and registers (TDM1-0 bits, DIF2-0 bits, SDS2-0 bits and DCHAIN bit). The RSTN bit should be toggled in case these format setting bits are changed during operation. [1] PCM Mode Normal Mode (TDM1-0 bits=“00”) Two channels audio data is shifted in via the SDTI1 pin using BICK and LRCK inputs. Eight data formats are supported and selected by the DIF2-0 bits as shown in Table 13. In all formats the serial data is MSB first, 2's compliment format and is latched on the rising edge of BICK. Mode 2 can be used in 16-bit and 20-bit MSB justified and Mode 6 can be used in 16-bit, 20-bit and 24-bit MSB justified formats by zeroing the unused LSBs. TDM128 Mode (TDM1-0 bits=“01”) Four channels audio data is shifted in via the SDTI1 pin using BICK and LRCK inputs. Data is selected by SDS2-0 bits. BICK is fixed to 128fs. Six data formats are supported and selected by the DIF2-0 bits as shown in Table 13. In all formats the serial data is MSB first, 2's compliment format and is latched on the rising edge of BICK. TDM256 Mode (TDM1-0 bits=“10”) Eight channels audio data is shifted in via the SDTI1 pin using BICK and LRCK inputs. Data is selected by SDS2-0 bits. BICK is fixed to 256fs. Six data formats are supported and selected by the DIF2-0 bits as shown in Table 13. In all formats the serial data is MSB first, 2's compliment format and is latched on the rising edge of BICK. TDM512 Mode (TDM1-0 bits=“11”) Sixteen channels audio data is shifted in via the SDTI1 pin using BICK and LRCK inputs. Data is selected by SDS2-0 bits. BICK is fixed to 512fs. Six data formats are supported and selected by the DIF2-0 bits as shown in Table 13. In all formats the serial data is MSB first, 2's compliment format and is latched on the rising edge of BICK. 015002211-E-02 2015/08 - 30 - [AK4452] Mode 0 1 2 3 4 5 6 7 Normal (Note 33) TDM128 TDM256 TDM512 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 TDM1 TDM0 0 0 0 1 1 0 1 1 DIF2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 DIF1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 DIF0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 SDTI Format LRCK BICK 16-bit LSB justified H/L 32fs 20-bit LSB justified H/L 40fs 24-bit MSB justified H/L 48fs 2 24-bit I S compatible L/H 48fs 24-bit LSB justified H/L 48fs 32-bit LSB justified H/L 64fs 32-bit MSB justified H/L 64fs 32-bit I2S compatible L/H 64fs N/A 128fs N/A 128fs 24-bit MSB justified 128fs 24-bit I2S compatible 128fs 24-bit LSB justified 128fs 32-bit LSB justified 128fs 32-bit MSB justified 128fs 32-bit I2S compatible 128fs N/A 256fs N/A 256fs 24-bit MSB justified 256fs 24-bit I2S compatible 256fs 24-bit LSB justified 256fs 32-bit LSB justified 256fs 32-bit MSB justified 256fs 32-bit I2S compatible 256fs N/A 512fs N/A 512fs 24-bit MSB justified 512fs 24-bit I2S compatible 512fs 24-bit LSB justified 512fs 32-bit LSB justified 512fs 32-bit MSB justified 512fs 32-bit I2S compatible 512fs (Shaded settings are not available) Table 13. Audio Interface Format Note 33. BICK that is input to each channel must be longer than the bit length of setting format. 015002211-E-02 2015/08 - 31 - [AK4452] LRCK 0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1 BICK (32fs) SDTI1 Mode 0 15 14 6 5 1 0 4 14 3 15 2 16 1 17 0 31 15 14 0 6 5 14 1 4 3 15 2 16 1 17 0 31 15 14 0 1 BICK (64fs) SDTI1 Mode 0 Don’t care 15 14 0 Don’t care 15 14 0 15:MSB, 0:LSB Lch Data Rch Data Figure 10. Mode 0 Timing LRCK 0 1 8 9 10 11 12 31 0 1 8 9 10 11 12 31 0 1 0 1 BICK (64fs) SDTI1 Mode 1 Don’t care 19 0 Don’t care 19 0 Don’t care 19 0 19 0 19:MSB, 0:LSB SDTI1 Mode 4 Don’t care 23 22 21 20 23 22 20 21 23:MSB, 0:LSB Lch Data Rch Data Figure 11. Mode 1/4 Timing LRCK 0 1 2 22 23 24 30 31 0 1 2 22 23 24 30 31 BICK (64fs) SDTI1 23 22 1 0 Don’t care 23 22 1 0 Don’t care 23 22 23:MSB, 0:LSB Lch Data Rch Data Figure 12. Mode 2 Timing 015002211-E-02 2015/08 - 32 - [AK4452] LRCK 0 1 2 3 23 24 25 31 0 1 2 3 23 24 25 31 0 1 BICK (64fs) SDTI1 23 0 1 22 Don’t care 23 22 0 1 23 Don’t care 23:MSB, 0:LSB Lch Data Rch Data Figure 13. Mode 3 Timing LRCK 0 1 2 22 23 24 30 31 0 1 2 22 23 24 30 31 0 1 BICK (64fs) SDTI1 Mode 5,6 31 30 1 0 31 30 0 1 31 30 32:MSB, 0:LSB Lch Data Rch Data Figure 14. Mode 5/6 Timing LRCK 0 1 2 3 23 24 25 31 0 1 0 31 2 3 23 24 25 31 0 1 0 31 BICK (64fs) SDTI1 31 30 1 30 1 30 32:MSB, 0:LSB Lch Data Rch Data Figure 15. Mode 7 Timing 015002211-E-02 2015/08 - 33 - [AK4452] 128 BICK LRCK BICK(128fs) SDTI1 Mode8 23 22 SDTI1 Mode11,12 31 30 0 23 22 0 0 31 30 23 22 23 22 0 0 31 30 0 0 31 30 23 22 0 31 30 2 L1 R1 L2 R2 32 BICK 32 BICK 32 BICK 32 BICK Figure 16. Mode 8/11/12 Timing 128 BICK LRCK BICK(128fs) SDTI1 Mode9 23 22 SDTI1 Mode13 31 30 0 0 23 22 0 23 22 0 31 30 23 22 0 31 30 L1 R1 32 BICK 32 BICK 23 0 0 31 30 2 0 31 30 L2 R2 32 BICK 32 BICK Figure 17. Mode 9/13 Timing 128 BICK LRCK BICK(128fs) SDTI1 23 22 0 23 22 0 23 22 0 0 23 22 L1 R1 L2 R2 32 BICK 32 BICK 32 BICK 32 BICK 23 Figure 18. Mode 10 Timing 015002211-E-02 2015/08 - 34 - [AK4452] 256 BICK LRCK BICK (256fs) SDTI1 Mode14 SDTI1 Mode17,18 23 22 0 31 30 23 22 0 23 22 0 31 30 0 0 31 30 23 22 0 0 31 30 23 22 0 0 31 30 23 22 0 0 31 30 23 22 0 0 31 30 23 22 0 0 31 30 23 22 0 31 30 L1 R1 L2 R2 L3 R3 L4 R4 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 23 23 Figure 19. Mode 14/17/18 Timing 256 BICK LRCK BICK (256fs) SDTI1 Mode15 SDTI1 Mode19 23 0 23 31 30 0 23 0 31 30 0 23 0 31 30 0 23 0 31 30 0 23 0 31 30 0 0 31 30 0 0 31 30 0 0 31 30 23 0 31 L1 R1 L2 R2 L3 R3 L4 R4 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK Figure 20. Mode 15/19 Timing 256 BICK LRCK BICK(256fs) SDTI1 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 L1 R1 L2 R2 L3 R3 L4 R4 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 0 23 Figure 21. Mode 16 Timing 015002211-E-02 2015/08 - 35 - [AK4452] 512BICK LRCK BICK(512fs) SDTI1 Mode8 SDTI1 Mode11,12 23 22 0 23 22 0 23 22 23 22 0 0 23 22 0 23 22 0 23 22 0 23 22 23 0 2 31 22 0 31 22 0 31 22 R1 L1 0 31 22 0 31 22 R2 L2 0 31 22 0 31 22 R3 L3 0 31 22 31 0 R4 L4 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK Figure 22. Mode 20/23/24 Timing 512BICK LRCK BICK(512fs) SDTI1 Mode21 SDTI1 Mode25 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 23 0 2 31 22 0 31 22 0 31 22 R1 L1 0 31 22 0 31 22 R2 L2 0 31 22 0 31 22 R3 L3 0 31 22 31 0 R4 L4 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK Figure 23. Mode 21/25 Timing 512BICK LRCK BICK(512fs) SDTI1 Mode22 23 22 L1 0 23 22 2 R1 0 23 22 L2 0 23 22 R2 0 23 22 L3 0 23 22 R3 0 23 22 L4 0 23 22 23 0 R4 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK Figure 24. Mode 22 Timing 015002211-E-02 2015/08 - 36 - [AK4452] [1]-1. Data Select One data cycle of SDTI1 for each format are defined as below. SDS2-0 bits control playback channel of each DAC. LRCK L1 SDTI1 R1 Figure 25. Data Slot in Normal Mode 128 BICK LRCK L1 SDTI1 R1 L2 R2 Figure 26. Data Slot in TDM128 Mode 256 BICK LRCK SDTI1 L1 R1 L2 R2 L3 R3 L4 R4 Figure 27. Data Slot in TDM256 Mode 512 BICK LRCK SDTI1 L1 R1 L2 R2 L3 R3 L4 R4 L5 R5 L6 R6 L7 R7 L8 R8 Figure 28. Data Slot in TDM512 Mode 015002211-E-02 2015/08 - 37 - [AK4452] SDS2 SDS1 SDS0 * * * * 0 0 * 0 1 DAC Lch Rch L1 R1 L1 R1 L2 R2 0 0 0 0 0 0 1 1 0 1 0 1 L1 L2 L3 L4 R1 R2 R3 R4 0 0 0 0 TDM512 1 1 1 1 (*: Do not care) 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 L1 L2 L3 L4 L5 L6 L7 L8 R1 R2 R3 R4 R5 R6 R7 R8 Normal TDM128 TDM256 Table 14. Data Select 015002211-E-02 2015/08 - 38 - [AK4452] [1]-2. Daisy Chain AK4452 is available for Daisy Chain structure. Set DCHAIN bit to “1” or DCHAIN pin to “H” to enable Daisy Chain mode. Daisy Chain supports TDM512/256 mode. (1)TDM512 mode Figure 29 shows example of TDM512 mode Daisy Chain structure (TDM1-0 bits= “11” ). 16ch data is input to the second AK4452’s SDTI1 pin from a DSP. Connect the second AK4452’s TDMO1 pin to the first AK4452’s SDTI1 pin. Figure 30 shows data I/O example of TDM512 mode. SDTI1 (L8, R8) data is the input for the DAC of the second AK4452, and the second AK4452 outputs the data from TDMO1 by shifting 2ch. The first AK4452 accepts SDTI1 (L7, R7) data as input data of DAC. DIF2-0 bits setting of both first AK4452 and the second AK4452 must be the same. TDMO1 SDTI1 TDMO1 SDTI1 Second AK4452 First AK4452 DSP Figure 29. Daisy Chain (TDM512/256 Mode) 512 BICK LRCK SDTI1 L1 R1 L2 R2 L3 R3 L4 R4 L5 R5 L6 R6 L7 R7 L8 R8 Second AK4452 TDMO1 L1 R1 L2 R2 L3 R3 L4 R4 L5 R5 L6 R6 L7 R7 First AK4452 Figure 30. Daisy Chain (TDM512 Mode) 015002211-E-02 2015/08 - 39 - [AK4452] (2)TDM256 mode Figure 29 shows example of TDM256 mode Daisy Chain structure (TDM1-0 bits= “10” ). 8ch data is input to the second AK4452’s SDTI1 pin from a DSP. Connect the second AK4452’s TDMO1 pin to the first AK4452’s SDTI1 pin. Figure 31 shows data I/O example of TDM256 mode. SDTI1 (L4, R4) data is the input for the DAC of the second AK4452, and the second AK4452 outputs the data from TDMO1 by shifting 2ch. The first AK4452 accepts SDTI1 (L3, R3) data as input data of DAC. DIF2-0 bits setting of both first AK4452 and the second AK4452 must be the same. 256 BICK LRCK SDTI1 L1 R1 L2 R2 L3 R3 L4 R4 Second AK4452 TDMO1 L1 L2 R1 R2 L3 R3 First AK4452 Figure 31. Daisy Chain (TDM256 Mode) 015002211-E-02 2015/08 - 40 - [AK4452] [2] DSD Mode 2ch Data is shifted in via the DSDL1 and DSDR1 pins using DCLK inputs. DSD data is supported by both Normal mode (Figure 32) and Phase Modulation mode (Figure 33). Input data is clocked in on a rising or falling edge of DCLK that is set by DCKB bit. The frequency of DCLK is variable at 64fs, 128fs and 256fs by setting DSDSEL1-0 bits. DCLK (DCKB bit=”0”) DSDL,DSDR D0 D1 D2 D3 Figure 32. DSD Mode Timing (Normal Mode) DCLK (DCKB bit=”0”) DSDL,DSDR D0 D1 D1 D2 D2 D3 Figure 33. DSD Mode Timing (Phase Modulation Mode) 015002211-E-02 2015/08 - 41 - [AK4452] ■ D/A Conversion Mode (PCM Mode, DSD Mode) Switching Timing RSTN bit 5/fs D/A Mode PCM Mode DSD Mode 0 D/A Data PCM Data DSD Data Figure 34. D/A Mode Switching Timing (PCM to DSD) RSTN bit D/A Mode DSD Mode PCM Mode 5/fs D/A Data DSD Data PCM Data Figure 35. D/A Mode Switching Timing (DSD to PCM) Note 34. The signal range is defined as 25% ~ 75% duty ratios in DSD mode. DSD signal must not go beyond this duty range at the SACD format book (Scarlet Book). 015002211-E-02 2015/08 - 42 - [AK4452] ■ Digital Filter (PCM mode) Four digital filters are available for playback, providing a choice of different sound colors. These digital filters are selected by SD bit, SLOW bit and SSLOW bit. SSLOW 0 0 0 0 1 SD bit 0 0 1 1 * SLOW bit Mode 0 Sharp roll-off filter 1 Slow roll-off filter 0 Short delay Sharp roll-off filter 1 Short delay Slow roll-off filter * Super Slow Roll-off Mode Table 15. Digital Filter Setting (*: don’t care) (default) The slowest frequency characteristics setting is when SSLOW bit = “1”. ■ De-emphasis Filter (PCM mode) A digital de-emphasis filter is available for 32kHz, 44.1kHz or 48kHz sampling rates (tc = 50/15µs) and is enabled or disabled with DEM11-10 bits (DEM bits). DEM11-10 bits control de-emphasis mode of DAC. DEM bits settings are invalid in DSD mode. This mode is only valid in PCM Normal Speed Mode. DEM11 DEM10 Mode 0 0 44.1kHz 0 1 OFF 1 0 48kHz 1 1 32kHz Table 16. De-emphasis Control 015002211-E-02 (default) 2015/08 - 43 - [AK4452] ■ Output Volume (PCM mode, DSD mode) The AK4452 has a channel-independent digital attenuator (256 levels, 0.5dB steps). Attenuation level of each DAC can be set by ATT7-0 bits (register 03-04H), respectively (Table 17). Input data is attenuated from 0dB to -127dB including Mute. The transition between set values is a soft transition, thus no switching noise is occurred. ATT7-0bits Attenuation Level (register03-04H) FFH +0dB (default) FEH -0.5dB FDH -1.0dB : : : : 02H -126.5dB 01H -127.0dB 00H MUTE (-∞) Table 17. Attenuation level of Digital Attenuator Transition time between set values of ATL/R7-0 bits can be selected by the ATS1-0 bits (Table 18). The transition between set values is a soft transition in Mode0/1/2/3 eliminating switching noise in the transition. The register settings are maintained when switching the mode between PCM and DSD modes. Mode ATS1 ATS0 ATT speed (default) 0 0 0 4080/fs 1 0 1 2040/fs 2 1 0 510/fs 3 1 1 255/fs Table 18. Transition Time between Set Values of ATT7-0 bits The transition between set values is a soft transition of 4080 levels in mode 0. It takes 4080/fs (92.5ms @fs=44.1kHz) from FFH to 00H. If the PDN pin goes to “L”, ATT7-0 bits are initialized to FFH. If the digital volume is changed during reset, the volume will be changed to the setting value after releasing the reset. If the volume is changed in 5/fs after releasing a reset, the volume is changed immediately without soft transition. In DSD mode, the digital volume is set to MUTE by setting ATT7-0 bits = “02H” or “01H”. 015002211-E-02 2015/08 - 44 - [AK4452] ■ Out of Band Noise Reduction Filter (PCM mode, DSD mode) The AK4452 has an out of band noise reduction filter that can change frequency response. This FIR filter attenuates out of band noise and prevents a degradation of the analog characteristics caused by a switching regulator, etc. FIR2-0 bits set the frequency for noise attenuation. The filter characteristics will differ in DSD direct mode compared with other modes (Table 19). FIR2-0 FIR filter bits Mode 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 FIR filter Except DSD direct mode DSD direct mode 1/4*[1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0] 1/2*[1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0] (default) 1/4*[1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1] 1/2*[0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0] 1/4*[1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1] 1/2*[0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0] 1/4*[1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1] 1/2*[0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0] 1/4*[1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1] 1/2*[0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0] 1/4*[1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1] 1/2*[0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0] 1/4*[1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1] 1/2*[0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0] 1/4*[1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1] 1/2*[0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0] Table 19. FIR Filter Setting Figure 36. Mode0 FIR Filter (Except DSD direct mode) Figure 37. Mode1 FIR Filter (Except DSD direct mode) 015002211-E-02 2015/08 - 45 - [AK4452] Figure 38. Mode2 FIR Filter (Except DSD direct mode) Figure 39. Mode3 FIR Filter (Except DSD direct mode) Figure 40. Mode4 FIR Filter (Except DSD direct mode) 015002211-E-02 2015/08 - 46 - [AK4452] Figure 41. Mode5 FIR Filter (Except DSD direct mode) Figure 42. Mode6 FIR Filter (Except DSD direct mode) Figure 43. Mode7 FIR Filter (Except DSD direct mode) 015002211-E-02 2015/08 - 47 - [AK4452] Figure 44. Mode0 FIR Filter (DSD direct mode) Figure 45. Mode1 FIR Filter (DSD direct mode) Figure 46. Mode2 FIR Filter (DSD direct mode) 015002211-E-02 2015/08 - 48 - [AK4452] Figure 47. Mode3 FIR Filter (DSD direct mode) Figure 48. Mode4 FIR Filter (DSD direct mode) Figure 49. Mode5 FIR Filter (DSD direct mode) 015002211-E-02 2015/08 - 49 - [AK4452] Figure 50. Mode6 FIR Filter (DSD direct mode) Figure 51. Mode7 FIR Filter (Except DSD direct mode) 015002211-E-02 2015/08 - 50 - [AK4452] ■ Zero Detection (PCM mode, DSD mode) When zero detection function is enabled, the DZF pin goes to “H” if the input data at each channel is continuously zeros for 8192 LRCK cycles. Zero detection channels (AOUTL1N/P and AOUTR1N/P pins) can be selected by 08H registers (L1 bit, R1 bit). The DZF pin immediately returns to “L” if the input data of each channel is not zero. If the RSTN bit is “0”, the DZF pins of both channels go to “H”. The DZF pin of both channels go to “L” after 4 ~ 5/fs when RSTN bit returns to “1”. The DZFB bit can invert the polarity of the DZF pin. If all channels are disabled, the DZF pin outputs “Not zero”. Zero detection function is disabled when DSDD bit = “1”. DZFB bit Data DZF pin Not zero L 0 Zero detect H Not zero H 1 Zero detect L Not zero: One of the zero detection channels set by L1 bit and R1 bit does not detect zero. Zero detect: All zero detection channels set by L1 bit and R1 bit detect zero. Table 20. DZF Pin Function ■ LR Channel Output Signal Select (PCM mode, DSD mode) Select output signal combination of L and R channels by this function. Input and output signal combination of the AK4452 can be set by MONO1 bit and SELLR1 bit. The output signal phase of DAC is controlled by INVL and INVR bits. With these settings, sixteen output signal combinations are available. These settings are available for any audio format. MONO1 bit SELLR1 bit 0 0 0 1 1 0 1 1 INVL1 bit INVR1 bit 0 0 1 0 0 1 1 1 0 0 1 0 0 1 1 1 0 0 1 0 0 1 1 1 0 0 1 0 0 1 1 1 Table 21. Output Select for DAC 015002211-E-02 L1ch Out R1ch Out L1ch In L1ch In Invert L1ch In L1ch In Invert R1ch In R1ch In Invert R1ch In R1ch In Invert L1ch In L1ch In Invert L1ch In L1ch In Invert R1ch In R1ch In Invert R1ch In R1ch In Invert R1ch In R1ch In R1ch In Invert R1ch In Invert L1ch In L1ch In L1ch In Invert L1ch In Invert L1ch In L1ch In L1ch In Invert L1ch In Invert R1ch In R1ch In R1ch In Invert R1ch In Invert 2015/08 - 51 - [AK4452] ■ Sound Quality Adjustment (PCM mode, DSD mode) The sound color of the AK4452 can be controlled by SC1-0 bits. SC1 SC0 0 0 1 0 1 0 1 1 Sound Mode 1 (default) 2 3 4 Table 22. Sound Quality Select Mode 015002211-E-02 2015/08 - 52 - [AK4452] ■ DSD Full Scale (FS) Signal Detection Function The AK4452 has a full scale signal detection function for each channel in DSD mode. When the input data of each channel (DSDL1, DSDR1) is continuously “0” (-FS) or “1” (+FS) for 2048 cycles, the AK4452 detects a full scale signal and outputs “1” on the DML1 and DMR1 bits. The output data is muted if a full scale signal is detected. When DSDD bit = “0”, the output data is changed in soft transition, and the output data is changed without soft transition when DSDD bit = “1”. A recovering condition to normal operation mode from full scale detection status is selected by DMC bit if DDM bit = “1”. When DMC bit = “0”, the AK4452 will return to normal operation automatically by inputting a normal signal. When DMC bit = “1”, the AK4452 will return to normal operation mode by writing “1” to DMRE bit. DSDD bit Mode Status after Detection 0 Normal path DSD Mute (default) 1 Volume pass PD Table 23. DSD Mode and The Device Status after Full Scale Detection (DDM bit= “0”) 2048fs DSD Error (DDR or DDLbit) DSD Data DSD Data DSD Data (FS or -FS ) DSD Data AOUT Figure 52. Analog Output Waveform when DSD FS is Detected (DSDD bit= “1”) 2048fs DSD Error (DDR or DDLbit) DSD Data DSD Data DSD Data (FS or -FS ) DSD Data AOUT Figure 53. Analog Output Waveform when DSD FS is Detected (DSDD bit= “0”) 015002211-E-02 2015/08 - 53 - [AK4452] ■ Soft Mute Operation (PCM mode, DSD mode) The soft mute operation is performed at digital domain. When the SMUTE pin goes to “H” or set SMUTE bit to “1”, the output signal is attenuated by during ATT_DATA ATT transition time from the current ATT level. When the SMUTE pin is returned to “L” or the SMUTE bit is returned to “0”, the mute is cancelled and the output attenuation gradually changes to the ATT level during ATT_DATA ATT transition time. If the soft mute is cancelled before attenuating , the attenuation is discontinued and returned to ATT level by the same cycle. The soft mute is effective for changing the signal source without stopping the signal transmission. SMUTE pin or SMUTE bit (1) (1) ATT_Level (3) Attenuation - GD (2) GD (2) AOUT DZF pin (4) 8192/fs Notes: (1) ATT_DATA ATT transition time. For example, this time is 4080LRCK cycles (1020/fs) at ATT_DATA=255 in Normal Speed Mode. (2) The analog output corresponding to the digital input has group delay (GD). (3) If the soft mute is cancelled before attenuating after starting the operation, the attenuation is discontinued and returned to ATT level by the same cycle. (4) When the input data for a zero detection channel is continuously zeros for 8192 LRCK cycles, the DZF pin goes to “H”. The DZF pin immediately returns to “L” if input data are not zero. Figure 54. Soft Mute Function 015002211-E-02 2015/08 - 54 - [AK4452] ■ Error Detection Three types of error can be detected in I2C mode when the LDOE pin = “H”. (Table 24) When the error is detected, all circuits are powered-down and the analog outputs become floating (Hi-Z) state. In I2C mode, the AK4452 does not generate acknowledge (ACK) in error status. Once the error is detected the AK4452 does not return to normal operation automatically even if the error condition is removed so restart the AK4452 by the PDN pin. No Error Error Condition 1 Internal Reference Voltage Error Internal reference voltage is not powered up. 2 LDO Over Voltage Detection LDO voltage > 2.2 ~ 2.5V 3 LDO Over Current Detection LDO current < 40 ~ 110mA Table 24. Error Detection In I2C mode, the AK4452 does not generate acknowledge (ACK) in error status. ■ System Reset The AK4452should be reset once by bringing the PDN pin = “L” upon power-up. In PCM (DSD) mode, the AK4452 exits this system reset (power-down mode) by MCLK and LRCK (DCLK) after the PDN pin = “H”. The AK4452 detects a rising edge of MCLK first, and then the analog block exits power-down mode by a rising edge of LRCK (DCLK). The digital block exits power-down mode after the internal counter counts MCLK for 4/fs. 015002211-E-02 2015/08 - 55 - [AK4452] ■ Power Down Function The AK4452 is placed in power-down mode by bringing the PDN pin “L” and the analog outputs become floating (Hi-Z) state. Power-up and power-down timings are shown in Figure 55. Power PDN pin (1) VDD18 pin (2) Internal PDN Internal State Normal Operation (register write and DAC input are available) DAC In (Digital) “0”data “0”data GD (4) DAC Out (Analog) Clock In Reset (3) (5) GD (5) (4) Don’t care MCLK,LRCK,BICK (7) DZF External Mute (6) Mute ON Mute ON Notes: (1) After AVDD and TVDD are powered-up, the PDN pin should be “L” for 150ns. (2) After PDN pin = “H”, the internal LDO power-up if the LDOE pin = “H”. The internal circuits will be powered up after shutdown switch is ON in the end of a counter by the internal oscillator (10ms(max)). If the LDOE pin = “L”, the shutdown switch is activated after the AK4452 is powered up. The internal circuits will be powered up in 1msec (max) after the activation of the shutdown switch. During this period, digital output and digital in/output pins may output an instantaneous pulse (max. 1us). Therefore, referring the output of digital pins and data transmission with a device on the same 3-wire serial/I2C bus as the AK4452 should be avoided in this period to prevent system errors. (3) The analog output corresponding to digital input has group delay (GD). (4) Analog outputs are floating (Hi-Z) in power down mode. (5) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input. (6) Mute the analog output externally if click noise (5) adversely affect system performance The timing example is shown in this figure. (7) The DZF pin is “L” in the internal power-down mode. Figure 55. Power down/up Sequence Example 015002211-E-02 2015/08 - 56 - [AK4452] ■ Power Off and Reset Functions RSTN PW1 1 1 0 0 0 1 0 1 DAC Register Digital OFF Hold Off ON Hold On OFF Hold Off ON Hold Off Table 25. Power Off and Reset Function Analog Output DAC Hi-Z normal Hi-Z VREFH/2 (1) Power OFF Function 1 (PW1 bit) The DAC can be powered down immediately by setting PW1 bit to “0”. In this time, all circuits except registers are powered down and the analog output goes to floating state (Hi-z). Figure 56 shows a timing example of power-on and power-down. PW1 bit Internal State Normal Operation Power-off D/A In (Digital) “0” data GD D/A Out (Analog) (1) GD (3) Clock In (2) (3) (1) Don’t care MCLK, BICK, LRCK DZF External MUTE Normal Operation (5) (4) Mute ON Notes: (1) The analog output corresponding to digital input has group delay (GD). (2) Analog outputs are floating (Hi-Z) in power down mode. (3) Small pop noise occurs at the edges(“ ”) of the internal timing of PW1 bit. This noise is output even if “0” data is input. (4) Mute the analog output externally if click noise (3) adversely affect system performance. (5) The DZF pin outputs “L”, in power down mode (PW1 bit = “0”). Figure 56. Power-off/on Sequence Example 015002211-E-02 2015/08 - 57 - [AK4452] (2) Reset Function (RSTN bit) The DAC can be reset by setting RSTN bit to “0” but the internal registers are not initialized. In this time, the corresponding analog outputs go to VREFH/2 and the DZF pin outputs “H” if clocks (MCLK, BICK and LRCK) are input. Figure 57 shows an example of reset sequence by RSTN bit. RSTN bit 3~4/fs (6) 2~3/fs (5) Internal RSTN bit Internal State Normal Operation D/A In (Digital) “0” data (1) D/A Out (Analog) Normal Operation Digital Block Power-down GD GD (3) Clock In (2) (3) (1) Don’t care BICK 2/fs(4) DZF Notes: (1) The analog output corresponding to digital input has group delay (GD). (2) Analog outputs are floating (Hi-Z) in power down mode. (3) Small pop noise occurs at the edges(“ ”) of the internal timing of RSTN bit. This noise is output even if “0” data is input. (4) The DZF pin goes to “H” on the falling edge of RSTN bit and goes to “L” in 2/fs after a rising edge of the internal RSTN. (5) There is a delay, 3~4/fs from RSTN bit “0” to the internal RSTN bit “0”, and 2~3/fs from RSTN bit “1” to the internal RSTN bit “1”. Figure 57. Reset Sequence Example 1 Note: When using both reset (RSTN bit = “0”) and DAC power-off bits (PW1 bit), power-off bits should be set to “0” before RSTN bit. 015002211-E-02 2015/08 - 58 - [AK4452] (3) Reset Function (MCLK Stop) When the MCLK stops for more than 10us during operation (PDN pin = “H”), the AK4452 is placed in reset state and the analog output goes to floating state (Hi-Z). When the MCLK is restarted, reset state is released and the AK4452 returns to normal operation mode. Zero detection function is disabled while the MCLK is stopped. Figure 58 shows a reset sequence by stopping the MCLK. PDN pin RSTN bit (1) Internal State Power-down D/A In (Digital) Power-down Normal Operation (2) GD (4) Hi-Z (2) (4) (4) Clock In MCLK Stop MCLK External MUTE Normal Operation (3) GD D/A Out (Analog) Digital Circuit Power-down (5) (5) (5) Notes: (1) After the AK4452 is powered-up, the PDN pin should be “L” for 150ns. (2) The analog output corresponding to digital input has group delay (GD). (3) The digital data input can be stopped. Click noise after MCLK is input again can be reduced by inputting “0” data during this period. (4) Click noise occurs within 3 ~ 4LRCK from the riding edge (“↑”) of the PDN pin or MCLK inputs. This noise is output even if “0” data is input. (5) Mute the analog output externally if click noise (4) adversely affect system performance. Figure 58. Reset Sequence Example 2 015002211-E-02 2015/08 - 59 - [AK4452] ■ Clock Synchronization and BICK Edge Detection Functions ● Synchronization Function (Analog Output Phase Synchronization) This function synchronizes analog output phase by suppressing the phase difference of the AK4452 and other AKM devices with synchronization function to within 3/256fs. Analog output phase synchronization function becomes valid when input data at all channels are continuously “0” for 8192 times if SYNCE bit is set to “1” during operation in PCM mode or when RSTN bit is set to “0”. Example) In the case of using the AK4452 with the AK4458 (Figure 59) The AK4452 and the AK4458 have synchronization function. The output phase difference between the AK4452’s output (AOUT1LP/N_2, AOUT1RP/N_2) and the AK4458’s output (AOUT1-4LP/N_8, AOUT1-4RP/N_8) will be within 3/256fs. DSP AK4452 MCLK LRCK MCLK LRCK AOUT1LP/N AOUT1RP/N AOUT1LP/N_2 AOUT1RP/N_2 AK4458 MCLK LRCK AOUT1LP/N AOUT1RP/N AOUT1LP/N_8 AOUT1RP/N_8 AOUT4LP/N AOUT4RP/N AOUT4LP/N_8 AOUT4RP/N_8 Figure 59. System Example of Clock Synchronization Function 015002211-E-02 2015/08 - 60 - [AK4452] ■ Parallel Mode Parallel mode is available by setting the I2C pin = “H”, and the PS pin = “H”. Audio interface format of the parallel mode is controlled by TDM1-0 bits and DIF bit (Table 26). Daisy Chain mode is also available by setting the DCHAIN pin = “H”. In parallel mode, the clock setting mode is always in auto setting mode (ACKS mode is enabled and fixed internally). Zero detection function is not available in parallel mode. All functions controlled exclusively by Serial mode are only available in their default register settings. TDM1 pin 0 0 0 0 1 1 1 1 TDM0 pin DIF pin 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 Table 26. Parallel Mode Mode Mode6 (Table 13) Mode7 (Table 13) Mode12 (Table 13) Mode13 (Table 13) Mode18 (Table 13) Mode19 (Table 13) Mode24 (Table 13) Mode25 (Table 13) ■ Serial Control Interface The AK4452’s functions are controlled through registers. The registers may be written by two types of control modes. The internal registers are controlled in 3-wire serial control mode when the I2C pin = “L”, and in I2C bus control mode when the I2C pin = “H” and the PS pin = “L”. 015002211-E-02 2015/08 - 61 - [AK4452] (1) 3-wire Serial Control Mode (I2C pin = “L”) The internal registers may be written through the 3-wire µP interface pins (CSN, CCLK and CDTI). The data on this interface consists of a 2-bit Chip address, Read/Write (1bit, Fixed to “1”, Write only), Register address (MSB first, 5bits) and Control data (MSB first, 8bits). Address and data are clocked in on the rising edge of CCLK and data is clocked out on the falling edge. For write operations, data is latched after a low-to-high transition of CSN. The clock speed of CCLK is 5MHz (max). The internal registers are initialized by setting the PDN pin = “L”. In serial mode, an internal timing circuit is reset by setting RSTN bit = “0” but register values are not initialized. CSN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CCLK CDTI C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 C1-C0: Chip Address (C1= CAD1 pin, C0= CAD0 pin) R/W: Read/Write (Fixed to “1”, Write only) A4-A0: Register Address D7-D0: Control Data Figure 60. 3-wire Serial Control I/F Timing * The AK4452 does not support read commands in 3wire serial control mode. * When the AK4452 is in power down mode (PDN pin = “L”), writing into the control registers is prohibited. * The control data cannot be written when the CCLK rising edge is 15 times or less or 17 times or more during CSN is “L”. 015002211-E-02 2015/08 - 62 - [AK4452] (2) I2C-bus Control Mode (I2C pin = “H”) The AK4452 supports the fast-mode I2C-bus (max: 400kHz, Ver1.0). 1. WRITE Operations Figure 61 shows the data transfer sequence of the I2C-bus mode. All commands are preceded by a START condition. A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 67). After the START condition, a slave address is sent. This address is 7 bits long followed by the eighth bit that is a data direction bit (R/W). The most significant five bits of the slave address are fixed as “00100”. The next bits are CAD1-0 (device address bits). This bits identifies the specific device on the bus. The hard-wired input pins (CAD1-0 pins) set these device address bit (Figure 62). If the slave address matches that of the AK4452, the AK4452 generates an acknowledge and the operation is executed. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse (Figure 68). R/W bit = “1” indicates that the read operation is to be executed. “0” indicates that the write operation is to be executed. The second byte consists of the control register address of the AK4452. The format is MSB first, and those most significant 3-bits are fixed to zeros (Figure 63). The data after the second byte contains control data. The format is MSB first, 8bits (Figure 64). The AK4452 generates an acknowledge after each byte is received. Data transfer is always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is HIGH defines STOP condition (Figure 67). The AK4452 can perform more than one byte write operation per sequence. After receipt of the third byte the AK4452 generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. After receiving each data packet the internal 6-bit address counter is incremented by one, and the next data is automatically taken into the next address. If the address exceeds 14H prior to generating a stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten. The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW (Figure 69) except for the START and STOP conditions. S T A R T SDA S T O P R/W="0" Slave S Address Sub Address(n) A C K Data(n) A C K Data(n+1) A C K Data(n+x) A C K A C K P A C K Figure 61. Data Transfer Sequence at the I2C-Bus Mode 0 0 1 0 0 CAD1 CAD0 R/W (These CAD1-0 should match with CAD1-0 pins) Figure 62. The First Byte 0 0 0 A4 A3 A2 A1 A0 D1 D0 Figure 63. The Second Byte D7 D6 D5 D4 D3 D2 Figure 64. Byte Structure After The Second Byte 015002211-E-02 2015/08 - 63 - [AK4452] 2. READ Operations Set the R/W bit = “1” for the READ operation of the AK4452. After transmission of data, the master can read the next address’s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word. After receiving each data packet the internal 6-bit address counter is incremented by one, and the next data is automatically taken into the next address. If the address exceeds 14H prior to generating stop condition, the address counter will “roll over” to 00H and the data of 00H will be read out. The AK4452 supports two basic read operations: Current Address Read and Random Address Read. 2-1. Current Address Read The AK4452 contains an internal address counter that maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either a read or write) was to address “n”, the next CURRENT READ operation would access data from the address “n+1”. After receipt of the slave address with R/W bit “1”, the AK4452 generates an acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal address counter by 1. If the master does not generate an acknowledge but generates a stop condition instead, the AK4452 ceases transmission. S T A R T SDA S T O P R/W="1" Slave S Address Data(n) Data(n+1) MA AC SK T E R A C K Data(n+2) MA AC SK T E R Data(n+x) MA AC SK T E R MA AC SK T E R P MN AA SC T EK R Figure 65. Current Address Read 2-2. Random Address Read The random read operation allows the master to access any memory location at random. Prior to issuing a slave address with the R/W bit =“1”, the master must execute a “dummy” write operation first. The master issues a start request, a slave address (R/W bit = “0”) and then the register address to read. After the register address is acknowledged, the master immediately reissues the start request and the slave address with the R/W bit =“1”. The AK4452 then generates an acknowledge, 1 byte of data and increments the internal address counter by 1. If the master does not generate an acknowledge but generates a stop condition instead, the AK4452 ceases transmission. S T A R T SDA S T A R T R/W="0" Slave S Address Sub Address(n) A C K Slave S Address A C K S T O P R/W="1" Data(n) A C K Data(n+1) MA AC S K T E R Data(n+x) MA AC S T K E R MA AC S T K E R P MN A A S T C E K R Figure 66. Random Address Read 015002211-E-02 2015/08 - 64 - [AK4452] SDA SCL S P start condition stop condition Figure 67. START and STOP Conditions DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER 2 1 8 9 S clock pulse for acknowledgement START CONDITION Figure 68. Acknowledge on the I2C-Bus SDA SCL data line stable; data valid change of data allowed Figure 69. Bit Transfer on the I2C-Bus 015002211-E-02 2015/08 - 65 - [AK4452] ■ Function List Available functions are different in PCM mode and in DSD mode. Function Default Address Bit Attenuation Level 0dB 03-04H ATT7-0 Audio Data Interface Modes 32bit MSB justified 00H DIF2-0 Data Zero Detect Enable Disable 08H L1/R1 Minimum delay Filter Enable SD Slow Roll-off Filter Enable Sharp roll-off filter 01-02H SLOW Short delay Filter Enable De-emphasis Response OFF 01H DEM1-0 Soft Mute Enable Normal Operation 01H SMUTE DSD/PCM Mode Select PCM mode 02H D/P Master Clock Frequency Select 512fs 02H DCKS at DSD mode MONO mode Stereo mode Stereo 02H MONO select Inverting Enable of DZF “H” active 02H DZFB The data selection of L channel 02H,05H R channel SELLR1 and R channel 0DH The data selection of DAC Normal 0A-0BH SDS1/2 Data Invert Mode OFF 05H INVL1/R1 Clock Synchronization Not Available 07H SYNCE Table 27. Function List (Y: Available, -: Not available) 015002211-E-02 PCM Y Y Y Y Y Y Y Y Y DSD Y Y Y Y - Y Y Y Y Y Y Y Y Y Y Y - 2015/08 - 66 - [AK4452] ■ Register Map Addr 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H Register Name Control 1 Control 2 Control 3 L1ch ATT R1ch ATT Control 4 DSD1 Control 5 Sound Control DSD2 Control 6 Control 7 Control 8 Reserved Reserved Reserved Reserved D7 ACKS 0 DP ATT7 ATT7 INVL1 DDM 0 L1 0 TDM1 ATS1 0 0 0 1 1 D6 0 0 0 ATT6 ATT6 INVR1 DML1 0 R1 0 TDM0 ATS0 0 0 1 1 1 D5 0 SD DCKS ATT5 ATT5 0 DMR1 0 0 0 SDS1 0 0 0 0 1 1 D4 0 DFS1 DCKB ATT4 ATT4 0 DMC 0 0 0 SDS2 SDS0 0 0 1 1 1 D3 DIF2 DFS0 MONO1 ATT3 ATT3 0 DMRE 0 0 0 1 1 0 0 0 1 1 D2 DIF1 DEM11 DZFB ATT2 ATT2 0 0 0 0 0 PW1 1 FIR2 0 0 1 1 D1 DIF0 DEM10 SELLR1 ATT1 ATT1 DFS2 DSDD 1 SC1 DSDF 0 DCHAIN FIR1 0 0 1 1 D0 RSTN SMUTE SLOW ATT0 ATT0 SSLOW DSDSEL0 SYNCE SC0 DSDSEL1 1 0 FIR0 0 0 1 1 Note 35. Data must not be written into addresses from 11H to 1FH. Note 36. When the PDN pin is set to “L”, all registers are initialized to their default values. Note 37. When RSTN bit is set to “0”, only the internal timing circuit is reset but register values are not initialized. 015002211-E-02 2015/08 - 67 - [AK4452] ■ Register Definitions Addr Register Name 00H Control 1 R/W Default D7 ACKS R/W 0 D6 0 R/W 0 D5 0 R/W 0 D4 0 R/W 0 D3 DIF2 R/W 1 D2 DIF1 R/W 1 D1 DIF0 R/W 0 D0 RSTN R/W 0 RSTN: Internal Timing Reset 0: Reset (default) Internal clock timings are reset, but all other registers are not reset to their default value and R/W access is still allowed. 1: Normal Operation DIF2-0: Audio Data Interface Modes (Table 13) Default value is “110” (Mode 6: 32-bit MSB justified). ACKS: Master Clock Frequency Auto Setting Mode Enable (PCM only) 0: Disable : Manual Setting Mode (default) 1: Enable : Auto Setting Mode When ACKS bit = “1”, the sampling frequency and MCLK frequency are detected automatically. Addr Register Name 01H Control 2 R/W Default D7 0 R/W 0 D6 0 R/W 0 D5 SD R/W 1 D4 DFS1 R/W 0 D3 DFS0 R/W 0 D2 DEM11 R/W 0 D1 DEM10 R/W 1 D0 SMUTE R/W 0 SMUTE: Soft Mute Enable. 0: Normal Operation (default) 1: DAC outputs soft-muted. DEM11-0: DAC1 De-emphasis Response (Table 16) Default value is “01” (OFF). DFS1-0: Sampling Speed Control (Table 2) Default value is “00” (Normal Speed). See also register address 05H for DFS2. A click noise occurs when switching DFS2-0 bits setting. SD: Short delay Filter Enable. (Table 12) 0: Sharp roll-off filter 1: Short delay filter (default) 015002211-E-02 2015/08 - 68 - [AK4452] Addr Register Name 02H Control 3 R/W Default D7 DP R/W 0 D6 0 R 0 D5 DCKS R/W 0 D4 DCKB R/W 0 D3 MONO1 R/W 0 D2 DZFB R/W 0 D1 SELLR1 R/W 0 D0 SLOW R/W 0 SLOW: Slow Roll-off Filter Enable. (Table 12) 0: Sharp roll-off filter (default) 1: Slow roll-off filter SELLR1: The data selection of DAC1 L channel and R channel, when MONO mode (Table 21) 0: All channel output L channel data. (default) 1: All channel output R channel data. Settings of MONO1 bit, INVL1 bit and INVR1 bit should also be considered when setting this bit. DZFB: Inverting Enable of DZF (Table 20) 0: DZF pin goes “H” at Zero Detection (default) 1: DZF pin goes “L” at Zero Detection MONO1: DAC1 enters monaural output mode when MONO bit = “1”. (Table 21) 0: Stereo mode (default) 1: MONO mode DCKB: Polarity of DCLK (DSD Only) 0: DSD data is output from DCLK falling edge. (default) 1: DSD data is output from DCLK rising edge. DCKS: Master Clock Frequency Select at DSD mode (DSD only) 0: 512fs (default) 1: 768fs DP: DSD/PCM Mode Select 0: PCM Mode (default) 1: DSD Mode The AK4452 must be reset by RSTN bit when changing DP bit setting. Addr Register Name 03H L1ch ATT 04H R1ch ATT R/W Default D7 ATT7 ATT7 R/W 1 D6 ATT6 ATT6 R/W 1 D5 ATT5 ATT5 R/W 1 D4 ATT4 ATT4 R/W 1 D3 ATT3 ATT3 R/W 1 D2 ATT2 ATT2 R/W 1 D1 ATT1 ATT1 R/W 1 D0 ATT0 ATT0 R/W 1 ATT7-0: Attenuation Level (Table 17) Initial value is “FF” (0dB) 015002211-E-02 2015/08 - 69 - [AK4452] Addr Register Name 05H Control 4 R/W Default D7 INVL1 R/W 0 D6 INVR1 R/W 0 D5 0 R/W 0 D4 0 R/W 0 D3 0 R/W 0 D2 0 R/W 0 D1 DFS2 R/W 0 D0 SSLOW R/W 0 SSLOW: Digital Filter Bypass Mode Enable (Table 15) 0: Enable digital filter selected by SD and SLOW bits (default) 1: Super Slow Roll-off Mode DFS2: Sampling Speed Control (Table 2) Default value is “0” (Normal Speed). See also register address 01H for DFS1-0. A click noise occurs when switching DFS2-0 bits setting. INVL1: AOUTL1 Output Phase Inverting Bit INVR1: AOUTR1 Output Phase Inverting Bit 0: Normal (default) 1: Inverted 015002211-E-02 2015/08 - 70 - [AK4452] Addr Register Name 06H DSD1 R/W Default D7 DDM R/W 0 D6 DML1 R/W 0 D5 DMR1 R/W 0 D4 DMC R/W 0 D3 DMRE R/W 0 D2 0 R/W 0 D1 DSDD R/W 0 D0 DSDSEL0 R/W 0 DSDSEL1-0: DSD sampling speed control (Table 10) Default value is “00”. DSDD: DSD play back path control (Table 11) Default value is “0”. DMRE: DSD mute release 0: Hold (default) 1: Mute Release This register is only valid when DDM bit = “1” and DMC bit = “1”. It releases a mute state when DSD data is muted by DDM and DMC bits. DMC: DSD mute control 0: Auto Return (default) 1: Mute Hold This register is only valid when DDM bit = “1”. It selects the process when DSD data level drops under full scale while DSD data is muted by DDM bit. DMR1/DML1 This register output detection flag when the signal level of the DSDR1/L1 pin is full scale. DDM: DSD data mute 0: Disable (default) 1: Enable The AK4452 has a function that mutes the output when DSD data is all “1” or “0” for 2048 samplings (1/fs). This register controls the DSD mute function. 015002211-E-02 2015/08 - 71 - [AK4452] Addr Register Name 07H Control 5 R/W Default D7 0 R/W 0 D6 0 R/W 0 D5 0 R/W 0 D4 0 R/W 0 D3 0 R/W 0 D2 0 R/W 0 D1 1 R/W 1 D0 SYNCE R/W 1 D6 R1 R/W 0 D5 0 R/W 0 D4 0 R/W 0 D3 0 R/W 0 D2 0 R/W 0 D1 SC1 R/W 0 D0 SC0 R/W 0 SYNCE: SYNC Mode Enable 0: SYNC Mode Disable 1: SYNC Mode Enable (default) Addr Register Name 08H Sound Control R/W Default D7 L1 R/W 0 SC1-0: Sound Control (Table 22) Default value is “00”. L1, R1: Zero Detect Flag Enable Bit for the DZF pin 0: Disable (default) 1: Enable 015002211-E-02 2015/08 - 72 - [AK4452] Addr Register Name 09H DSD2 R/W Default D7 0 R/W 0 D6 0 R/W 0 D5 0 R/W 0 D4 0 R/W 0 D3 0 R/W 0 D2 0 R/W 0 D1 DSDF R/W 0 D4 SDS2 R/W 0 D3 1 R/W 1 D2 PW1 R/W 1 D1 0 R/W 0 D0 DSDSEL1 R/W 0 DSDSEL1-0: DSD Sampling Speed Control (Table 10) Default value is “00”. DSDF: DSD Filter Select (Table 12) Default value is “0”. Addr Register Name 0AH Control 6 R/W Default D7 TDM1 R/W 0 D6 TDM0 R/W 0 D5 SDS1 R/W 0 D0 1 R/W 1 PW1: Power Down control for DAC PW1: Power management for DAC 0: DAC power OFF 1: DAC power ON (default) SDS2-0: DAC Data Select 0: Normal Operation 1: Output Other Slot Data (Table 14) Default value is “000”. TDM1-0: TDM Mode Select (Table 13) Default value is “00”. 015002211-E-02 2015/08 - 73 - [AK4452] Addr Register Name 0BH Control 7 R/W Default D7 ATS1 R/W 0 D6 ATS0 R/W 0 D5 0 R/W 0 D4 SDS0 R/W 0 D3 1 R/W 1 D2 1 R/W 1 D1 DCHAIN R/W 0 D0 0 R/W 0 D3 0 R/W 0 D2 FIR2 R/W 0 D1 FIR1 R/W 0 D0 FIR0 R/W 0 DCHAIN: Daisy Chain Mode Enable 0: Daisy Chain Mode Disable (default) 1: Daisy Chain Mode Enable SDS2-0: DAC Data Select 0: Normal Operation 1: Output Other Slot Data (Table 14) ATS1-0: DAC Digital attenuator transition time setting (Table 18) Default value is “00”. Addr Register Name 0CH Control 8 R/W Default D7 0 R/W 0 D6 0 R/W 0 D5 0 R/W 0 D4 0 R/W 0 FIR2-0: FIR Filter Control (Table 19) Default value is “000”. 015002211-E-02 2015/08 - 74 - [AK4452] 10. Recommended External Circuits ■ Typical Connection Diagram Figure 70 and Figure 71 show system connection diagram, and Figure 72 shows the analog output circuit example. (1) LDOE pin = “H”, I2C-bus Control Mode(I2C pin = “H”) Analog 5.0V TST5 25 TST6 26 TST7 27 LDOE 28 TVDD 29 Analog 5.0V TST4 24 TST1 6 TDMO1 7 DZF 8 CAD1 TST2 22 AVDD 21 AVSS 20 0.1u + 10u AOUTR1P 19 AOUTR1N 18 VREFH1 17 N 15 AOUT1LN VREFL1 16 SDTI1 5 13 I2C 14 AOUT1LP 4 AK4452VN TST3 23 12 PS LRCK 11 CAD0_I2C 3 DVSS 30 PDN 32 BICK 10u + 0.1u 10 SCL Micro- MCLK 2 ９ SDA DSP 1 1u + VDD18 31 Digital 3.3V Analog Ground R1ch Mute R1ch Out L1ch LPF L1ch Mute L1ch Out 0.1u Controller Digital Ground R1ch LPF + Electrolytic Capacitor Ceramic Capacitor Notes: - Chip Address = “00”. BICK = 64fs, LRCK = fs - Power lines of AVDD and VREFH1 should be distributed separately from LDO and etc. while keeping low impedance. If it is not possible, it is recommended to connect a LPF composed by a 10Ω resistor and a 220uF capacitor between VREFL1 and VREFH1. - DVSS and AVSS must be connected to the same potential. - All digital input pins should not be allowed to float. Figure 70. Typical Connection Diagram (AVDD=5V, TVDD=3.3V) 015002211-E-02 2015/08 - 75 - [AK4452] (2) LDOE pin = “L”, I2C-bus Control Mode(I2C pin = “H”) Digital 3.3V Digital 1.8V Analog 5.0V Analog 5.0V TST1 6 TDMO1 7 DZF 8 CAD1 TST5 25 TST7 27 LDOE 28 TVDD 29 TST6 26 TST2 22 AVDD 21 AVSS 20 0.1u + 10u AOUTR1P 19 AOUTR1N 18 VREFH1 17 N 15 AOUT1LN VREFL1 16 SDTI1 5 AK4452VN 4 13 I2C 14 AOUT1LP Micro- TST4 24 TST3 23 12 PS LRCK 11 CAD0_I2C 3 DVSS 30 PDN 32 BICK 10 SCL MCLK 2 ９ SDA DSP 1 VDD18 31 10u + 1u 0.1u + Analog Ground R1ch Mute R1ch Out L1ch LPF L1ch Mute L1ch Out 0.1u Controller Digital Ground R1ch LPF + Electrolytic Capacitor Ceramic Capacitor Notes: - Chip Address = “00”. BICK = 64fs, LRCK = fs - Power lines of AVDD and VREFH1 should be distributed separately from LDO and etc. while keeping low impedance. If it is not possible, it is recommended to connect a LPF composed by a 10Ω resistor and a 220uF capacitor between VREFL1 and VREFH1. - DVSS and AVSS must be connected to the same potential. - All digital input pins should not be allowed to float. Figure 71. Typical Connection Diagram (AVDD=5V, TVDD=3.3V, VDD18=1.8V) 015002211-E-02 2015/08 - 76 - [AK4452] 1. Grounding and Power Supply Decoupling To minimize coupling by digital noise, decoupling capacitors should be connected to AVDD and TVDD respectively. AVDD are supplied from the analog supply of the system and TVDD is supplied from the digital supply of the system. DVSS and AVSS must be connected to the same potential. Decoupling capacitors especially small ceramic capacitors for high frequency should be placed as near as possible to the supply pin. 2. Voltage Reference The differential voltage between the VREFH1 pin and the VREFL1 pin sets the analog output range. The VREFH1 pin is normally connected to AVDD, and the VREFL1 pin is normally connected to AVSS. VREFH1 and VREFL1 should be connected with a 0.1µF ceramic capacitor as near as possible to the pin to eliminate the effects of high frequency noise. All signals, especially clocks, should be kept away from the VREFH1 and VREFL1 pins in order to avoid unwanted noise coupling into the AK4452. 015002211-E-02 2015/08 - 77 - [AK4452] 3. Analog Outputs The analog outputs are full differential outputs and 2.8Vpp (typ, VREFH1 VREFL1 = 5V) centered around VREFH/2. The differential outputs are summed externally, adding voltage VAOUT is calculated as (AOUT+) (AOUT). If the summing gain is 1, the output range is 5.6Vpp (typ, VREFH1 VREFL1= 5V). The bias voltage of the external summing circuit is supplied externally. PCM input data format is 2's complement. The output voltage (VAOUT) is a positive full scale for 7FFFFFH (@24bit) and a negative full scale for 800000H (@24bit). The ideal VAOUT is 0V for 000000H(@24bit). The output level is determined by the 1-bit signal duty ratio in DSD input mode. The output level is positive full scale when the duty is 100% (all “1”) and the output level is negative full scale when the duty is 0% (all “0”). In ideal case, a 0V voltage is output when the input signal duty is 50%. The internal switched - capacitor filters attenuate the noise generated by the delta -sigma modulator beyond the audio pass band. Figure 72 shows an example of differential outputs and LPF circuit example by a single op-amp. AK4452 R1 AOUT- 3.9k R2 4.7k 150 470p +Vop AOUT+ 3.9n R1 3.9k 4.7k Analog Out 150 470p -Vop Figure 72. External LPF Circuit Example 1 for PCM (fc = 99.0kHz, Q=0.680) R1 R2 GAIN(dB) DC Load (MAX) 3.3k 3.9k 3.9k 4.3k 4.7k 3.3k 4.7k 5.6k 6.8k 8.2k 0 1.620665 3.142468 3.980809 4.83432 3.8k 4.0k 3.5k 3.6k 3.6k Table 28. External LPF Circuit Example 1 for PCM 5.6k 12.0k 6.619864 3.8k Frequency Response Gain 20kHz 0.036dB 40kHz 0.225dB 80kHz 1.855dB Table 29. Frequency Response of External LPF Circuit Example 1 for PCM 015002211-E-02 2015/08 - 78 - [AK4452] 11. Package ■ Outline Dimensions 32-pin QFN (Unit: mm) ■ Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy, Halogen (bromine and chlorine) free Cu Solder (Pb free) plate 015002211-E-02 2015/08 - 79 - [AK4452] ■ Marking 4452 XXXX 1 1) Pin #1 indication 2) Date Code: XXXX (4 digits) 3) Marking Code: 4452 12. Revision History Date (Y/M/D) Revision 15/02/23 00 15/03/21 01 15/08/26 02 Reason Page First Edition Description 9 Addition 10 Error Correction Description Addition Error Correction Contents 76 ■ Handling of Unused Pin TDMO1 was added. Note 7: A description was added. “at the same time” Figure 70 was changed. 77 Figure 71 was added. 13, 15 13 to 16 Sharp Roll-Off Filter, fs=44.1kHz, DF + SCF, FR: 0 ~ 20kHz, max=0.1dB Short Delay Sharp Roll-Off Filter, fs=96kHz, DF + SCF, FR: 0 ~ 40kHz, max=0.1dB Description of Pass band spec of -3.0dB was added. 13 to 16 Frequency Response of -3.0(-6.0)dB was deleted. 27 [Table 3] 384kHz, 128fs 49.152 was added. Figure 52 and Figure 53 was changed. 13, 15 Description Addition Description Delete Description Addition Description Change Description Addition 53 56 ■ Power Down Function Description (2) was changed. 015002211-E-02 2015/08 - 80 - [AK4452] Date (Y/M/D) Revision Reason Error Correction Page 62 63 68 Contents C1-C0: Chip Address C1= CAD0 pin → CAD1 pin The most significant [remove “seven”] [add “five”] bits of the slave address Correct default value = 0 on table and description. Clarify description 015002211-E-02 2015/08 - 81 - [AK4452] IMPORTANT NOTICE 0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the information contained in this document without notice. When you consider any use or application of AKM product stipulated in this document (“Product”), please make inquiries the sales office of AKM or authorized distributors as to current status of the Products. 1. All information included in this document are provided only to illustrate the operation and application examples of AKM Products. AKM neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of AKM or any third party with respect to the information in this document. You are fully responsible for use of such information contained in this document in your product design or applications. AKM ASSUMES NO LIABILITY FOR ANY LOSSES INCURRED BY YOU OR THIRD PARTIES ARISING FROM THE USE OF SUCH INFORMATION IN YOUR PRODUCT DESIGN OR APPLICATIONS. 2. The Product is neither intended nor warranted for use in equipment or systems that require extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may cause loss of human life, bodily injury, serious property damage or serious public impact, including but not limited to, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic signaling equipment, equipment used to control combustions or explosions, safety devices, elevators and escalators, devices related to electric power, and equipment used in finance-related fields. Do not use Product for the above use unless specifically agreed by AKM in writing. 3. Though AKM works continually to improve the Product’s quality and reliability, you are responsible for complying with safety standards and for providing adequate designs and safeguards for your hardware, software and systems which minimize risk and avoid situations in which a malfunction or failure of the Product could cause loss of human life, bodily injury or damage to property, including data loss or corruption. 4. Do not use or otherwise make available the Product or related technology or any information contained in this document for any military purposes, including without limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass destruction weapons). When exporting the Products or related technology or any information contained in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. The Products and related technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 5. Please contact AKM sales representative for details as to environmental matters such as the RoHS compatibility of the Product. Please use the Product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. AKM assumes no liability for damages or losses occurring as a result of noncompliance with applicable laws and regulations. 6. Resale of the Product with provisions different from the statement and/or technical features set forth in this document shall immediately void any warranty granted by AKM for the Product and shall not create or extend in any manner whatsoever, any liability of AKM. 7. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of AKM. 015002211-E-02 2015/08 - 82 -