[AK4185] AK4185 Low Power Touch Screen Controller with SPI™ Interface AK4185 12 A/D 4 /5 IC 1.6Vmin AK4185 AK4185 X, Y DSC, DVC, Smart Phone, PMP 4/5 SPI™ 12bit ADC (S/H : 300Ksps ) ( (4 Osc ( ) ) ) : VDD = 1.6V ~ 3.6V PENIRQN : 240μA at 1.8V Package: 12pin CSP (1.96mm x 1.46mm, pitch 0.5mm) AK4182A VDD CSN XP/BR YP/TR XN/TL 4/5wire Touch Screen Drivers Interface VREF+ AIN+ SAR MUX ADC AIN- YN/BL SPI Serial I/F & Control Logic DIN SCLK DOUT VREF- IN/ WIPER PENIRQN TEMP Internal Osc VSS Figure 1. SPI™ MS0954-J-05 Motorola 2010/10 -1- [AK4185] ■ AK4185ECB −40 ∼ +85°C AKD4185 AK4185 12pin CSP (1.96mm x 1.46mm, 0.5mm pitch) ■ 3 Top View 2 1 A B C D 3 XP/BR YP/TR XN/TL YN/BL 2 VDD CSN DIN VSS 1 IN/WIPER PENIRQN DOUT SCLK A B C D TOP View MS0954-J-05 2010/10 -2- [AK4185] No. C2 Pin Name DIN B2 CSN D1 A2 A3 SCLK VDD XP BR YP TR XN TL YN BL VSS IN WIPER PENIRQN B3 C3 D3 D2 A1 B1 I/O I I I I/O I/O I/O I/O I/O I/O I/O I/O I I O Function Serial Data Input SCLK “↑” “L” Chip Select Input CSN = “L” Serial Clock Input Power Supply and External Reference Input: 1.6V ~ 3.6V Touch Panel X+ Input (4-wire, PANEL bit = “0”) Touch Panel Bottom Right Input (5-wire, PANEL bit = “1”) Touch Panel Y+ Input (4-wire, PANEL bit = “0”) Touch Panel Top Right Input (5-wire, PANEL bit = “1”) Touch Panel X- Input (4-wire, PANEL bit = “0”) Touch Panel Top Left Input (5-wire, PANEL bit = “1”) Touch Panel Y- Input (4-wire, PANEL bit = “0”) Touch Panel Bottom Right Input (5-wire, PANEL bit = “1”) Ground Auxiliary Analog Input (4-wire, PANEL bit = “0”) Top Touch Panel Input (5-wire, PANEL bit = “1”) Pen Interrupt Output (CMOS output) “L” “H” C1 DOUT Note 1. O “H” Serial A/D Data Output A/D SCLK “↓” MSB CSN = “H” DOUT Hi-Z (DIN, CSN, SCLK) MS0954-J-05 2010/10 -3- [AK4185] ■ Analog IN/WIPER (VSS = 0V (Note 2)) Parameter Symbol min max Power Supply VDD -0.3 4.6 Input Current, Any Pins except for supply IIN ±10 Touch Panel Drive Current IOUTDRV 50 Input Voltage (Note 3) VIN (VDD+0.3) or 4.6 −0.3 Ambient Temperature (power applied) Ta -40 85 Storage Temperature Tstg -65 150 Note 2. Note 3. XP/BR, XN/TL, YP/TR, YN/TL, IN/WIPER, CSN, DIN and SCLK pins. Max (VDD+0.3)V Units V mA mA V °C °C 4.6V : (VSS = 0V (Note 2)) Parameter Power Supply Note 2. Symbol VDD min 1.6 typ 1.8 max 3.6 Units V : MS0954-J-05 2010/10 -4- [AK4185] (Ta = -40°C to 85°C, VDD = 1.8V, fSCLK = fs x 16=5.0MHz, 12bit mode) Parameter min A/D Converter Resolution No Missing Codes 11 Integral Nonlinearity (INL) Error Differential Nonlinearity (DNL) Error -2 Offset Error Gain Error Touch Panel Drivers Switch On-Resistance XP, YP (RL=300Ω) 2.5 XN, YN (RL=300Ω) 2.5 PENIRQ Pull Up Resistor RIRQ 30 Auxiliary IN Input Input Voltage Range 0 Temperature Measurement Temperature Range -40 Resolution (Note 4) Accuracy (Note 5) Power Supply Current Normal Mode (Internal Oscillator mode) (Note 6) VDD=1.8V VDD=3.6V Normal Mode (Bus clock mode) PD0 = “0” (Note 7) VDD=1.8V VDD=3.6V Full Power Down ( PD0 = “0” Write ) Note 4. VDD=1.8V Note 5. +6°C (typ.) Offset Note 6. 1kHz 1.6Vpp (-1dB) IN/WIPER pin DOUT CL=0pF Note 7. 1kHz 1.6Vpp (-1dB) IN/WIPER pin DOUT CL=0pF DC (Ta=-40°C to 85°C, VDD =1.6V to 3.6V) Parameter Digital Input (CSN, SCLK, DIN) “H” level input voltage “L” level input voltage Input Leakage Current Digital Output (DOUT, PENIRQN) “H” level output voltage (@ Iout = -250μA) “L” level output voltage (@ Iout = 250μA) Tri-state Leakage Current All pins expect for XP, YP, XN, YN pins XP, YP, XN, YN pins VDD typ max Units 12 12 ±1 - ±2 +3 ±6 ±4 Bits Bits LSB LSB LSB LSB 5 5 50 15 15 70 Ω Ω KΩ VDD V 1.2 ±3 85 - °C °C °C 240 340 0 550 800 3 μA μA μA μA μA 0.6466 VDD COUNT bit = 0 INTERVAL=0μs EXT Clock 50μs 16SCLK (Logic I/O) Symbol min typ max Units VIH VIL IILK 0.8xVDD -10 - 0.2xVDD 10 V V μA VOH VOL IOLK VDD-0.4 - - 0.4 V V -3 -3 - 3 3 μA μA MS0954-J-05 2010/10 -5- [AK4185] (Ta=-40°C to 85°C, VDD=1.6V to 3.6V, CL=50pF) Parameter Symbol Internal OSCILLATOR Clock frequency fOSC Touch Panel (A/D Converter) Throughput Rate fs SCLK frequency fSCLK duty duty tTRK Sampling Time (Rin = 600Ω) (Note 8) Conversion Time tCONV CSN edge to First SCLK “↑” tCSS CSN edge to DOUT Tri-State Disabled tDCD SCLK High Pulse Width tCKH SCLK Low Pulse Width tCKL Data Setup Time tDS Data Valid to SCLK Hold Time tDH Data Output Delay after SCLK “↓” tDOD CSN “↑” to SCLK Ignored tCSI CSN “↑” to DOUT Hi-Z state tCCZ CSN Hold Time tCSW Note 8. 3tSCLK min typ max Units 2.5 3.6 5.1 MHz - 300 - kHz 50 - 5000 60 12 50 70 90 - KHz % μs 1/fSCLK ns ns ns ns ns ns ns ns ns ns 30 40 0.6 50 80 80 40 40 50 150 (tSCLK = 1/fSCLK) tCSW CSN 50%VDD tCKL tCSS tCSI tDOD tCKH SCLK 50%VDD tDH tDS PD0 50%VDD DIN tCCZ tDCD DOUT D11 D10 D0 VOH VOL Figure 2. Timing Diagram MS0954-J-05 2010/10 -6- [AK4185] ■ AK4185 z 1.6V z 4 /5 z AD z z AD z SPI™ I/F ■ AD A/D 12 bit A/D A/D 12 A/D (ΔVREF-1.5LSB) ~ ΔVREF (ΔVREF-2.5LSB) ~ (ΔVREF-1.5LSB) --------0.5LSB ~ 1.5LSB 0 ~ 0.5LSB Table 1 FFFH FFEH --------001H 000H ΔVREF: (VREF+) – (VREF-) Table 1. AD I/F A/D SCLK ΔVREF fOSC IN 8 A/D 12bit ■ (A2/1/0 bit) (X , Y (ΔVREF) ) (Z ) A/D A/D A/D A/D (ΔVREF) (ΔAIN) CSN (ΔAIN) VSS (IN,TEMP) VSS 5SCLK↓ 8CLK↓ AD MS0954-J-05 2010/10 -7- [AK4185] ■ 1. ( XP, XN YP) ) 2 VDD X-Plate XP-Driver SW ON XP AIN+ X-Plate YP-Driver SW ON XP Y-Plate VREF+ YP ADC VREF Y A/D VDD VREF+ ( X AIN+ YP ADC AIN- Y-Plate VREF- AIN- XN XN XN-Driver SW ON YN YN Touch Screen YN-Driver SW ON a) X-Position Measurement Differential Mode b) X-plate Y-Position Measurement Differential Mode Y-plate X+ X-Plate (Top side) X- Y-Plate (Bottom side) Y- Y+ c) 4-wire Touch Screen Construction Figure 3. 4 MS0954-J-05 2010/10 -8- [AK4185] 2. 5 5 ( ) 4 4 Y AD WIPER pin 2 VDD SW ON VDD AD Y 4 TR, TL (Y ) AD TL VSS VDD Switch VDD/VSS X Y SW TR VDD VDD VDD ON/OFF 2 BR, BL BL VSS VSS VSS ON/OFF VSS ON VSS BR VDD VSS Switch VDD/VSS Table 2. Driver SW configuration VDD VDD VDD TR SW ON VDD TL SW ON BR SW ON VREF+ BR TR TR SW ON WIPER AIN+ VREF+ ADC VREF TL TR AIN+ WIPER ADC TL AIN- AIN- VREF- BL TL SW ON BR BL SW ON BL BL SW ON BR SW ON a) X-Position Measurement Differential Mode b) Y-Position Measurement Differential Mode Top layer, Bottom layer (Top layer) ADC WIPER TL TR BL BR (Bottom Layer) 5-wire Touch Screen Construction Figure 4. 5 MS0954-J-05 2010/10 -9- [AK4185] ■ (4 ) YP VREF+ XN VREF- XP YN 2 2 X (Rx-plate) Z2 Z1 R TOUCH = R X -plate ⋅ X Position 4096 X X ⎛ Z2 ⎞ ⎜⎜ − 1⎟⎟ ⎝ Z1 ⎠ Y (Rxplate, Ryplate) Y Z1 R X-plate ⋅ X Position ⎛ 4096 ⎞ ⎛ Y ⎞ ⎜⎜ − 1⎟⎟ − R Y -plate ⋅ ⎜1 - Position ⎟ 4096 ⎝ 4096 ⎠ ⎝ Z1 ⎠ R TOUCH = VDD VDD ON ON YP XP VREF+ YP touch XP AIN+ ADC VREF+ AIN+ VREF- AIN- touch ADC VREF- AIN- XN XN ON ON YN a) YN b) Z1-Position Measurement Differential Mode Z2-Position Measurement Differential Mode Figure 5. MS0954-J-05 2010/10 - 10 - [AK4185] ■ i D = I0 ( ) ⋅e VD VT ⎛ k ⋅T ⎞ ⎟⎟ VT = ⎜⎜ ⎝ q ⎠ I0: q: 1.602189×10-19 ( k: 1.38054×10-23( V D: T: <1> ) ) Temp. Sensor I 80 1 TEMP0 TEMP1 Figure 6. AK4185 Figure 6 (1 2 2 2 ) 2 2 <1> ⎧ ( V (1)− V (80 ) ) ⎫ ⎛ I ⎞ ⎪ ⎪ ⎬ ⎨ ⎜ ⎟ VT ⎛ i D1 ⎞ ⎪⎭ ⎪ ⎜⎜ ⎟⎟ = ⎜ 1 ⎟ = 80 = e ⎩ ⎝ i D0 ⎠ ⎜⎜ I ⎟⎟ ⎝ 80 ⎠ q T[°C ] = ΔVbe ⋅ − 273 k ⋅ In(80) ΔVbe = V(1) − V(80 ) T[ ° C ] = 2.648 × 10 3 × ΔVbe − 273 <2> 1 ⎛ k ⎞ VD T = ⎜⎜ ⎟⎟ ⋅ <2> ⎝ q ⎠ In⎛⎜ i D ⎞⎟ ⎝ I0 ⎠ MS0954-J-05 2010/10 - 11 - [AK4185] ■ I/F AK4185 SPI™ 1.6V VDD=1.6V ~ 3.6V CSN SCLK AK4185 Micro- DIN Processor DOUT 4/5-wire touch panel PENIRQN Figure 7. I/F 1. A/D ( ) (1) (CONTINUE bit = “0”) DDLY bit = “0” ( ) CSN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 2122 23 24 SCLK S DIN “L” Command Byte DOUT (DDLY bit=0, MODE bit =0) 12bit A/D Data (1) (MSB First) Hi-Z DOUT (DDLY bit=0, MODE bit =1) 8bit A/D Data (1) (MSB First) Hi-Z Figure 8. DDLY bit = “1” ( ( Hi-Z Hi-Z : DDLY bit = “0”) ) CSN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 SCLK S DIN Command Byte “L” DOUT (DDLY bit=1, MODE bit =0) 12bit A/D Data (1) (MSB First) Hi-Z DOUT (DDLY bit=1, MODE bit =1) 8bit A/D Data (1) (MSB First) Hi-Z Figure 9. ( Hi-Z Hi-Z : DDLY bit = “1”) MS0954-J-05 2010/10 - 12 - [AK4185] (2) (CONTINUE bit = “1”) ) DDLY bit = “0” ( CSN ··· 104 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 2122 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 SCLK S DIN “L” Command Byte DOUT (DDLY bit=0, MODE bit =0) 12bit A/D Data (1) (MSB First) Hi-Z DOUT (DDLY bit=0, MODE bit =1) 12bit A/D Data (2) (MSB First) 8bit A/D Data (1) (MSB First) Hi-Z Figure 10. DDLY bit = “1” ( 12bit A/D Data (6) (MSB First) 8bit A/D Data (2) (MSB First) ( Hi-Z 8bit A/D Data (6) (MSB First) Hi-Z : DDLY bit = “0”, COUNT bit = “0”) ) CSN ··· 101 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 2122 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 SCLK S DIN “L” Command Byte DOUT (DDLY bit=1, MODE bit =0) 12bit A/D Data (1) (MSB First) Hi-Z DOUT (DDLY bit=1, MODE bit =1) 8bit A/D Data (1) (MSB First) Hi-Z Figure 11. 2. A/D 12bit A/D Data (2) (MSB First) 8bit A/D Data (2) (MSB First) ( ( 12bit A/D Data (6) (MSB First) 8bit A/D Data (6) (MSB First) Hi-Z Hi-Z : DDLY bit = “1”, COUNT bit = “0”) ) 3. CSN 1 2 3 4 5 6 7 8 SCLK R/W=“0” Command Byte DIN S 01 0 1 11 D7 D0 Figure 12. (2) A/D CSN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 2122 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 ··· 72 SCLK R/W=“1” Command Byte DIN S D7 DOUT (DDLY bit=0) 01 0 “L” 11 1 D0 12bit A/D Data (X) (MSB First) Hi-Z 12bit A/D Data (Y) (MSB First) 12bit A/D Data (Z1) (MSB First) 12bit A/D Data (Z2) (MSB First) Hi-Z DOUT (DDLY bit=1) Hi-Z 12bit A/D Data (X) (MSB First) Figure 13. 12bit A/D Data (Y) (MSB First) A/D MS0954-J-05 12bit A/D Data (Z1) (MSB First) 12bit A/D Data (Z2) (MSB First) Hi-Z (SEQM bit = “000”) 2010/10 - 13 - [AK4185] 3. Setup (1) Setup Write CSN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK R/W=“0” D3 Command Byte DIN S 01 0 Addr D7 DOUT 4. DIN “L” D0 Hi-Z Hi-Z 13SCLK 16SCLK (2) Setup D0 Data 15SCLK DIN Figure 14. Setup “L” “L” Write Read CSN 1 2 3 4 5 6 7 8 9 10 11 12 SCLK R/W=“1” Command Byte DIN S 0 10 D0 D3 D7 DOUT 5. DIN D0 Data Hi-Z 9SCLK 13SCLK “L” Addr DIN Figure 15. Setup 12SCLK “L” MS0954-J-05 Hi-Z “L” Read 2010/10 - 14 - [AK4185] ■ ADC 8 AK4185 Table 4 CSN = “L” SCLK SCLK AK4185 D7 S D6 A2 D5 A1 D4 A0 D3 MODE D2 x1 D1 x2 D0 PD0 Table 3. Command Byte definition (x1, x2: Don’t care) BIT D7 Name S D6-D4 A2-A0 D3 MODE D2 D1 D0 x1 x2 PD0 “H” ADC A/D 0: 12 1: 8 Don’t care Don’t care 12 /8 ( ) Table 4. Control Command definition (1) 4-wire touch panel configuration Channel Selection A2 A1 0 0 0 0 0 1 0 1 1 1 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Status of Driver Switch X-Driver Y-Driver OFF OFF OFF ON XN-ON XN-ON ON OFF OFF YP-ON YP-ON OFF OFF OFF ADC input (ΔAIN) AIN+ AINTEMP0 VSS XP YN XP YN YP IN TEMP1 XN XN XN VSS VSS Reference Voltage (ΔVREF) VREF+ VREFVREF VSS YP YN YP YP XP VREF VREF XN XN XN VSS VSS Note TEMP0 Y-axis Setup Command (Table 7) Z1 (Pressure) Z2 (Pressure) X-axis AIN TEMP1 Ref. Mode SER DFR DFR DFR DFR SER SER Table 5. Control Command List (4-wire) MS0954-J-05 2010/10 - 15 - [AK4185] (2) 5-wire touch panel configuration TR: VDD ON/OFF, BL: VSS ON/OFF Channel Status of ADC input Selection Driver Switch (ΔAIN) A2 A1 A0 TR-Driver BL-Driver AIN+ AIN0 0 0 OFF OFF TEMP0 VSS 0 0 1 ON ON WIPER BL 0 1 0 0 1 1 1 1 1 0 0 1 1 1 0 1 0 1 Reference Voltage (ΔVREF) VREF+ VREFVREF VSS TR BL - ON ON WIPER BL TR BL OFF OFF TEMP1 VSS VREF VSS Table 6. Control Command List (5-wire) ( Note Ref. Mode TEMP0 Y-axis Setup Command (Table 7) Reserved Reserved X-axis Reserved TEMP1 SER DFR DFR SER invalid) (3) Setup Command configuration BIT D7 NAME S D6-D4 D3-D1 A2-A0 Addr D0 R/W DESCRIPTION “H” Setup command. Must write “010” Addr Selection (Table 8) “000”: Function 1 (Table 9) “001”: Function 2 (Table 10) “010”: Function 3 (Table 11) “011”: Function 4 (Table 12) “111”: Command of internal clock mode READ/WRITE 0: Write (Addr bits = “111” 1: Read (Addr bits = “111” ) A/D ) Table 7. Setup Command description Setup Command Function Addr 00H 01H 02H 03H 04H 05H 06H 07H Note 9. “0” NAME Function 1 Function 2 Function 3 Function 4 Reserved Reserved Reserved Command D3 PANEL D2 CONTINUE SEQM[2:0] INTERVAL[2:0] SLEEP[1:0] 0 0 0 x “1” D1 COUNT D0 DDLY 0 0 SEQST[1:0] 0 0 0 x 0 0 0 x 0 0 0 x Table 8. Setup Command List (x: Don’t care.) MS0954-J-05 2010/10 - 16 - [AK4185] Function 1 [R/W]: BIT NAME D3 PANEL D2 CONTINUE D1 COUNT D0 DDLY Function 2 [R/W]: BIT NAME D3-D1 SEQM D0 Function 3 [R/W]: BIT NAME D3-D1 INTERVAL D0 Function 4 [R/W]: BIT NAME D3-D2 SLEEP D1-D0 SEQST / DESCRIPTION 4/5 0: 4 (default) 1: 5 / ( 0: (default) 1: ADC Conversion count 0: 6 times AD conversion (default) 1: 10 times AD conversion AD 0: (default) 1: Table 9. Setup Function 1 description ) DESCRIPTION Sequence Mode 000: X → Y → Z1 → Z2 Scan (4 001: X → Y Scan 010: X Scan 011: Y Scan 100: Z1 → Z2 Scan (4 ) 101: TEMP0 → TEMP1 110: A-IN (4 ) 111: Reserved Reserved Table 10. Setup Function 2 description ) (default) DESCRIPTION Sampling interval times. 000: 0μs (default) 001: 5μs 010: 10μs 011: 20μs 100: 50μs 101: 100μs 110: 200μs 111: 500μs Reserved Table 11. Setup Function 3 description / DESCRIPTION Sleep Command ( CSN=H ) 00: Normal Mode (default) 01: Sleep Mode 1 (PENIRQN disabled and output “H”. Touch Panel is open.) 10: Sleep Mode 2 (PENIRQN disabled and open. Touch Panel is open.) 11: Reserved Status Bits [Read only] 00: Not Busy 01: Sampling Wait 10: Sequence Busy 11: Data Available Table 12. Setup Function 4 description MS0954-J-05 2010/10 - 17 - [AK4185] ■ AK4185 20ms bit L (0.1V ) 2ms A/D 80%VDD PD0 8bit CSN = “H” CSN = “H” CSN = “H” CSN = “L” CSN = “L” 1 80%VDD 0.1V VDD 20ms (min) 2ms (max) CSN 50ms DIN C ontrol Command Setup F unction1 Setup Function2 Setup Function3 Setup Func tion4 Figure 16. ■ PD0 bit A/D A/D (X, Y, Z, TEMP, IN A/D PD0 bit = “0” ) PD0 bit = “1” ADC ON PD0 0 A/D CSN = “H” OFF 5 1 : BL pin ADC ON CSN = “L” A/D CSN = “H” OFF CSN = “H” (4 : YN pin A/D VSS) A/D VSS ON A/D (4 : YN pin VSS, 5 : BL pin VSS) CSN = “H” CSN = “L” Table 13. MS0954-J-05 2010/10 - 18 - [AK4185] ■ AK4185 Open SLEEP[1:0] SLEEP[1:0] CSN = “L” CSN = “H” SLEEP[1:0] CSN = “L” CSN = “H” 00 Disable (PENIRQN=H) Disable (PENIRQN=Hi-z) N/A 01 10 11 N/A Open Open Table 14. MS0954-J-05 2010/10 - 19 - [AK4185] ■ ( (DCLK) (1) ) A/D (CONTINUE bit = “0”) A/D CSN, SCLK, DIN, DOUT AK4185 7SCLK Figure 17 Figure 18 CSN pin ↓ 4 8 DIN = “L” “1” AD MSB 9SCLK↓ DOUT Hi-Z 8bit (S bit) 5SCLK↓~8SCLK↓ (tSam) SCLK 12bit or 8bit 15SCLK A/D ADC 8SCLK↓ “L” AD A/D CSN 1 2 3 4 5 A0 MO 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SCLK S DIN A2 A1 X1 X2 PD0 Hi-Z 11 10 9 8 7 6 S A2 A1 5 4 3 A0 2 MO X1 1 0 X2 PD0 11 10 DOUT Touch Screen Driver SW (Internal Node) (DFR Mode, PD0 =”0”) Figure 17. ( 12bit ) CSN 1 2 3 4 5 A0 MO 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SCLK S DIN A2 A1 Hi-Z X1 X2 PD0 7 6 5 4 3 2 S A2 1 0 A1 A0 MO X1 X2 PD0 7 6 DOUT Touch Screen Driver SW (Internal Node) (DFR Mode, PD0 =”0”) Figure 18. ( MS0954-J-05 8bit ) 2010/10 - 20 - [AK4185] (2) (CONTINUE bit = “1”) A/D Hi-Z Figure 19 Figure 20 AK4185 8bit 5SCLK↓~8SCLK↓ (tSam) ADC SCLK 9SCLK↓ AD “L” AD DDLY bit = “0” COUNT bit MSB 12SCLK↓ MSB CSN pin ↓ DOUT 8bit 12bit 16SCLK 8SCLK↓ (12bit ) CSN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 9 8 7 6 5 20 21 22 23 2 1 24 25 26 27 28 37 29 38 39 40 41 42 SCLK S DIN A2 A1 A0 MO X1 X2 PD0 Hi-Z 11 10 DOUT 4 3 0 11 3 Data 1 2 1 0 11 10 9 8 Data 2 7 6 5 4 3 2 1 0 Data n Touch Screen Driver SW (Internal Node) (DFR Mode, PD0 =”0”) 16SCLK 16SCLK Figure 19. DDLY bit = “1” COUNT bit MSB ( 9SCLK↓ MSB 9SCLK↓ : DDLY bit = “0”) 12bit 16SCLK (12bit ) CSN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 9 8 7 6 5 17 18 19 20 2 1 21 22 23 24 25 26 27 28 29 37 8 0 38 39 40 41 42 SCLK S DIN A2 A1 Hi-Z A0 MO X1 X2 PD0 11 10 DOUT 4 3 0 11 Data 1 10 9 11 Data 2 10 9 8 7 6 5 4 3 2 1 0 Data n Touch Screen Driver SW (Internal Node) (DFR Mode, PD0 =”0”) 16SCLK 16SCLK Figure 20. PD0 bit = “1” = “0” = “0”) 96SCLK↑ COUNT bit = “1” 161SCLK↑(COUNT bit = “1”) ( ADC :DDLY bit = “1”) ADCON COUNT bit 97SCLK↑(COUNT bit 160SCLK↑ (16SCLK MS0954-J-05 ) 2010/10 - 21 - [AK4185] ■ ( ) (OSCLK) A/D (10101110b) PENIRQN “L” OSC PENIRQN↑ 2.8µs(typ) PENIRQN↑ SEQM[2:0] PENIRQN↑ PENIRQN OSC Status SEQST[1:0] (10101111b) Pen ADC SEQM[1:0] “0” 1 PENIRQN↑ Status SEQST[1:0] “11” (Data Available) Pen Touch Sequence Start Set PENIRQN Low Start Clock Driver Set Wait Timer ADC No Count End? Yes Sequence End? No Yes Set PENIRQN High Stop Clock & PenTouch Enable Done Figure 21. MS0954-J-05 2010/10 - 22 - [AK4185] PENIRQN 2.8us CSN SCLK S Sequent ial Mode W DIN S=1 DOUT = “010111” W=0 Hi-Z OSCLK Internal Sequence (SEQM2-0 bits=“001”, X - Y Scan) PEN Touch Wait Tracking, Conversion (X-axis 1st) Tracking, Conversion (X-axis 2nd) Tracking, Conversion (X-axis nth) 20 OSCLK 20 OSCLK 20 OSCLK Tracking, Conversion (Y-axis 1st) Tracking, Conversion (Y-axis nth) 20 OSCLK 20 OSCLK Wait PENIRQN Enable Data Available Figure 22. ( (X-Y Scan: SEQM2-0 bits = “001”) Data Available) PENIRQN 2.8us (typ) CSN SCLK S Sequential Mode R DIN DOUT (DDLY bit=0) DOUT (DDLY bit=1) S=1 = “010111” R=1 0 00 0 Hi-Z 0 Hi-Z X-axis 12bit A/D-data X-axis 12bit A/D-data 0000 000 0 Y-axis 12bit A/D-data Y-axis 12bit A/D-data 000 Data Available 16 SCLK Figure 23. (Data Available A/D 16 SCLK (X-Y Scan: SEQM2-0 bits = “001”) Read) A2-0, MODE, PD0 bits CSN = “H” SLEEP mode SLEEP mode SLEEP mode (CSN = “H” ) MS0954-J-05 2010/10 - 23 - [AK4185] ■ 4 4 XP pin PENIRQN 5 WIPER pin XP pin 5 4 (Ri)--- (X+)---(Y-) CSN = “H” PENIRQN “L” ) VSS 4 (VDD)--- “H” ( ( CSN = “L” 8SCLK↑ bit BL pin 2 (VDD)--- (Ri)--- (WIPER)---(BL) PENIRQN “L” 5 PENIRQN A/D YN pin 5 (RIRQ: typ.50K ) WIPER pin PD0 bit ( ) PENIRQN ( PD0 bit CSN = “L” PD0 bit ) PD0 Setup Disable ) i. CSN = “L” 5SCLK↓ PENIRQN PD0 bit “0” “H” PENIRQN Y Z1 Z2 5 WIPER) ( IN) “H” ii. bit CSN = “L” 5SCLK↓ PD0 bit “L” PD0 bit “1” (X “L” 20SCLK↓ (8bit mode PD0 bit 16SCLK↓) PENIRQN “L” IN “H” “H” iii. PD0 PD0 “0” PD0 CSN = “L” 20SCLK↓(8bit mode PENIRQN “0” “H” PD0 bit PENIRQN “L” “1” 16SCLK↓) PD0 bit “L” “1” IN “H” A/D CSN “L” PEN ADC mode PD0 bit = “0” 1SCLK PD0 bit = “1” 5SCLK↓ 21SCLK↓ (20SCLK↓ 21SCLK↓ ADC mode MS0954-J-05 ) 2010/10 - 24 - [AK4185] PENIRQN VDD VDD RIRQ = VDD EN2 50kΩ XP/WIPER Driver OFF EN1 YN/BL Driver ON Figure 24. (WIPER i ) iii ii CSN 1 2 3 4 5 A0 MO 6 7 8 9 10 11 12 13 14 15 16 9 8 7 6 5 17 18 19 20 21 22 23 24 SCLK DIN S A2 A1 X1 X2 PD0 11 10 4 3 2 1 0 DOUT CONV Internal Figure 25. MS0954-J-05 2010/10 - 25 - [AK4185] Figure 26 Figure 27 <4 (AKD4185) > 4-wire Analog Ground Touch Screen Digital Ground 0.01µ * 0.01µ * 0.01µ * 0.01µ * XP YP XN YN Top View Analog Supply 1.6∼3.6V 10µ + 0.1µ VDD CSN DIN VSS IN PENIRQN DOUT SCLK Auxiliary Analog Input µP Figure 26. : - AK4185 VSS (CSN, SCLK, DIN pins) AK4185 DOUT pin 100kΩ MS0954-J-05 DOUT pin Hi-Z AK4185 2010/10 - 26 - [AK4185] <5 > 5-wire Analog Ground Touch Screen Digital Ground 0.01µ * 0.01µ * 0.01µ * 0.01µ * BR TR TL BL Top View Analog Supply 1.6∼3.6V 10µ + VDD CSN DIN VSS WIPER PENIRQN DOUT SCLK 0.1µ 0.01µ * µP Figure 27. : - AK4185 VSS (CSN, SCLK, DIN pins) AK4185 DOUT pin 100kΩ DOUT pin Hi-Z AK4185 6. VDD VSS PC 7. RF XP, XN, YP, YN RF (* 0.01μF) XP, XN, YP, YN MS0954-J-05 2010/10 - 27 - [AK4185] 12pin CSP: 1.96mm x 1.46mm Top View Bottom View 1.96 ± 0.05 A 0.5 3 4185 XXXX 2 1 A B C B 3 1.46 ± 0.05 2 1 D D C B A 0.65± 0.05 φ 0.3 ± 0.05 φ 0.05 M S AB 0.25 ± 0.05 S 0.08 S ■ : : SnAgCu MS0954-J-05 2010/10 - 28 - [AK4185] 4185 XXXX A1 XXXX: Date code identifier (4 Pin #A1 indication MS0954-J-05 ) 2010/10 - 29 - [AK4185] Date (YY/MM/DD) 08/05/09 10/01/25 Revision 00 01 Reason Page 12, 13, 14 Contents I/F Figure 8~15 18 Figure 16 10/04/22 02 1, 20, 22 5 Touch panel drivers switch on-resistance Min/Max : 2.5Ω (min), 15Ω (max) 10/05/31 03 5 PENIRQ Pull Up Resistor RIRQ Min/Max : 30kΩ (min), 70kΩ (max) 10/10/01 04 5 Touch panel drivers switch on-resistance : RL=300Ω DC Tri-state Leakage Current max: 10μA → 3μA min: -10μA → -3μA 5 10/10/19 05 28 z z z z z z MS0954-J-05 2010/10 - 30 -