[AK4184A] AK4184A TSC with Keypad Scanner and GPIO Expander AK4184A 4 GPIO 12 A/D IC PWM X /Y 6x5 GPIO 8 I/O AK4184A AD 2.5V 125kHz I/F 1.6V DSC, DVC, Smart Phone, MP3 player ■ SPI Serial ■ 12bit ADC (S/H ■ ■ 125KHz (max) ■ ■ 6 x 5 keypad ■ 8 GPIO ■ LED (PWM) ■ : AVDD = 2.5V ~ 3.6V ) IOVDD = 1.6V ~ AVDD : 400μA ■ ■ Package: 41pin BGA (4mm x 4mm, pitch: 0.5mm) MS0947-J-00 -1- 2008/04 [AK4184A] C1 C2 C3 C4 C5 C6 R1 R2 R3 R4 GP0 GP1 GP2 GP3 R5 GP4 Keypad Scanner GPIO I/F GP5 GP6 XP GP7 YP IOVDD Control Logic XN SCLK CSN YN DOUT VREF+ Serial Data I/F and Level Shifter VREF- DIN BUSY KEYIRQN AIN+ AIN- 12bit ADC (SAR type) PENIRQN PW M G e n e r a to r BRCONT PEN and Keypad INTERRUPT OSCILLATOR AVDD VSS1 RESETN VSS2 Figure 1. MS0947-J-00 -2- 2008/04 [AK4184A] ■ AK4184AEG AKD4184A −40 ∼ +85°C AK4184A 41pin BGA (4mm x 4mm, 0.5mm pitch) ■ 7 6 AK4184AEG 5 Top View 4 3 2 1 A 7 6 5 4 3 2 1 NC C1 R4 R3 VSS2 IOVDD NC A C3 C4 C2 R5 R2 R1 KEYIRQN B B C D E F G C5 C6 BRCONT GP0 GP1 GP2 VSS2 BUSY DOUT C DIN SCLK D CSN RESETN E GP3 GP5 GP7 XP XN PENIRQN VSS1 F NC GP4 GP6 AVDD YP YN NC G TOP View MS0947-J-00 -3- 2008/04 [AK4184A] No. A1 Pin Name NC I/O - B1 KEYIRQN O C2 BUSY O C1 DOUT O D2 DIN I D1 E2 SCLK CSN I I E1 F2 RESETN PENIRQN I O G1 NC - F1 G2 VSS1 YN I/O F3 XN I/O G3 YP I/O F4 XP I/O G4 AVDD MS0947-J-00 - Function No Connection No internal bonding. This pin should be open or connected to the ground. Keypad Interrupt (Active Low) CSN pin = “H” Enable “L” “H” Disable “H” BUSY output “H” MSB “H” Serial Data Output SCLK pin ↓ CSN pin = “L” “L” CSN pin = “H” Hi-Z Serial Data Input SCLK pin ↑ “L” External Clock Input Chip Select Input (Active Low) CSN pin = “L” Device Reset (Active Low) Pen Interrupt Output (Active Low) CSN pin = “H” Enable “L” “H” CSN pin = “H” Disable “H” CSN pin = “L” No Connection No internal bonding. This pin should be open or connected to the ground. Analog Ground Touch Screen Y- plate Voltage supply Y : YX : OPEN : Z2 ADC : GND Touch Screen X- plate Voltage supply X : XY : OPEN : X : OPEN Touch Screen Y+ plate Voltage supply Y : Y+ X : ADC : Y+ : OPEN Touch Screen X+ plate Voltage supply X : X+ Y : ADC : Z1 ADC : 50kΩ Analog Power Supply: 2.5V ~ 3.6V -4- 2008/04 [AK4184A] F5 G5 F6 G6 G7 GP7 GP6 GP5 GP4 NC I/O I/O I/O I/O - F7 E6 E7 D6 D7 C6 C7 B6 A7 GP3 GP2 GP1 GP0 BRCONT C6 C5 C4 NC I/O I/O I/O I/O O O O O - B7 B5 A6 B4 A5 C3 A4 B3 A3 B2 A2 C3 C2 C1 R5 R4 VSS2 R3 R2 VSS2 R1 IOVDD MS0947-J-00 O O O I I I I I - GPIO7 pin GPIO6 pin GPIO5 pin GPIO4 pin No Connection No internal bonding. This pin should be open or connected to the ground. GPIO3 pin GPIO2 pin GPIO1 pin GPIO0 pin Pulse width modulated output signal Keypad Column 6 Keypad Column 5 Keypad Column 4 No Connection No internal bonding. This pin should be open or connected to the ground. Keypad Column 3 Keypad Column 2 Keypad Column 1 Keypad Row 5 Keypad Row 4 Digital I/O Ground Keypad Row 3 Keypad Row 2 Digital I/O Ground Keypad Row 1 Digital I/O Power Supply: 1.6V ~ AVDD -5- 2008/04 [AK4184A] ■ Digital GP0 ~ GP8, R1 ~ R5 C1 ~ C6, BRCONT (VSS1, VSS2 = 0V: Note 1) Parameter Power Supply Analog (Note 2) Digital I/F Input Current (any pins except for supplies) Analog Input Voltage (Note 3) Digital Input Voltage (Note 4) Touch Panel Drive Current Ambient Temperature (power supplied) Storage Temperature Symbol AVDD IOVDD IIN VINA VIND IOUTDRV Ta Tstg min -0.3 -0.3 -0.3 -0.3 -40 -65 max 6.0 6.0 ±10 AVDD+0.3 or 6.0 IOVDD+0.3 or 6.0 50 85 150 Note 1. Note 2. VSS1 VSS2 Note 3. XP, YP, XN, YN pin max (AVDD+0.3)V 6.0V Note 4. DIN, CSN, SCLK, RESETN, R1 ~ R5, GP0 ~ GP7 pins. max (IOVDD+0.3)V Open Drain GP0 ~ GP7 pins, BRCONT pin (IOVDD+0.3)V Units V V mA V V mA °C °C 6.0V : (VSS1, VSS2 = 0V: Note 1) Parameter Power Supply Digital I/O Power Supply Note 1. Symbol AVDD IOVDD min 2.5 1.6 typ 3.3 3.3 max 3.6 AVDD Units V V : MS0947-J-00 -6- 2008/04 [AK4184A] (Ta = -40°C to 85°C, AVDD = IOVDD = 3.3V, fs = 125 KHz, fSCLK = 5MHz) Parameter min ADC for Touch Screen Resolution No Missing Codes 11 Integral Nonlinearity (INL) Error Differential Nonlinearity (DNL) Error Offset Error Gain Error Touch Panel Drivers Switch On-Resistance XP, YP, RL = 300Ω XN, YN, RL = 300Ω XP Pull Up Resistance (when pen interrupt enable) Power Supply Current Touch Screen only fs = 125KHz (PD bit = “0”) Touch Screen only fs = 125KHz (PD bit = “1”) Oscillator on, Touch Screen Driver off, A/D power down Full Power Down (all blocks power down when CSN = “H”, RESETN = “H”) DC max Units 12 12 ±1 - ±2 ±6 ±4 Bits Bits LSB LSB LSB LSB 10 10 50 - Ω Ω KΩ 400 500 72 0 680 850 120 5 μA μA μA μA (Logic I/O) (Ta = -40°C to 85°C, IOVDD = 1.6V to 3.6V) Parameter Symbol min Digital Input (CSN, SCLK, DIN, R1 ~ R5, GP0 ~ GP7 pins) “H” level input voltage VIH 0.8xIOVDD “L” level input voltage VIL Input Leakage Current IILK -10 Digital Output (DOUT, BUSY, BRCONT, PENIRQN, KEYIRQN pins) VOH IOVDD-0.4 “H” level output voltage (@ Iout = -250μA) VOL “L” level output voltage (@ Iout = 250μA) Digital Output (GP0 ~ GP7 pins) “H” level output voltage (@ Iout = -1.5mA) VOH IOVDD-0.4 “L” level output voltage (@ Iout = 1.5mA) VOL Digital Output (C1 ~ C6 pins) “H” level output voltage (@ Iout = -1.5mA) VOH IOVDD-0.4 Resistance Rkey Pulldown Resistance (R1 ~ R5 pins) Rgp Pulldown Resistance (GP0 ~ GP7 pins @ input) Tri-state Leakage Current IOLK All pins except for XP, YP, XN, YN pins -10 XP, YP, XN, YN pins -50 MS0947-J-00 typ -7- typ max Units - 0.2xIOVDD 10 V V μA - 0.4 V V - 0.4 V V - - V 16 1000 - KΩ KΩ - 10 50 µA µA 2008/04 [AK4184A] (Ta = -40°C to 85°C, AVDD = 2.5V to 3.6V, IOVDD = 1.6V to AVDD, CL = 20pF) Parameter Symbol min typ Internal oscillator frequency fosc 0.9 1.3 Touch Panel (A/D Converter) SCLK period tCP 200 tSam 1.5 Sampling Time (Rin = 600Ω) Throughput Rate fs Conversion Time tCONV 24 Timing Characteristics SCLK Pulse Width Low tCKL 80 Pulse Width High tCKH 80 CSN “↓” to First SCLK “↓” tCSS 300 CSN “↓” to DOUT Tri-State Disabled tDV Data Setup Time tDS 40 Data Hold Time tDH 40 Data Output Delay after SCLK “↓” tDD CSN “↑” to DOUT Hi-Z state tCDZ tCSW 150 CSN H” Time SCLK “↑” to CSN “↑” tCSH 50 Reset Timing RESETN Pulse Width (Note 5) tRST 20 Note 5. RESETN pin = “L” max 1.7 Units MHz 1000 125 - ns µs KHz tCP 50 50 70 - ns ns ns ns ns ns ns ns ns ns - µs tCSW VIH VIL CSN tCP tCSH tDD tCKH tCSS VIH VIL SCLK tCKL tDS tDH VIH VIL DIN tCDZ tDV DOUT D11 Hi-Z D10 D0 Hi-Z 50%IOVDD Figure 2. Timing Diagram tRST RESETN VIL Figure 3. Power-down & Reset Timing MS0947-J-00 -8- 2008/04 [AK4184A] ■ AK4184A ●4 ●6 x5 ● 8 GPIO pin ● LED PWM ● AD ● ● 4 SPI™ SPI™ Motorola Inc. ■ A/D 12 bit A/D A/D 12 A/D Table 1 (ΔVREF - 1.5LSB) ~ ΔVREF (ΔVREF - 2.5LSB) ~ (ΔVREF - 1.5LSB) --------0.5LSB ~ 1.5LSB 0 ~ 0.5LSB ΔVREF: (VREF+) – (VREF-) Table 1. MS0947-J-00 -9- FFFH FFEH --------001H 000H 2008/04 [AK4184A] ■ (X Y ) A/D (X ΔVREF = VXP - VXN) (VXP) (X = (AIN+) - (AIN-)) (ΔVREF) (VXN) ΔAIN = VYP – VXN) A/D (ΔAIN ( ADC X ) 125kHz Y 2 A/D AVDD AVDD X-Plate XP-Driver SW ON XP VREF+ AIN+ X-Plate YP-Driver SW ON XP Y-Plate YP ADC VREF- 1.5μs VREF+ AIN+ VREF- AIN- ADC AINXN Y-Plate YP XN XN-Driver SW ON YN a) YN-Driver SW ON X-Position Measurement Differential Mode b) X-plate YN Touch Screen Y-Position Measurement Differential Mode Y-plate XP X-Plate (Top side) XN Y-Plate (Bottom side) YN YP c) 4-wire Touch Screen Construction Figure 4. MS0947-J-00 -10- 2008/04 [AK4184A] ■ YP pin VREF+ XN pin VREF- XP pin YN pin 2 X (Rxplate) Z2 Z1 Rtouch = (Rxplate) * (Xposition/4096) * [(Z2/Z1) – 1] X X Y Y (Rxplate, Ryplate) Z1 Rtouch = (Rxplate * Xposition/4096) * [(4096/Z1) – 1] – Ryplate * [1 – (Yposition/4096)] AVDD AVDD YP-Driver SW ON YP-Driver SW ON YP XP VREF+ AIN+ VREF- AIN- YP Rtouch ADC XP VREF+ AIN+ VREF- AIN- Rtouch ADC XN XN XN-Driver SW ON XN-Driver SW ON YN a) YN b) Z1-Position Measurement Z2-Position Measurement Figure 5. MS0947-J-00 -11- 2008/04 [AK4184A] ■ AK4184A 6 x5 6 x5 ■ C1 ~ C6 pins “H” R1 ~ R5 pins R1 ~ R5 pins “H” High KEYIRQN pin KEYIRQN pin Low (Rkey = 16KΩ, Figure 6) Low ( ) ■ AK4184A pin ON “H” R1 ~ R5 pins C1 pin R1 ∼ R5 pins (Sense Input 1) R1 ~ R5 pin R1 ∼ R5 pins (Column) Debounce Time MS0947-J-00 C1 (Scan Output 1) “H” “H” C2 ∼ C6 pins Hi-Z R1 ~ R5 pins “L” 2 C2 pin “H” (Scan Output 2) (Sense Input 2) Scan Output Sense Input Scan Output/ Sense Input -12- 1 2008/04 [AK4184A] Scan Output 6 Scan Output 5 Scan Output 4 Scan Output 3 Sense Input 1 through 5 Scan Output 2 Scan Output 1 Drive High or Hi-Z STATE Figure 6. Key Press Detection Circuitry and KEY No. Key pressed Rx Signal from keypad Debounce Scan Store the Key value in the KPDATA1, the KPDATA2 Register Key debounce time interval Time Oscillator startup Figure 7. Debounce Time Interval MS0947-J-00 -13- 2008/04 [AK4184A] ■ I/F AK4184A SPI I/F IOVDD 1.6V Touch Panel AVDD=2.5V ~ 3.6V X-Plate (Top side) IOVDD AK4184A XP CSN TP Interface XN YN YP IOVDD=1.6V~AVDD SCLK KP Interface DIN GPIO port DOUT BRCONT PENIRQN KEYIRQN μP Y-Plate (Bottom side) 8 GPIO 6x5 KEYPAD LED Driver Figure 8. SPI I/F pin (CSN, SCLK, DIN, DOUT pins) SCLK pin ↑ 16bit I/F SCLK pin ↓ CSN pin ↓ CSN pin ↑ 5MHz(max) RESETN pin = “L” LSB 8 Table 2 8bit Keypad, GPIO, LED 8 “0” S bit 16bit 16bit SCLK pin MSB 8bit “0” “1” 3 W/R bit PAGE bit 1bit Table 3 6bit Table 4 MS0947-J-00 -14- 2008/04 [AK4184A] D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Touch Screen Control Command Byte Other(Keypad, GPIO, LCD bias) Control Command Byte S A1 A0 PD x x x x W/R PAGE ADDR[5:0] MSB LSB Table 2. AK4184A (x: don’t care) PAGE Description 0 Data Register 1 Control Register Table 3. Page Address PAGE Addr Register Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 00H KPDATA1 DERR KD3[4] KD3[3] KD3[2] KD3[1] KD3[0] KD2[4] KD2[3] KD2[2] KD2[1] KD2[0] KD1[4] KD1[3] KD1[2] KD1[1] KD1[0] 0 01H KPDATA2 SERR KS2[4] KS2[3] KS3[2] KS3[1] KS3[0] KS2[4] KS2[3] KS2[2] KS2[1] KS2[0] KS1[4] KS1[3] KS1[2] KS1[1] KS1[0] 0 02H -FH Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10H GPLR 0 0 0 0 0 0 0 0 GPD7 GPD6 GPD5 GPD4 GPD3 GPD2 GPD1 GPD0 0 11H -3FH Resverved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 00H KEY KST1 KST0 DBN2 DBN1 DBN0 HLD2 HLD1 HLD0 0 0 0 0 0 0 0 0 1 01H KPMASK1 0 KM15 KM14 KM13 KM12 KM11 KM10 KM9 KM8 KM7 KM6 KM5 KM4 KM3 KM2 KM1 1 02H KPMASK2 0 KM30 KM29 KM28 KM27 KM26 KM25 KM24 KM23 KM22 KM21 KM20 KM19 KM18 KM17 KM16 1 03H KPColumnMask 0 0 0 0 0 0 0 0 0 0 CM6 CM5 CM4 CM3 CM2 CM1 04H KPScanInitiate 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 05H -07H Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 08H PDCTRL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KPPD TPPD 1 09H -0FH reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 10H GPSCR 0 0 0 0 0 0 0 0 SC7 SC6 SC5 SC4 SC3 SC2 SC1 SC0 1 11H GPDR IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 0 0 0 0 0 0 0 0 1 12H GPPU PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 0 0 0 0 0 0 0 0 1 1 13H GPSR PS7 PS6 PS5 PS4 PS3 PS2 PS1 PS0 0 0 0 0 0 0 0 0 1 14H -17H Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 18H PWMCTL LPU 0 0 BRV[4] BRV[3] BRV[2] BRV[1] BRV[0] 0 PACT 0 0 0 DIV2 DIV1 DIV0 1 19H -3FH Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 4. AK4184A Register Map MS0947-J-00 -15- 2008/04 [AK4184A] ■ RESETN pin AK4184A OFF(A1 bit = A0 bit = PD bit= “0”) AVDD IOVDD “L” (0000H) X ■ ADC ADC 12bit “0” Table 6, Table 7 Table 5 D15 S D14 A1 D13 A0 D12 PD D11 0 D10 0 D9 0 D8 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 Table 5. Touch Screen Command Word Format Bits 15 14:13 12 Name S A1-A0 PD “1” (Table 7) ADC (Table 8) 11:0 Reserved Table 6. Input S 1 1 1 1 A1 0 0 1 1 MS0947-J-00 A0 0 1 0 1 Status of Driver Switch XP XN YP YN ON ON OFF OFF OFF OFF ON ON OFF ON ON OFF OFF ON ON OFF Table 7. ADC input (ΔAIN) AIN+ AINYP XN XP YN XP(Z1) XN YN(Z2) XN -16- Reference Voltage (ΔVREF) VREF+ VREFXP XN YP YN YP XN YP XN Note X-axis Y-axis Z1 (Pen Pressure) Z2 (Pen Pressure) 2008/04 [AK4184A] ■ PD bit PD 0 1 Enabled OFF CSN pin = “H” ( YN OFF ON YN pin CSN pin = “L” GND ) CSN pin = “H” ON Disabled CSN pin ON PENIRQN pin “H” ON CSN pin Table 8. A/D MS0947-J-00 CSN pin = “H” CSN pin = “L” -17- 2008/04 [AK4184A] ■ A/D A/D AK4184A 4 (32SCLK) Figure 8 CSN pin ↓ DOUT Hi-Z DIN pin = “L” “1” (S bit) Sampling1 AD MSB A/D SCLK6 ↓ “L” AD SCLK20 ↓ Sampling2 SCLK 12bit PD bit A1 bit, A0 bit Sampling2 ( PD bit = “1” CSN pin ↓ SCLK pin ↓ ↓ SCLK6 ↓) (Sampling1) A1 bit A0 bit ( ) Sampling2 PD bit = “0” Sampling1 + Sampling2(CSN PD bit (A1 bit, A0 bit) Sampling1 PD bit = “1” Sampling2 ( PD bit = “0” SCLK ) ) Sampling2 PD bit = “1” CSN 1 2 3 4 5 6 7 8 9 14 16 17 18 19 20 21 22 23 24 25 29 30 31 32 SCLK A/D conversion DIN A1 A0 PD S 0 Control Command Hi-Z Hi-Z D11 D10 D9 D8 D4 D3 D2 D1 D0 DOUT A/D Data Touch Screen Driver SW Current PD bit Previous PD bit Sampling2 PD = “1” PD = “0” PD = “0” Sampling1 + Sampling2 PD = “1” PD = “1” PD = “0” Figure 9. Touch Screen Operation MS0947-J-00 -18- 2008/04 [AK4184A] ■ A/D YN pin GND PENIRQN pin 2 (Ri: typ.50KΩ) (Ri)--- (XP) -- ( PENIRQN pin “L” PENIRQN pin “H” PD = “1” PD = “0” XP pin XP pin (AVDD)--Ω ) -- (YN) 2 PENIRQN pin IOVDD “H” 3SCLK ↓ CSN ↑ (Figure 7) “H” “L” PD bit “H” PENIRQN pin (TPPD bit = “1”,Table 38) IOVDD AVDD PENIRQN AVDD Ri = 50kΩ EN Driver OFF XP YN Driver ON Figure 10. MS0947-J-00 -19- 2008/04 [AK4184A] ■ GPIO LED GPIO LED Table 10 Figure 11 MSB Figure 12 ( ) “0” Table 4 D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 Table 9. 1. Bits 7 Name W/R 6 PAGE 5:0 ADDR D8 0 D7 W/R GPIO Write/Read bit 0: Write 1: Read Page bit (Table 3 Address bit (Table 4 D6 PAGE D5 D4 D3 D2 D1 ADDR[5:0] D0 LED ) Table 10. Control Command Write Operation CSN 1 2 3 8 9 10 11 12 13 14 15 16 17 18 19 25 26 27 28 29 30 31 32 7 6 5 4 3 2 1 0 SCLK DIN ADDR[5:0] W/R Page 15 14 13 8 Control Data Control Command DOUT Hi-Z Hi-Z “0” Figure 11. Write Operation 2. Read Operation CSN 1 2 3 8 9 10 11 12 13 14 15 16 17 18 19 25 26 27 28 29 30 7 6 5 4 3 2 31 32 1 0 SCLK DIN W/R Page ADDR[5:0] Control Command DOUT Hi-Z 15 14 13 “0” 8 Hi-Z Read Data Figure 12. Read Operation MS0947-J-00 -20- 2008/04 [AK4184A] ■ AK4184A 6 x5 ■ KST1 bit = “0” (default) KST0 bit 2 ■ KST0 bit =“1” (KEYIRQN pin ↓) OSC KPScanInitiate (Page1 Address 04H) OSC ■ KST0 bit = “0” OSC (KPDATA1, KPDATA2) KEYIRQN pin ”H” Hold Hold Hold Hold Hold Hold Page0 Address00h 01h Keypad Control Register(KEY) Keypad Debounce Scan initiated by Host (Initial : KST1 bit="0", KST0 bit="1") Ry KEYIRQN BUSY CSN KPScanInitiate KPScanInitiate DIN KPDATA1,2 KPDATA1,2 DOUT State Key Detect Enable wait Debounce Scan HOLD Key Detect Disable Debounce Scan Key Detect Hold Enable then wait Read HOLD Read Hold Figure 13. Timing Diagram for keypad debounce scan initiated by Host (Initial : key interrupt enable, wait for Host instruction) MS0947-J-00 -21- 2008/04 [AK4184A] Keypad Debounce Scan initiated by keypad activity (Initial : KST1 bit="0", KST0 bit="0") Ry KEYIRQN BUSY CSN KPDATA1,2 DOUT Key Detect Enable State Debounce Scan Key Detect Disable HOLD Debounce Scan HOLD Key Detect Enable then wait Figure 14. Keypad Debounce Scan initiated by key activity (key interrupt enable, keyscan initiated by key touch) ■ Keypad Control Register (PAGE 1) (Table 12) Keypad Mask ( Register (Table 17), KPColumnMASK (Table 19) Host ) Keypad Mask Mask Addr NAME 00H KEY D15 MSB KST1 D14 D13 KST0 D12 DBN[2:0] D11 Keypad Column D10 D9 HLD[2:0] D8 D7 D6 D5 D4 D3 D2 D1 0 0 0 0 0 0 0 D0 LSB 0 Table 11. Keypad Control Register Format KST1 Bits 15 Name KST1 14 KST0 13:11 10:8 7:0 DBN HLD Description Key Interrupt enable ( enable) 0: enable 1: disable Key scan initiated by Host/Key 0: keyTouch Scan 1: Host Scan Keypad debounce time interval Keypad hold time control Reserved Table 12. Keypad Control Register (Write) KST0 Table 13 KST1 0 0 1 1 MS0947-J-00 KST0 0 1 0 1 Description Keypad Debounce scan is busy. Wait for the command initiated by Host No detect Data available Table 13. KST bit (Read) -22- 2008/04 [AK4184A] [DBN2:DBN0] DBN2 0 0 0 0 1 1 1 1 1ms DBN1 DBN0 Function 0 0 Debounce time: 1ms (default) 0 1 Debounce time: 2ms 1 0 Debounce time: 5ms 1 1 Debounce time: 10ms 0 0 Debounce time: 20ms 0 1 Debounce time: 50ms 1 0 Debounce time: 80ms 1 1 Debounce time: 100ms Table 14. Keypad Debounce Time Interval [HLD2:HLD0] HLD2 0 0 0 0 1 1 1 1 HLD1 0 0 1 1 0 0 1 1 HLD0 0 1 0 1 0 1 0 1 100μs Function Wait 100μs for next Debounce scan (default) Wait 1 debounce time interval to the next debounce scan Wait 2 debounce time interval to the next debounce scan Wait 3 debounce time interval to the next debounce scan Wait 4 debounce time interval to the next debounce scan Wait 5 debounce time interval to the next debounce scan Wait 6 debounce time interval to the next debounce scan Wait 7 debounce time interval to the next debounce scan Table 15. Keypad Hold Time Control ■ Keypad Mask Register (PAGE 1) Table 17 KPDATA2 Register Addr NAME D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 01H KPMASK1 0 KM15 KM14 KM13 KM12 KM11 KM10 KM9 KM8 KM7 KM6 KM5 KM4 KM3 KM2 KM1 02H KPMASK2 0 KM30 KM29 KM28 KM27 KM26 KM25 KM24 KM23 KM22 KM21 KM20 KM19 KM18 KM17 KM16 Table 16. Keypad Mask Register Format KMx 0 1 Description (default) Table 17. Keypad Mask bit Table 24 MS0947-J-00 KPMASK1, 2 0000H -23- 2008/04 [AK4184A] ■ Keypad Column Mask Register (PAGE 1) Addr NAME D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 03H KPColumnMASK 0 0 0 0 0 0 0 0 0 0 CM6 CM5 CM4 CM3 CM2 CM1 Table 18. Keypad Column Mask Resister Format CMx 0 1 Description (Column) (Column) Table 19. Keypad Column Mask bit (default) ■ Keypad Scan Initiate Command (PAGE 1) KST0 bit = “1” Host Write Keypad Data Register (KPDATA1, KPDATA2) Addr 04H NAME D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 KPScanInitiate X X X X X X X X X X X X X X X X Table 20. Keypad Scan Initiate Command Format MS0947-J-00 -24- 2008/04 [AK4184A] ■ Keypad Data Register (PAGE 0) 24) KD3, KS3 “1” Addr 00H 01H (#1 ~ 30:Table 3 KD1 ~ KD3, KS1 ~ KS3 NAME KPDATA1 KPDATA2 00H 2 0 4 KD1 ~ KD3, KS1 ~ KS3 KS1 ~ KS3 D15 DERR SERR D14 D13 D12 D11 KD3[4:0] KS3[4:0] KD1, KD2, KS1, KS2 (DERR bit, SERR bit) KD1 ~ KD3 column 31(1FH) column D10 D9 D8 D7 D6 KD2[4:0] KS2[4:0] D5 D4 D3 D2 D1 KD1[4:0] KS1[4:0] D0 Table 21. Keypad Data Register Format Bits 15 14:10 9:5 4:0 Name DERR KD3 KD2 KD1 Description Keypad scan data error Keypad scan result 3. can be masked by column mask Keypad scan result 2. can be masked by column mask Keypad scan result 1. can be masked by column mask Table 22. Keypad Data 1 Register (addr: 00H) Bits 15 14:10 9:5 4:0 Name SERR KS3 KS2 KS1 Description Keypad status data error Keypad status result 3. can be masked by both keymask and column mask Keypad status result 2. can be masked by both keymask and column mask Keypad status result 1. can be masked by both keymask and column mask Table 23. Keypad Data 2 Register (addr: 01H) C1 C2 C3 C4 C5 C6 #11 #16 #21 #26 R1 #1 #6 #12 #17 #22 #27 R2 #2 #7 #13 #18 #23 #28 R3 #3 #8 #14 #19 #24 #29 R4 #4 #9 R5 #5 #10 #15 #20 #25 #30 Table 24. Keypad to Key number Mapping MS0947-J-00 -25- 2008/04 [AK4184A] ■ GPIO controller AK4184A 8 pin (CMOS, pin GPSR ~ GP7 pins ) GPSCR GPPU pin CMOS I/O Pin Direction (GPDR) Pin Pull-up (GPPU) GPDR (pull-down, Hi-Z) GPLR GP0 pin Pin State (GPSR) Pin Set (GPSCR) GPIO Pin Pin Level (GPLR) Figure 15. GPIO ■ GPIO Pin Set/ Clear Register (PAGE 1) GPSCR pin (Table 28: IO bit = “1”) GPLR Addr 10H Name GPSCR D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 0 D7 SC7 D6 SC6 D5 SC5 D4 SC4 D3 SC3 D2 SC2 D1 SC1 D0 SC0 D4 0 D3 0 D2 0 D1 0 D0 0 Table 25. GPIO Pin Set/Clear Register Format Bits 15:8 7:0 Name Description Reserved Set GPIO Pin level for GPIO pins 0: Set pin level low (default) 1: Set pin level high Table 26. GPIO Pin Set/ Clear Register SC ■ GPIO Pin Direction Register (PAGE 1) GPDR Addr 11H Name GPDR D15 IO7 D14 IO6 D13 IO5 D12 IO4 D11 IO3 D10 IO2 D9 IO1 D8 IO0 D7 0 D6 0 D5 0 Table 27. GPIO Pin Direction Register Format Bits 15:8 7:0 MS0947-J-00 Name IO Description GPIO Direction select 0: GPIO pin configured as input. (default) 1: GPIO pin configured as output. Reserved Table 28. GPIO Direction Register -26- 2008/04 [AK4184A] ■ GPIO Pin Pull-up Register (PAGE 1) GPPU Addr 12H (CMOS Open-drain) Name GPPU D15 PU7 D14 PU6 D13 PU5 D12 PU4 (Table 28: IO bit = “1”) (IOVDD+0.3)V D11 PU3 D10 PU2 D9 PU1 D8 PU0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 D2 0 D1 0 D0 0 Table 29. GPIO Pin Pull-up Register Format Bits 15:8 Name PU Description GPIO Pullup register select 0: GPIO CMOS outputs (default) 1: GPIO Open drain outputs Reserved Table 30. GPIO Pin Pull-up Register 7:0 ■ GPIO Pin State Register (PAGE 1) GPSR Addr 13H (IO bit = “0”) Name GPSR D15 PS7 D14 PS6 D13 PS5 D12 PS4 D11 PS3 D10 PS2 D9 PS1 D8 PS0 D7 0 D6 0 D5 0 D4 0 D3 0 Table 31. GPIO Pin Sate Register Format Bits 15:8 Name PS 7:0 Description GPIO Pin state select 0: GPIO Pull-down (Rgp=1MΩ typ.) state (default) 1: GPIO pin Hi-Z state Reserved Table 32. GPIO Pin State Register ■ GPIO Pin Level Register (PAGE 0) (IO bit) Reserved 8 Addr 10H Name GPLR D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 0 D7 GPD7 “0” D6 GPD6 D5 GPD5 D4 GPD4 D3 GPD3 D2 GPD2 D1 GPD1 D0 GPD0 Table 33. GPIO Pin Level Register Format Bits 15:8 7:0 MS0947-J-00 Name 0 GPD Description Reserved GPIO Pin Level bits for GPIO pins 0: Pin state is low 1: Pin state is high Table 34. GPIO Pin Level Register -27- 2008/04 [AK4184A] ■ LED AK4184A LED LED IC PWM PWM (OSC) (fPWM) PWM PWM (typ.) fpwm PACT bit 32 PWM BRV bit DIV bit IOVDD (fpwm) 80Hz duty CMOS BRCONT pin fosc Oscillator LED duty fpwm Divider 2 fbrcont PWM Logic (DIV[2:0]+7) “L” BRCONT pin Controller Figure 16. PWM output block Example BRV [4:0] =11H PWM 0 1 2 3 8 9 10 11 12 13 14 15 16 17 18 8 24 25 26 27 28 29 30 31 0 (DIV[2:0]+7) PWM (fpwm) = fosc / 2 BRCONT Duty Cycle BRV[4:0] =11H Figure 17. PWM output waveform ■ PWM Control Register (PAGE 1) Addr Name 18H PWMCTRL D15 MSB LPU D14 D13 0 0 D12 D11 D10 BRV[4:0] D9 D8 D7 D6 D5 D4 D3 0 PACT 0 0 0 D2 D1 D0 LSB DIV[2:0] Table 35. PWM Control Register Format Bits 15 Name LPU 14:13 12:8 BRV 7 6 PACT 5:3 2:0 DIV MS0947-J-00 Description Output type Open drain/ CMOS 0: CMOS type (default) 1: Open Drain type Reserved Bright Control Value The period of “H” output level is (control value + 1) cycle in unit of (fpwm/32) Reserved Oscillator and PWM Logic Controller Power Up 0: Power Down State (default) 1: Normal mode (Oscillator power up and enable output) Reserved PWM clock divider index fpwm(typ.) = fosc/2 [DIV + 7] Table 36. PWM Control Register -28- 2008/04 [AK4184A] ■ Power Down Register (PAGE 1) (TPPD bit = “1”) PENIRQN pin OFF “H” (KPPD bit = “1”) Addr NAME D15 D14 D13 08H PDCTRL 0 0 0 C1 ~ C6 pins “L” D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 KPPD TPPD Table 37. Power Down Register Format Bits 15:2 1 0 Name Description Reserved KPPD 0: 1: (default) 0: 1: (default) TPPD Table 38. Power Down Register MS0947-J-00 -29- 2008/04 [AK4184A] Figure 18 (AKD4184A) LED Driver GPIO Keypad NC C3 C5 BRCONT GP1 GP3 NC C1 C4 C6 GP0 GP2 GP5 GP4 R4 C2 GP7 GP6 6x5 R3 0.1µ Digital I/O Supply 1.6∼AVDD + 10µ VSS2 R5 Top View R2 VSS2 IOVDD R1 BUSY NC KEYIRQN DIN AVDD XN YP CSN SCLK RESETN DOUT Analog Supply 0.1µ XP PEN IRQN YN VSS1 NC 0.01µ* 0.01µ* 0.01µ* 0.01µ* + 10µ 2.5∼3.6V 4-wire Touch Screen µP : - AK4184A VSS1, VSS2 (CSN, SCLK, DIN pins) AK4184A DOUT pin 100kΩ DOUT pin Hi-Z AK4184A Figure 18. ■ PCB VSS1 VSS2 PC RF RF XP, XN, YP, YN (*:Figure 18 GPIO (XP, XN, YP, YN, GP1-8, C1-6, R1-5 pins) MS0947-J-00 -30- 0.01μF) 2008/04 [AK4184A] ■ X-, Y- Coordinate measurements Cycle repeat CSN pin X, 0 X, 1 repeat X, 0 Y, 0 Y, 1 Y, 0 X: X-measurement, Y:Y-measurement. 0: PD bit = “0” setting, 1: PD bit = “1” setting. Figure 19. Timing Sequence for detecting X, Y position MS0947-J-00 -31- 2008/04 [AK4184A] ■ Keypad Scanner flowchart 1. Keypad Touch No Read KPDATA1,2 Register? Yes KEYIRQN pin Low Write KPScanInitiate Register Start Clock BUSY pin High Start Scanning & Debouncing keys Store scan results in KPDATA1, 2 Register BUSY pin Low Stop Clock KEYIRQN pin High Done Figure 20. Keypad scanner sequence initiated by Host command MS0947-J-00 -32- 2008/04 [AK4184A] 2. Keypad Touch No Read KPDATA1,2 Register? Yes KEYIRQN pin Low Start Clock BUSY pin High Start Scanning & Debouncing keys Store scan results in KPDATA1, 2 Register BUSY pin Low Stop Clock KEYIRQN pin High Done Figure 21. Keypad scanner sequence initiated by key press MS0947-J-00 -33- 2008/04 [AK4184A] FBGA (Unit: mm) 4.0 ± 0.1 41 - φ 0.3 ± 0.05 φ 0.15 A 41 M S AB 7 6 5 4 3 2 1 A B B D 3.0 4.0 ± 0.1 C E F G 0.5 0.5 3.0 0.89 ± 0.11 0.24 ± 0.06 S 0.08 S ■ : : BT : SnAgCu MS0947-J-00 -34- 2008/04 [AK4184A] 4184A XXXX Date Code: XXXX(4 digits) Pin #A1 indication Date (YY/MM/DD) Revision 08/04/16 00 MS0947-J-00 Reason Page -35- Contents 2008/04 [AK4184A] • • • • • • MS0947-J-00 -36- 2008/04