[AK4201] AK4201 Stereo Cap-less HP-Amp AK4201 2ch / AK4201 100dB PSRR(Power Supply Rejection Ratio) 2Vrms 12pin USON(2.2mm x 2.9mm) Stereo Cap-less Amplifier (No DC-blocking capacitors required) High PSRR (100dB at 217Hz) Output Power: 65 mW 2ch @ 16Ω, AVDD=PVDD=5.0V, THD+N=-60dB 30 mW 2ch @ 16Ω, AVDD=PVDD=3.3V, THD+N=-60dB Output Noise Level: 11 µVrms (Ri=20kΩ, Rf=30kΩ) Line-Out level: 2.0Vrms @ 5kΩ, AVDD=PVDD=5.0V 2.0Vrms @ 5kΩ, AVDD=PVDD=3.3V Regulator built-in THD+N: -60dB @ 16Ω, 50mW, AVDD=PVDD=5.0V -60dB @ 16Ω, 20mW, AVDD=PVDD=3.3V -100dB @ 5kΩ, 2Vrms, AVDD=PVDD=5.0V -100dB @ 5kΩ, 2Vrms, AVDD=PVDD=3.3V Low Power Shutdown Mode 0.1µA (typ) Mute -88dB ATT Pop noise free at power-ON/OFF Power Supply: 2.6V ~ 3.6V or 4.5V ~ 5.5V Ta: −40 ∼ 85°C Package: 12pin USON (2.2 x 2.9mm, 0.5mm pitch) MS1077-J-01 2011/02 -1- [AK4201] ■ Rf AVDD Ci Ri Regulator Amp LIN LOUT AK4201 VSS2 Regulator Ci Ri ROUT RIN Amp Charge Pump PVDD PDN VSS1 CP CN PVEE Rf Figure 1. AK4201 Block Diagram MS1077-J-01 2011/02 -2- [AK4201] ■ AK4201EU AKD4201 −40 ∼ +85°C AK4201 12pin USON (2.2mm x 2.9mm, 0.5mm pitch) ■ LIN 1 12 RIN LOUT 2 11 ROUT 10 PVEE Top View AVDD 3 VSS1 4 9 VSS2 PVDD 5 8 PDN CN 6 7 CP MS1077-J-01 2011/02 -3- [AK4201] No. 1 2 3 4 5 6 7 8 Pin Name LIN LOUT AVDD VSS1 PVDD CN CP PDN 9 VSS2 10 PVEE 11 ROUT 12 RIN Note. PDN pin I/O I O I O I O O I Function L-channel analog input L-channel analog output Headphone positive power supply pin Ground 1 pin Charge-pump positive power supply pin Negative charge-pump capacitor terminal pin Positive charge-pump capacitor terminal pin Power-down mode pin “H”: Power-up, “L”: Power-down Ground 2 pin Charge-pump circuit negative voltage output pin R-channel analog output R-channel analog input ■ Analog LIN, RIN, LOUT, ROUT Lch LOUT LIN MS1077-J-01 2011/02 -4- [AK4201] (VSS1=VSS2 =0V (Note 1)) Parameter Power Supplies: Analog (Note 2) Charge Pump Input Current, Any Pin Except Supplies Input Voltage (Note 3) Symbol AVDD PVDD IIN VIN min −0.3 −0.3 −0.3 Ambient Temperature (powered applied)(Note 4) Ta −40 Tstg −65 Storage Temperature Note 1. Units V V mA V °C °C PDN pin=“L” PDN pin=“L” PDN pin “H” Note 2. VSS1, VSS2 Note 3. LIN, RIN, PDN pin max (AVDD+0.3)V Note 4. max 6.0 6.0 ±10 (AVDD + 0.3) or 6.0 70(Note 5) 85(Note 6) 150 6.0V 150% Note 5. 2 Note 6. 2 65mW 50mW : (VSS1=VSS2 =0V (Note 1)) Parameter Symbol Power Analog, Charge Pump AVDD, PVDD Supplies (Note 7) Difference AVDD-PVDD min 4.5 2.6 -0.3 Symbol Ri Rf Gain min 10 10 -16 typ - max 100 100 16 Units k k dB RL CL Csum 16 - - 300 20 pF pF Parameter Input Resistor Feedback Resistor Gain Range Load Resistance (LOUT,ROUT pins) Capacitance (LOUT,ROUT pins) Capacitance (LIN,RIN pins) Note 7. AVDD PVDD 3.6V typ 5.0 3.3 0 max 5.5 3.6 0.3 Units V V 4.5V : MS1077-J-01 2011/02 -5- [AK4201] (AVDD=PVDD=5.0V) (AVDD=PVDD=5.0V; PDN=5.0V; Ta=25 ; VSS1=VSS2=0V; Input Signal Frequency =1kHz; Measurement band width=10Hz ∼ 20kHz; Gain=+3.5dB(Ri=20k ,Rf=30k ); Headphone-Amp: RL =16Ω; Charge Pump Circuit External Capacitance: C1=C2= 1μF (Figure 3), unless otherwise specified) Parameter min typ max Units Output Power 65 mW RL =16 , 0.68Vrms Input THD+N -60 dB 0.68Vrms Input; Po = 65mW @ RL =16 -60 -50 dB 0.60Vrms Input; Po = 50mW @ RL =16 -100 -90 dB 1.33Vrms Input; Vo = 2.0Vrms @ RL =5k S/N (Signal-to-Noise Ratio) 94 100 dB RL =16Ω (A-weighted) (Note 8) 100 106 dB RL =5kΩ (A-weighted) (Note 9) PSRR (Power Supply Rejection Ratio) (Note 10) 217Hz 100 dB 1kHz 90 dB Interchannel Isolation 60 80 dB RL =16 100 dB RL =5k mV 0 1 Output Offset Voltage 50 ms Start-up time (Note 11) Power Supplies 4.8 7.2 mA AVDD + PVDD (Normal Mode; No Output) 0.1 10 uA AVDD + PVDD (Power-Down Mode, PDN =0V) Note 8. 0.68Vrms Input (Po=65mW) Note 9. 1.33Vrms Input (Vo=2Vrms) Note 10. AVDD, PVDD 300mVpp Note 11. PDN pin= “H” AK4201 MS1077-J-01 2011/02 -6- [AK4201] (AVDD=PVDD=3.3V) (AVDD=PVDD=3.3V; PDN=3.3V; Ta=25 ; VSS1=VSS2=0V; Input Signal Frequency =1kHz; Measurement band width=10Hz ∼ 20kHz; Gain=+3.5dB(Ri=20k ,Rf=30k ); Headphone-Amp: RL =16Ω; Charge Pump Circuit External Capacitance: C1=C2= 1μF (Figure 3), unless otherwise specified) Parameter min typ max Units Output Power 30 mW RL =16 , 0.46Vrms Input THD+N -60 dB 0.46Vrms Input; Po = 30mW @ RL =16 -60 -50 dB 0.27Vrms Input; Po = 10mW @ RL =16 -100 -90 dB 1.33Vrms Input; Vo = 2.0Vrms @ RL =5k S/N (Signal-to-Noise Ratio) 90 96 dB RL =16Ω (A-weighted) (Note 12) 100 106 dB RL =5kΩ (A-weighted) (Note 13) PSRR (Power Supply Rejection Ratio) (Note 14) 217Hz 70 dB 1kHz 70 dB Interchannel Isolation 60 77 dB RL =16 100 dB RL =5k mV 0 1 Output Offset Voltage 50 ms Start-up time (Note 15) Power Supplies 3.8 5.7 mA AVDD + PVDD (Normal Mode; No Output) 0.1 10 uA AVDD + PVDD (Power-Down Mode, PDN =0V) Note 12. 0.46Vrms Input(Po=30mW) Note 13. 1.33Vrms Input (Vo=2Vrms) Note 14. AVDD, PVDD 100mVpp Note 15. PDN pin=”H” AK4201 MS1077-J-01 2011/02 -7- [AK4201] DC & (Ta= -40 ∼ 85°C; AVDD=PVDD=2.6 ∼ 3.6V or 4.5 ∼ 5.5V, Note 16) Parameter Symbol High-Level Input Voltage VIH Low-Level Input Voltage VIL Input Leakage Current Power-down (PDN pulse Width) Note 16. PDN pin min 1.6 - typ - max 0.5 Units V V 150 - ±2 - μA ns Iin tPD ■ tPD VIH PDN VIL Figure 2. Power-down Timing MS1077-J-01 2011/02 -8- [AK4201] ■ AK4201 (PVEE) Figure 3 ESR (Equivalent Series Resistance) (1uF 2.2uF, C1, C2 ±35%) 0.65uF Headphone-amp negative voltage PVEE pin C1: 1uF CN pin VSS1 Charge Pump Circuit C2: 1uF CP pin Figure 3. Charge Pump Circuit External Capacitor ■ (LOUT/ROUT pins) AVDD VSS1 (0V) min. 16 AK4201 MS1077-J-01 DC typ. 20 VSS1(0V) 2011/02 -9- [AK4201] ■ Power-Up/Down PDN pin = “L” (AVDD, PVDD) PDN pin “H” Power Supply (1) Form er Device DAC etc Power Up (No Signal Output) Don’t Care Ta (2) Former Device Click noise Normal Operation Don’t Care (4) A 0V PDN pin 0V (5) (3) PVEE pin LOUT/ROUT pins 0V PVEE pin Output =-3.3V(Typ.) Normal Operation(0V Common) 0V 0V Figure 4. Power-up/down Sequence example (1) PDN pin “L” “H” AK4201 150ns “L” PDN pin = “L” (AVDD, PVDD) (2) AK42 DAC AK4201 (MUTE) (DC (Ci) (Ri) HPF Normal Operation Ta : Ci = 0.22uF, Ri = 20k =0.22u * 20k = 4.4ms Ta = * 7.6 = 33ms ( (3) PDN pin = “H” Max.50ms AK4201 Normal O eration (4) AK4201 Normal Operation MUET (5) PDN pin = “L” LOUT/ROUT pins typ. 20 typ. 17.5k PDN pin “H” PDN pin “L” ) Figure 4 Ta =2V, VSS1 0V MS1077-J-01 “H” AK4201 A 1mV AK4210 7.6* PVEE pin PVEE pin PDN pin 150ns ) “L” 2011/02 - 10 - [AK4201] Ci Ri Analog Input 0.22µ Power Supply 4.5∼5.5V, 2.6∼3.6V 20k + 10µ 10µ + Ri Top View 1 LIN Ci RIN 12 Rf 30k Rf 30k 2 LOUT ROUT 11 3 AVDD PVEE 10 4 VSS1 VSS2 9 5 PVDD PDN 8 20k 0.1µ 0.22µ Analog Input 1µ (+) 0.1µ Power Supply 4.5∼5.5V, 2.6∼3.6V 6 CN DSP or μP CP 7 1µ (+) Figure 5. Note: 1. PDN= “L” PDN= “H” Power-Up/Down 1) PDN pin = “L” PDN pin = “L” 150ns PDN pin = “H” 2) PDN pin = “L” 2. CP pin CN pin VSS1 pin PVEE pin ±35%) 3. LIN pin, RIN pin 4. LIN pin, RIN pin 1uF Ri 2.2uF ( Rf DC MS1077-J-01 2011/02 - 11 - [AK4201] 12pin USON (2.2mm x 2.9mm, 0.5mm pitch) 0.225 ± 0.05 2.9 ± 0.05 2.9± 0.05 ∅ 0.50 Exposed Pad 0.08 ± 0.05 0.175 ± 0.05 2.6 ± 0.05 1.35 ± 0.05 2.2 ± 0.05 2.2 ± 0.05 0.5 0.25 ± 0.05 S M Au: 0.1um< 0.6MAX Ag: 2.5um< Ni: 65 ± 15um 0.05 0.05 S MS1077-J-01 2011/02 - 12 - [AK4201] 4201 XXXX 1 XXXX: Date code (4 digit) Date (YY/MM/DD) 09/05/12 11/02/03 Revision 00 01 Reason Page Contents 12 MS1077-J-01 2011/02 - 13 - [AK4201] z z z z z z MS1077-J-01 2011/02 - 14 -