[AK4201] AK4201 Stereo Cap-less HP-Amp GENERAL DESCRIPTION The AK4201 is an audio stereo cap-less headphone amplifier. The AK4201 eliminates the need for large DC-blocking capacitors with a built-in Charge-pump circuit. A 100dB PSRR (Power Supply Rejection Ratio) is achieved by a built-in regulator, and 2Vrms outputs are available with excellent linearity when the AK4201 is used as a lineout amplifier. The AK4201 is available in tiny 12-pin USON (2.2 X 2.9mm), saving board space, cost, and reducing component height. FEATURE Stereo Cap-less Amplifier (No DC-blocking capacitors required) High PSRR (100dB at 217Hz) Output Power: 65 mW x 2ch @ 16Ω, AVDD=PVDD=5.0V, THD+N=-60dB 30 mW x 2ch @ 16Ω, AVDD=PVDD=3.3V, THD+N=-60dB Output Noise Level: 11µVrms (Ri=20kΩ, Rf=30kΩ) Line-Out level: 2.0Vrms @ 5kΩ, AVDD=PVDD=5.0V 2.0Vrms @ 5kΩ, AVDD=PVDD=3.3V Regulator built-in THD+N: -60dB @ 16Ω, 50mW, AVDD=PVDD=5.0V -60dB @ 16Ω, 20mW, AVDD=PVDD=3.3V -100dB @ 5kΩ, 2Vrms, AVDD=PVDD=5.0V -100dB @ 5kΩ, 2Vrms, AVDD=PVDD=3.3V Low Power Shutdown Mode 0.1µA (typ) Mute function at shutdown mode: -88dB attenuation No external component is required Zero offset by ground-referenced output Pop noise free at power-ON/OFF Power Supply: 2.6V ~ 3.6V or 4.5V ~ 5.5V Ta: −40 ∼ 85°C Package: 12pin USON (2.2 x 2.9mm, 0.5mm pitch) MS1077-E-01 2011/02 -1- [AK4201] ■ Block Diagram Rf AVDD Ci Ri Regulator Amp LIN LOUT AK4201 VSS2 Regulator Ci Ri ROUT RIN Amp Charge Pump PVDD PDN VSS1 CP CN PVEE Rf Figure 1. AK4201 Block Diagram MS1077-E-01 2011/02 -2- [AK4201] ■ Ordering Guide AK4201EU AKD4201 −40 ∼ +85°C 12pin USON (2.2mm x 2.9mm, 0.5mm pitch) Evaluation board for AK4201 ■ Pin Layout LIN 1 LOUT 2 Top View 12 RIN 11 ROUT 10 PVEE AVDD 3 VSS1 4 9 VSS2 PVDD 5 8 PDN CN 6 7 CP MS1077-E-01 2011/02 -3- [AK4201] PIN/FUNCTION No. 1 2 3 4 5 6 7 8 Pin Name LIN LOUT AVDD VSS1 PVDD CN CP PDN I/O I O I O I 9 VSS2 10 PVEE O 11 ROUT O 12 RIN I Note. The PDN pin must not be floated. Function L-channel analog input L-channel analog output Headphone positive power supply pin Ground 1 pin Charge-pump positive power supply pin Negative charge-pump capacitor terminal pin Positive charge-pump capacitor terminal pin Power-down mode pin “H”: Power-up, “L”: Power-down Ground 2 pin Charge-pump circuit negative voltage output pin R-channel analog output R-channel analog input ■ Handling of Unused Pin The unused I/O pins must be processed appropriately as below. Classification Pin Name Analog LIN, RIN, LOUT, ROUT Setting Connect Output pin to Input pin when one channel is used and the other is not used. (Example) Connect the ROUT pin to the RIN pin if Rch is not used. MS1077-E-01 2011/02 -4- [AK4201] ABSOLUTE MAXIMUM RATINGS (VSS1=VSS2 =0V (Note 1)) Parameter Power Supplies: Analog (Note 2) Charge Pump Input Current, Any Pin Except Supplies Input Voltage (Note 3) Ambient Temperature (powered applied)(Note 4) Storage Temperature Symbol AVDD PVDD IIN VIN min −0.3 −0.3 −0.3 Ta −40 Tstg −65 max 6.0 6.0 ±10 (AVDD + 0.3) or 6.0 70(Note 5) 85(Note 6) 150 Units V V mA V °C °C Note 1. All voltages are respect to ground. The PDN pin should be held to “L” when powered-up, and it should be set to “H” after all power supplies are powered-up. The PDN pin should be held to “L”, when powered-down. Note 2. VSS1 and VSS2 must be connected to the same analog plane. Note 3. LIN, RIN and PDN pin The maximum value is smaller value between (AVDD+0.3)V and 6.0V. Note 4. PCB wiring density should be 150% or more. Device back PAD should be connected to ground. Note 5. Headphone Output Power should below 65mW/ch. Note 6. Headphone Output Power should below 50mW/ch. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMEND OPERATING CONDITIONS (VSS1=VSS2 =0V (Note 1)) Parameter Power Supplies (Note 7) Analog, Charge Pump AVDD, PVDD Difference AVDD − PVDD min 4.5 2.6 -0.3 Symbol Ri Rf Gain min 10 10 -16 typ - max 100 100 16 Units kΩ kΩ dB RL CL Csum 16 - - 300 20 Ω pF pF Parameter External Input Resistance External Feedback Resistance Gain Range Load Resistance (LOUT, ROUT pins) Capacitance (LOUT, ROUT pins) Capacitance (LIN, RIN pins) Symbol typ 5.0 3.3 0 max 5.5 3.6 0.3 Units V V Note 7. AVDD and PVDD must not be in the range from 3.6V to 4.5V. Note: AKM assumes no responsibility for the usage beyond the conditions in this datasheet. MS1077-E-01 2011/02 -5- [AK4201] ANALOG CHARACTERISTICS (AVDD=PVDD=5.0V) (AVDD=PVDD=5.0V; PDN=5.0V; Ta=25ºC; VSS1=VSS2=0V; Input Signal Frequency =1kHz; Measurement band width=10Hz ∼ 20kHz; Gain=+3.5dB (Ri=20kΩ, Rf=30kΩ); Headphone-Amp: RL =16Ω; Charge Pump Circuit External Capacitance: C1=C2= 1μF (Figure 3), unless otherwise specified) Parameter min typ max Units Output Power 65 mW RL =16Ω, 0.68Vrms Input THD+N dB −60 0.68Vrms Input; Po = 65mW @ RL =16Ω -50 dB −60 0.60Vrms Input; Po = 50mW @ RL =16Ω -90 dB −100 1.33Vrms Input; Vo = 2.0Vrms @ RL =5kΩ S/N (Signal-to-Noise Ratio) 94 100 dB RL =16Ω (A-weighted) (Note 8) 100 106 dB RL =5kΩ (A-weighted) (Note 9) PSRR (Power Supply Rejection Ratio) (Note 10) 217Hz 100 dB 1kHz 90 dB Interchannel Isolation 60 80 dB RL =16Ω 100 dB RL =5kΩ ±0 ±1 mV Output Offset Voltage 50 ms Start-up time (Note 11) Power Supplies 4.8 7.2 mA AVDD + PVDD (Normal Mode; No Output) 0.1 10 uA AVDD + PVDD (Power-Down Mode, PDN =0V) Note 8. In case of 0.68Vrms Input (Po=65mW). Note 9. In case of 1.33Vrms Input (Vo=2Vrms). Note 10. PSR is applied to AVDD and PVDD with 300mVpp sine wave. Note 11. The time from the PDN pin= “H” to when the AK4201 can output signals. MS1077-E-01 2011/02 -6- [AK4201] ANALOG CHARACTERISTICS (AVDD=PVDD=3.3V) (AVDD=PVDD=3.3V; PDN=3.3V; Ta=25ºC; VSS1=VSS2=0V; Input Signal Frequency =1kHz; Measurement band width=10Hz ∼ 20kHz; Gain=+3.5dB (Ri=20kΩ, Rf=30kΩ); Headphone-Amp: RL =16Ω; Charge Pump Circuit External Capacitance: C1=C2= 1μF (Figure 3), unless otherwise specified) Parameter min typ max Units Output Power 30 mW RL =16Ω, 0.46Vrms Input THD+N -60 dB 0.46Vrms Input; Po = 30mW @ RL =16Ω -60 -50 dB 0.27Vrms Input; Po = 10mW @ RL =16Ω -100 -90 dB 1.33Vrms Input; Vo = 2.0Vrms @ RL =5kΩ S/N (Signal-to-Noise Ratio) 90 96 dB RL =16Ω (A-weighted) (Note 12) 100 106 dB RL =5kΩ (A-weighted) (Note 13) PSRR (Power Supply Rejection Ratio) (Note 14) 217Hz 70 dB 1kHz 70 dB Interchannel Isolation 60 77 dB RL =16Ω 100 dB RL =5kΩ mV Output Offset Voltage ±0 ±1 50 ms Start-up time (Note 15) Power Supplies 3.8 5.7 mA AVDD + PVDD (Normal Mode; No Output) 0.1 10 AVDD + PVDD (Power-Down Mode, PDN =0V) μA Note 12. In case of 0.46Vrms Input (Po=30mW). Note 13. In case of 1.33Vrms Input (Vo=2Vrms). Note 14. PSR is applied to AVDD and PVDD with 100mVpp sine wave. Note 15. The time from the PDN pin= “H” to when the AK4201 can output signals. MS1077-E-01 2011/02 -7- [AK4201] DC & SWITCHING CHARACTERISTICS (Ta= -40 ∼ 85°C; AVDD=PVDD=2.6 ∼ 3.6V or 4.5 ∼ 5.5V, Note 16) Parameter Symbol min High-Level Input Voltage VIH 1.6 Low-Level Input Voltage VIL Input Leakage Current Iin Power-down (PDN pulse Width) tPD 150 Note 16. Apply to the PDN pin. typ - max 0.5 ±2 - Units V V μA ns ■ Timing Diagram tPD VIH PDN VIL Figure 2. Power-down Timing MS1077-E-01 2011/02 -8- [AK4201] OPERATION OVERVIEW ■ Charge Pump Circuit The charge pump operates by the output of a regulator which uses PVDD voltage. The negative power supply (PVEE) for headphone amplifiers is generated from internal charge pump circuit. The external capacitors are showed in Figure 3. Low ESR (Equivalent Series Resistance) capacitors with 1uF to 2.2uF (+/-35% or less difference including temperature drift and a deviation over samples) are recommended for C1 and C2. The minimum value of capacitors should be more than 0.65uF if temperature drifts and a deviation over samples are big. Headphone-amp negative voltage PVEE pin C1: 1uF CN pin VSS1 Charge Pump Circuit C2: 1uF CP pin Figure 3. Charge Pump Circuit External Capacitor ■ Headphone-Amp (LOUT/ROUT pins) Power supply voltage for headphone amplifiers is supplied by a regulator for positive power and a charge-pump for negative power. The headphone amplifier output is single-ended and centered on VSS1(0V). Therefore, a capacitor for AC-coupling can be removed. The minimum load resistance is 16Ω. The output impedance is 20Ω (typ) when powered-down. MS1077-E-01 2011/02 -9- [AK4201] ■ Power-Up/Down Sequence The PDN pin must keep “L” until all power supply pins (AVDD, PVDD) are supplied, and must be set to “H” after. Power Supply (1) The Device in front of AK4201 DAC etc The Device in front of AK4201 Click noise Power Up (No Signal Output) Don’t Care Ta (2) Normal Operation Don’t Care (4) A 0V PDN pin 0V PVEE pin LOUT/ROUT pins (5) (3) 0V PVEE pin Output =-3.3V(Typ.) 0V Normal Operation(0V Common) 0V Figure 4. Power-up/down Sequence example (1) The interval from power Up to PDN pin = “L” → “H” “L” time of 150ns or more is needed to reset the AK4201. The power should be ON when the PDN pin = “L”. The PDN pin should be set to “H” after power supply (AVDD, PVDD) are ON. (2) The interval from power-up of the signal source device in front of the AK4201 to the AK4201’s PDN pin transition from “L” to “H” The other device should be powered up with no signal (e.g. MUTE). When a step wave (an instant DC level change) is output from the other device at the power-up, a high pass filter response wave will occur at “A” timing of Figure 4, according to the time constant of the input coupling capacitor (Ci) and the input resistor(Ri) in front of the AK4201. In order to prevent this pop noise through the AK4201, a wait time “Ta” is required after the other devices are powered-up. The AK4201 can attenuate pop noises of the other device by a built-in mute circuit during shutdown mode (PDN pin= “L”). Ta calculation example: (in the case of Ci =0.22uF, Ri = 20kΩ) τ=0.22u * 20k = 4.4ms Ta =τ* 7.6 = 33ms (When noise level by former device= 2V, response wave level= 1mV. 7.6*τ is needed) If a waiting time is not sufficient, a pop noise might occur, but there is no problem for the normal operation. (3) The AK4201 is in normal operation 50ms (max) after the PDN pin goes to “H”. The other device in front of the AK4201 should be still muted during this interval (50ms). (4) The other device in front of the AK4201 should start outputting the signal after the AK4201 starts Normal Operation. If click noise is generated by former device when MUTE is canceled, it will be output from the AK4201. (5) The PDN pin = “L”. LOUT/ROUT pins short to VSS1 with 20Ω(typ.). After 50ms (max.), the PVEE pin will be 0V according to a capacitor which connected to PVEE and internal resistance (typ. 17.5kΩ). The AK4201 can be powered up again after 150ns or more from the PDN pin = “L”. MS1077-E-01 2011/02 - 10 - [AK4201] SYSTEM DESIGN Ci Analog Input Power Supply 4.5∼5.5V, 2.6∼3.6V 0.22µ Ri 20kΩ + 10µ 10µ + Power Supply 4.5∼5.5V, 2.6∼3.6V Ri Top View 1 LIN RIN 12 Rf 30kΩ 20kΩ Rf 30kΩ 2 LOUT ROUT 11 3 AVDD PVEE 10 4 VSS1 VSS2 9 5 PVDD PDN 8 0.1µ Ci 0.22µ Analog Input 1µ (+) 0.1µ 6 CN DSP or μP CP 7 1µ (+) Note: 1. The PDN pin should be held to “L” when powered-up. The PDN pin should be set to “H” after all power supplies are powered-up. When power-down the AK4201, the PDN pin should be held to “L”. Refer to “Power-Up/Down Sequence” to avoid pop noise when power-up/down the AK4201. 1) Power-Up The power should be ON when the PDN pin = “L”. The PDN pin should be set to “H” 150ns after all power supplies (AVDD, PVDD) are ON. 150ns “L” time or more is needed to reset the AK4201. 2) Power-Down The AK4201 should be powered-down when the PDN pin = “L”. 2. 1uF~2.2uF ceramic capacitors (±35% including temperature characteristics and piece-to-piece variations) should be connected to between the CP and CN pins, and the VSS1 and PVEE1 pins, respectively. 3. Both lines from the LIN pin and RIN pin to each Input resistance Ri and feedback resistance Rf should be as short as possible for better PSRR. 4. AC coupling capacitors should be connected to LIN and RIN pins, respectively. MS1077-E-01 2011/02 - 11 - [AK4201] PACKAGE 12pin USON (2.2mm x 2.9mm, 0.5mm pitch) 0.225 ± 0.05 2.9 ± 0.05 2.9± 0.05 ∅ 0.50 Exposed Pad 0.08 ± 0.05 0.175 ± 0.05 2.6 ± 0.05 1.35 ± 0.05 2.2 ± 0.05 2.2 ± 0.05 0.5 0.25 ± 0.05 S M Au: 0.1um< 0.6MAX Ag: 2.5um< Ni: 65 ± 15um 0.05 0.05 S Note) The exposed pad on the bottom surface of the package must be connected to the ground. MS1077-E-01 2011/02 - 12 - [AK4201] MARKING 4201 XXXX 1 XXXX: Date code (4 digit) REVISION HISTORY Date (YY/MM/DD) 09/05/12 11/02/03 Revision 00 01 Reason First Edition Specification Addition Page Contents 12 The package drawing was changed. MS1077-E-01 2011/02 - 13 - [AK4201] IMPORTANT NOTICE z These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to current status of the products. z Descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application examples of the semiconductor products. You are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. z Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKM. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS1077-E-01 2011/02 - 14 -