AK2365

[AK2365]
AK2365
dPMR Filterless IF LSI
1. Features
The AK2365 includes 2nd-Mixer, AGC+BPF, PLL FM detector, noise squelch, and RSSI circuit.
This device can eliminate E to J type ceramic filters, quadrature discriminator, and other external
components.
• Low operating voltage: VDD = 2.6 to 5.5 V
• Wide operating temperature: Ta = -40 to 85 °C
• High sensitivity: -102dBm at 12dB SINAD
• Built-in PGA and 2nd Mixer
• Local frequency: 45.9MHz, 50.4MHz, 57.6MHz (Triple of 15.3, 16.8 and 19.2MHz)
• Built-in programmable AGC+BPF circuits corresponding to E to J type ceramic filters
• Built-in PLL FM detector
• RSSI function
• Built-in noise squelch circuits
• Low consumption current: 6mA
• Compact plastic packaging: 32-pin QFNJ （4.0 x 4.0 x 0.75mm, 0.4mm pitch）
MS1453-E-02
2014/5
-1-
[AK2365]
2. Contents
1. Features............................................................................................................................... 1
2. Contents .............................................................................................................................. 2
3. Block Diagram ..................................................................................................................... 3
4. Circuit Configuration ............................................................................................................ 4
5. Pin/Function ......................................................................................................................... 5
6. Absolute Maximum Ratings ................................................................................................. 7
7. Recommended Operating Conditions .................................................................................. 7
8. Digital DC Characteristics .................................................................................................... 8
9. Digital AC Timing ................................................................................................................. 9
10. Power-up Sequence ........................................................................................................ 11
11. System Reset .................................................................................................................. 11
12. Power Consumption......................................................................................................... 12
13. Analog Characteristics ..................................................................................................... 13
14. Serial Interface Configuration .......................................................................................... 18
15. Calibration Procedure ...................................................................................................... 24
16. AGC Operation ................................................................................................................ 25
17. Recommended External Application Circuits ................................................................... 26
18. Packaging ........................................................................................................................ 30
19. Important Notice............................................................................................................... 31
MS1453-E-02
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[AK2365]
3. Block Diagram
NC
IF_INPUT
MIX
IFIP
AGC1
NC
BPF0
NC
BPF1
IFOUT
NC
AGC2
BPF2
BPF3
PDOUT
DISCOUT
IFBUF
LPF
Limiter
AUDIOOUT
DISCRI
NAMPI
Noise AMP
Divider
NAMPO
NRECTO
Noise
Rectifier
Control
Logic
VIREF
LDO
RSSI
DETO
Comparator
AVSS2
RSTN SCLK SDATA CSN
AVSS3
LOIN
LOCAP
PDN
VREFA VREFD
BIAS
AGNDIN AGNDOUT
RSSIOUT
DVDD DVSS
AVSS AVDD
LO_INPUT
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2014/5
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[AK2365]
4. Circuit Configuration
Block
MIX
AGC+BPF
IFBUF
Divider
Description
2nd-mixer to convert the input signal down to 450kHz.
The circuit composed of AGC and BPF, where the desired signal is amplified and
spurious components included in the signal from the 2nd-mixer are eliminated.
The circuit to output filtered signal by AGC+BPF.
DISCRI
The circuit to divide the signal from LOIN pin.
The circuit to amplify the signal filtered at the AGC+BPF stage and generate rectangular
wave.
The demodulator circuit with PLL FM detector, where the audio signal is recovered.
LPF
The Low-pass filter to eliminate the noise generated at the DISCRI stage.
Noise AMP
The amplifiers to compose the Band-pass filter for noise squelch.
Noise Rectifier
The rectification circuit to detect the noise level.
Comparator
The circuit to compare the noise level with reference voltage level.
The circuit to indicate the Received Signal Strength Indicator (RSSI) by generating a DC
voltage corresponding to the input level from Limiter.
The circuit to generate internal reference voltage.
Limiter
RSSI
VIREF
LDO
Control Logic
The circuit to supply 1.8V power for some circuits.
The control register controls the status of internal condition by serial data that consists of
1 instruction bit, 6 address bits and 8 data bits.
MS1453-E-02
2014/5
-4-
[AK2365]
5. Pin/Function
Signal
Package
Pin No
Name
Type
Conditions
at power
down
Function
IF signal input pin
NC pin
NC pin
NC pin
NC pin
LDO reference pin
Connect the capacitor to stabilize LDO reference voltage.
Analog VSS power supply pin
Analog VDD power supply pin
Output pin to connect bias resistor for reference voltage
Output pin for the rectification circuit
Output pin for noise squelch amplifier
Input pin for noise squelch amplifier
Demodulated audio signal output pin
Pin2 for Discriminator Low-pass filter
Pin1 for Discriminator Low-pass filter
Output pin to connect capacitor for Received Signal Strength
Indicator(RSSI)
Output pin for IFBUF
Analog VSS power supply pin
Power down pin for LDO
Hardware reset pin
Chip select input pin for serial data
Clock input pin for serial data
Input and output pin for serial data
Signal detect output pin
Digital VDD power supply pin.
Digital VSS power supply pin.
LDO reference pin
Connect the capacitor to stabilize LDO reference voltage.
Analog VSS power supply pin
Analog ground output pin.
Connect the capacitor to stabilize the analog ground level.
Analog ground input pin.
Connect the capacitor to stabilize the analog ground level.
Local signal input pin
Local signal input pin
1
2
3
4
5
IFIP
NC
NC
NC
NC
AI
AIO
AIO
AIO
AIO
Note 1)
Z
Z
Z
Z
6
VREFA
AO
Low
7
8
9
10
11
12
13
14
15
AVSS
AVDD
BIAS
NRECTO
NAMPO
NAMPI
AUDIOOUT
DISCOUT
PDOUT
PWR
PWR
AO
AI
AO
AI
AO
AO
AO
Z
Note 2)
Z
Z
Note 3)
Note 4)
Z
16
RSSIOUT
AO
Z
17
18
19
20
21
22
23
24
25
26
IFOUT
AVSS2
PDN
RSTN
CSN
SCLK
SDATA
DETO
DVDD
DVSS
AO
PWR
DI
DI
DI
DI
DB
DO
PWR
PWR
Note 5)
Z
Z
Z
Z
Z
Z
-
27
VREFD
AO
Low
28
AVSS3
PWR
-
29
AGNDOUT
AO
Low
30
AGNDIN
AI
Low
31
32
LOCAP
LOIN
AI
AI
Note 6)
Note 6)
Note A: Analog, D: Digital, PWR: Power, I: Input, O: Output, B: Bidirectional, Z: High-Z, L: Low
Note 1) Connecting internally to VSS pin by 50kΩ
Note 2) Connecting internally to VDD pin by 720kΩ
Note 3) Connecting internally to VSS pin by 830kΩ
MS1453-E-02
2014/5
-5-
[AK2365]
Note 4) Connecting internally to VSS pin by 50kΩ
Note 5) Connecting internally to VSS pin by 480kΩ
Note 5) Connecting internally to VDD pin by 139kΩ
IFOUT
21
AVSS2
22
20 19 18
17
PDN
CSN
23
RSTN
SCLK
24
SDATA
DETO
• Pin Assignment
VREFD
27
14
DISCOUT
AVSS3
28
13
AUDIOOUT
AGNDOUT
29
12
NAMPI
AGNDIN
30
11
NAMPO
LOCAP
31
10
NRECTO
LOIN
32
9
1
2
3
4
5
6
7
8
AVDD
PDOUT
AVSS
15
VREFA
26
NC
DVSS
NC
RSSIOUT
NC
16
NC
25
IFIP
DVDD
MS1453-E-02
BIAS
2014/5
-6-
[AK2365]
6. Absolute Maximum Ratings
Parameter
Symbol
Min.
Max.
Units
AVDD
-0.3
6.5
V
DVDD
-0.3
6.5
V
VSS
0
0
V
VIN analog
-0.3
AVDD+0.3
V
VIN digital
-0.3
DVDD+0.3
V
IIN
-10
+10
mA
Storage Temperature
Tstg
Note : All voltages are relative to the VSS pin.
-55
125
°C
Power Supply Voltage
Ground Level
Input Voltage
Input Current
(Except power supply pin)
Caution : Exceeding these maximum ratings can result in damage to the device.
Normal operation cannot be guaranteed under this extreme.
7. Recommended Operating Conditions
Parameter
Operating Temperature
Power Supply Voltage
Analog Reference Voltage
Output Load Resistance
Symbol
Condition
Min.
Typ.
Max.
Units
85
°C
Ta
-40
AVDD
2.6
3.0
5.5
V
2.6
3.0
5.5
V
DVDD
DVDD ≤ AVDD
AGND
AGNDOUT
RL1
CL1
Output Load Capacitance
CL2
1/2
VREFA
AUDIOOUT, DISCOUNT,
NAMPO
AUDIOOUT, DISCOUNT,
NAMPO
IFOUT
V
30
kΩ
21
15
pF
26
pF
Note : All voltages are relative to the VSS pin.
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[AK2365]
8. Digital DC Characteristics
Parameter
Symbol
High level input voltage
VIH
Low level input voltage
VIL
High level input current
IIH
Low level input current
IIL
High level output voltage
VOH
Low level output voltage
VOL
Condition
RSTN, SCLK, SDATA,
CSN, PDN
RSTN, SCLK, SDATA,
CSN, PDN
VIH=DVDD
RSTN, SCLK, SDATA,
CSN, PDN
VIL=0V
RSTN, SCLK, SDATA,
CSN, PDN
IOH=+0.2mA
SDATA
IOL=-0.4mA
SDATA, DETO
MS1453-E-02
Min.
Typ.
Max.
0.8DVDD
Units
V
0.2DVDD
V
10
uA
-10
uA
DVDD-0.4
DVDD
V
0.0
0.4
V
2014/5
-8-
[AK2365]
9. Digital AC Timing
1) Serial Interface Timing
AK2365 is connected to a CPU by three-wired interface through CSN, SCLK and SDATA pins, which
can make reading and writing data for control registers.
Serial data named SDATA is consist of 1-bit read and write instruction(R/W), 6-bit address (A5 to A0)
and 8-bit data(D7 to D0) in one frame.
Write mode
CSN
SCLK
SDATA
(Input)
SDATA
R/W
A5
A4
A3
A2
A1
A0
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
D5
D4
D3
D2
D1
D0
Hi-Z
(Output)
Read mode
CSN
SCLK
SDATA
(Input)
SDATA
R/W
Hi-Z
R/W
Hi-Z
D7
D6
: Instruction bit controls to write data to AK2365 or read back from it.
When set to low, AK2365 is in write mode. When set to high,
AK2365 is in read mode.
A5 to A0: Register address to be accessed.
D7 to D0: Write or read date to be accessed.
<1>
CSN(Chip select) is normally selected high for disable.
When CSN is set to low, serial interface becomes active.
<2>
In write mode, instruction, address and data input from SDATA pin are synchronized and
latched with the rising edge of 16 iterations of SCLK clock. Set to low between address A0 and
data D7.Input data is fixed synchronized with the rising edge of 16th clock. Note that if CSN
become “H” before 16th clock, setting data becomes invalid. During the period when CSN is
set to “L”, consecutive writing is available.
<3>
In read mode, instruction and address are synchronized and latched with the rising edge of 7
iterations of SCLK clock. And the register data are output from SDATA pin synchronized with
the falling edge of 9 iterations of SCLK clock. The data between address A0 and data D7 is
unstable. During the period when data is output, input to SDATA must be “Hi-z”. Set CSN to
“H” once reading is completed because consecutive reading is not valid.
MS1453-E-02
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[AK2365]
2) Detail Timing Chart
Write mode
tCSLH
tCSS
tCSHH
CSN
tWH
tWL
SCLK
tDS
SDATA
(Input)
R/W
SDATA
(Output)
High-Z
tDH
A5
A4
A3
A0
D7
D6
D1
D0
Read mode
tCSLH
tCSS
tCD
CSN
tSD
tDD
SCLK
High-Z
SDATA
(Input)
R/W
SDATA
(Output)
High-Z
A5
A4
A1
A0
D7
D6
D1
D0
Rising and falling time
tR
tF
SCLK
VIH
VIL
Parameter
CSN setup time
SDATA setup time
SDATA hold time
SCLK high time
SCLK low time
CSN low hold time
CSN high hold time
SDATA Hi-Z setup time
SCLK to SDATA output delay
time
CSN to SDATA input delay time
SCLK rising time
SCLK falling time
Symbol
Condition
Min.
Typ.
Max.
Unit
tCSS
100
ns
tDS
100
ns
tDH
100
ns
tWH
500
ns
tWL
500
ns
tCSLH
100
ns
tCSHH
100
ns
tSD
500
ns
tDD
20pF load
tCD
20pF load
400
ns
ns
200
tR
250
ns
tF
250
ns
Note) Digital input and output timing is relative to 0.5DVDD of rising signal and falling signal.
MS1453-E-02
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[AK2365]
10. Power-up Sequence
PDN (LDO)
1µs
700µs
1.8V
On-chip LDO
(1.8V operation)
The register can be written
RSTN
Internal register values are set.
Write to the register
Note) After PDN is set to “High”, registers remain undefined. In order to initialize them, RSTN is
set to “High”
11. System Reset
Parameter
Symbol
Hardware reset signal
input width
tRSTN
Min.
RSTN pin
Typ.
Max.
1
SRST
register
Software reset
*1)
Condition
Unit
Remarks
µs
*1)
*2)
After power-on, be sure to perform a hardware reset operation (register initialization). The
system is reset by a low pulse input of 1µs (min.) and enters the normal operation state. At this
moment, the digital (DI) pins are set as follows: RSTN pin to High, SCLK pin to Low, SDATA pin
to Low, CSN pin to Low.
tRSTN
VIH
RSTN
VIL
*2)
When data 0x04:10101010 is written to the SRST[7:0] register, software reset is performed.
This setting initializes the registers and the operation mode is set to mode 2 (Standby 2).
After software reset is completed, this register comes to “0”.
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[AK2365]
12. Power Consumption
Parameter
Symbol
IDD0
IDD1
IDD2
Power
Consumption
IDD3
IDD4
IDD5
IDD6
IDD7
Condition
Min.
Typ.
Mode 0
Max.
Units
0.01
Power down
Mode 1
Standby 1
Mode 2
Standby 2
Mode 3
0.3
0.6
0.4
0.7
1
1.6
5.6
7.5
6
8
6
8
7
9.8
mA
Mode 4
Digital Mode 1 with no signal input
Mode 5
Digital Mode 2 with no signal input
Mode 6
Analog Mode with no signal input
Mode 7
Full Power On with no signal input
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[AK2365]
13. Analog Characteristics
For the following conditions unless otherwise specified: Mode 6, LOIN=50.4MHz,IFIP=50.85MHz,
∆f=±1.5kHz, fmod=1kHz、AGC+BPF=F2, {AGC_OFF}=0, the exposure back pad of the package is
connected to VSS, with the external circuit shown in example page 26 to 28.
1) Local
Parameter
Local Frequency
Symbol
FLO
Condition
Min.
Max.
Units
45.9
50.4
57.6
LOIN
Input amplitude
VLO
LOIN
Note 1) Input from LOIN pin through DC cut
2) 2nd Mixer
Parameter
Typ.
MHz
0.2
Condition
2.0
Min.
Typ.
VPP
Max.
50
FLO
+0.45
28
Input Impedance
Input Frequency
Voltage Gain
Notes
Note 1)
Units
Notes
Ω
Note 2)
MHz
dB
Note 2) Include external matching circuit
3) Discriminator
Parameter
Condition
∆f=±3.0kHz,fmod=1kHz,
LIMITER IN to AUDIOOUT
{BAND}=1
Demodulation
Output Level
∆f=±1.5kHz,fmod=1kHz,
LIMITER IN to AUDIOOUT
{BAND}=0
∆f=±3.0kHz,fmod=1kHz,
Vin=-16dBm
S/N Ratio
LIMITER IN to AUDIOOUT
{BAND}=1
Note 3) With De-emphasis＋BPF(0.3 to 3kHz)
MS1453-E-02
Min.
Typ.
Max.
Units
70
100
130
mVrms
70
100
130
mVrms
43
50
dB
Notes
Note 3)
2014/5
- 13 -
[AK2365]
4) RX Overall Characteristics
Parameter
Condition
12dB SINAD
Input Sensitivity
Mode 5
Maximum gain setting for AGC
IFIP to IFOUT
{IFOG[1:0]}=00
Total Gain
Mode 5
Minimum gain setting for AGC
IFIP to IFOUT
{IFOG[1:0]}=00
Mode 5, BPF=F3
IFIP to IFOUT
When in CW, 450kHz, -102dBm
C/N ratio
Bandwidth: 450kHz ±3kHz
{IFOG[1:0]}=00
Mode 5
Maximum gain setting for AGC
IIP3
IFIP=50.8635MHz&50.876MHz
∆f=±3.0kHz,fmod=1kHz,
Demodulation
AGC+BPF=F1, {BAND}=1
Output
∆f=±1.5kHz,fmod=1kHz,
Level
AGC+BPF=F2, {BAND}=0
∆f=±3.0kHz, fmod=1kHz,
AGC+BPF=F1, Vin=-47dBm
{BAND}=1
S/N Ratio
∆f=±1.5kHz, fmod=1kHz,
AGC+BPF=F2, Vin=-47dBm
{BAND}=0
Note 4) With De-emphasis+BPF(0.3 to 3kHz)
MS1453-E-02
Min.
Typ.
Max.
Units
Notes
-102
dBm
Note 4)
84
dB
32
dB
17
-20
dBm
70
100
130
mVrms
70
100
130
mVrms
40
50
dB
Note 4)
34
44
dB
Note 4)
2014/5
- 14 -
[AK2365]
5) RSSI Characteristics
Parameter
Condition
RSSI Output Voltage
IFIP to RSSIOUT
{AGC_OFF}=0,
IFIP=-100dBm Input
IFIP to RSSIOUT
{AGC_OFF}=0,
IFIP=-30dBm Input
Min.
Typ.
Max.
Units
0.05
0.3
0.7
V
1.4
2.0
2.6
V
Min.
Typ.
Max.
Units
0.5
0.7
V
Notes
RSSI Characteristics
(VDD=3V)
3.0
RSSI output lvel (V)
2.5
2.0
1.5
1.0
0.5
0.0
-120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10
0
Mixer input level (dBm)
6) Noise Squelch Characteristics
Parameter
Condition
Noise Detection
Level
Noise Detection
Characteristic
NRECTO to DETO
Detect High
NRECTO to DETO
Detect Low
NAMPI to NRECTO
Input: 31kHz, 0.1mVrms
NAMPI to NRECTO
Input: 31kHz, 0.25mVrms
0.3
0.4
0.2
0.3
0.4
V
0.5
0.65
0.8
V
Notes
V
Noise Detect Characteristics
NRECTO output level [V]
(VDD=3V, fin=31kHz)
1.6
1.2
0.8
0.4
0.0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
Filter amplifier input level [mVrms]
MS1453-E-02
2014/5
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[AK2365]
7) AGC+BPF Characteristics
7.1) F0 (E type)
Parameter
Attenuation
Characteristics
Condition
7.2) F1 (F type)
Parameter
Attenuation
Characteristics
7.3) F2 (G type)
Parameter
Attenuation
Characteristics
Gain ripple
7.4) F3 (H type)
Parameter
Attenuation
Characteristics
Gain ripple
7.5) F4 (J type)
Parameter
Attenuation
Characteristics
(relative to the gain
at 450kHz)
Gain ripple
-50
dB
dB
457.5kHz
-6
dB
Condition
Min.
Typ.
437.5kHz
-50
dB
3
dB
Max.
Units
-50
dB
444kHz
-6
dB
456kHz
-6
dB
462.5kHz
Within 450±4kHz
Condition
Min.
Typ.
439kHz
-50
dB
3
dB
Max.
Units
-50
dB
445.5kHz
-6
dB
454.5kHz
-6
dB
461kHz
Within 450±3kHz
Condition
Min.
Typ.
441kHz
(relative to the gain
at 450kHz)
Units
-6
Within 450±5kHz
(relative to the gain
at 450kHz)
Max.
442.5kHz
465kHz
(relative to the gain
at 450kHz)
Gain ripple
Typ.
435kHz
(relative to the gain
at 450kHz)
Gain ripple
Min.
-50
dB
3
dB
Max.
Units
-50
dB
447kHz
-6
dB
453kHz
-6
dB
459kHz
Within 450±2kHz
Condition
Min.
442.5kHz
Typ.
-50
dB
2
dB
Max.
Units
-50
dB
448kHz
-6
dB
452kHz
-6
dB
457.5kHz
Within 450±1.5kHz
MS1453-E-02
-50
dB
2
dB
Notes
Notes
Notes
Notes
Notes
2014/5
- 16 -
[AK2365]
BPF F1 (BW=±6kHz)
BPF F0 (BW=±7.5kHz)
10
10
500
Gain[dB]
0
500
Gain[dB]
0
G.D.T.[μs]
-10
G.D.T.[μs]
-10
400
400
-50
200
-30
300
Gain [dB]
-40
G,D.T.[μs]
300
Gain [dB]
-30
-40
-50
200
G,D.T.[μs]
-20
-20
-60
-60
-70
-70
100
100
-80
-80
-90
-90
0
425
430
435
440
445
450
455
460
465
470
0
425
475
430
435
440
445
450
455
460
465
470
475
Frequency [kHz]
Frequency [kHz]
BPF F3 (BW=±3kHz)
BPF F2 (BW=±4.5kHz)
10
0
500
10
500
Gain[dB]
Gain[dB]
0
G.D.T.[μs]
-10
G.D.T.[μs]
400
-10
400
-50
200
300
-30
Gain [dB]
-40
G,D.T.[μs]
300
Gain [dB]
-30
-40
200
-50
G,D.T.[μs]
-20
-20
-60
-60
-70
100
-70
100
-80
-80
-90
-90
0
425
430
435
440
445
450
455
460
465
470
0
425
475
430
435
440
445
450
455
460
465
470
475
Frequency [kHz]
Frequency [kHz]
BPF F4 (BW=±2kHz)
500
10
Gain[dB]
0
G.D.T.[μs]
400
-10
300
Gain [dB]
-30
-40
200
-50
G,D.T.[μs]
-20
-60
-70
100
-80
-90
0
425
430
435
440
445
450
455
460
465
470
475
Frequency [kHz]
8) IFBUF Characteristics
Parameter
Settling time
Condition
Min.
IFBUF to IFOUT,
IFBUF=0.32Vpp/step
CL2=21pF, {IFOG[1:0]}=00
Typ.
Max.
100
Units
Notes
ns
Note: Convergence time within 1% when 0.32Vpp step signal input to IFBUF pin
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[AK2365]
14. Serial Interface Configuration
1) Register Configuration
Name
Control
register 1
ADRS D7(MSB)
D6
D5
BS[2:0]
D4
BAND
D3
D2
D1
BPF_BW[1:0]
D0(LSB) W/R
LOFREQ[1:0]
0x01
W/R
0
1
0
0
Reserved
Control
register 2
0x02
Control
register 3
0x03
Software
-reset
0x04
Reserved
0x05
to
0x0A
Control
register 4
BPF_BW
[2]
0x0B
0
Control
register 5
0x0C
0
0
0
0
AGC_TIME[1:0]
1
1
0
0
1
AGC1_
STEP
CAL
1
0
0
Reserved
W/R
IFOG[1:0]
W/R
0
0
0
0
0
0
0
0



SRST[7:0]






Reserved
AGC_
OFF
0
W
AGC1_G[5:0]
W/R
0
0
0
Reserved
0
0
1
0
0
AGC2_G[4:0]
W/R
1
0
0
0
0
0
Note: Do not access the data except specified address above.
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[AK2365]
2) Description of registers
Address 0x01 (Control Register 1)
Name
D7(MSB)
Control Register 1
D6
D5
BS[2:0]
Initial Value
0
D4
D3
BAND
1
0
D2
BPF_BW[1:0]
D1
D0(LSB)
LOFREQ[1:0]
0
0
0
0
1
LDOD
LDOA,
AGNDIN
VREF
MIX
AGC,
BPF,
Divider
IFBUF
Limiter,
RSSI
DISCRI,
Noise
Squelch
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON
OFF
OFF
OFF
OFF
OFF
OFF
ON
ON
OFF
OFF
OFF
OFF
OFF
BS[2:0]: Operation mode setting
PDN
pin
BS[2]
BS[1]
BS[0]
0
-
-
-
1
0
0
1
1
0
1
0
1
0
1
1
Mode 3
ON
ON
ON
OFF
OFF
OFF
OFF
1
1
0
0
Mode 4
ON
ON
ON
ON
ON
OFF
OFF
1
1
0
1
Mode 5
ON
ON
ON
ON
ON
ON
OFF
1
1
1
0
Mode 6
ON
ON
ON
ON
OFF
ON
ON
1
1
1
1
Mode 7
ON
ON
ON
ON
ON
ON
ON
Mode
name
Mode 0
(Powerdown)
Mode 1
(Standby
1)
Mode 2
(Standby
2)
Note: Do no set the combination of the code which is not defined in the table given above.
BAND：Demodulated signal level setting
BAND
Function
0
Narrow
1
Wide
Note1: When {BAND} register is set to “0”, demodulated signal level at AUDIOOUT pin, when input
signal is ∆f=±1.5kHz dev, is 100mVrms typ. When {BAND} register is set to “1”, demodulated signal
level at AUDIOOUT pin, when input signal is ∆f=±3.0kHz dev, is 100mVrms typ.
BPF_BW[1:0]: BPF band width setting
BPF_BW
[2]
BPF_BW
[1]
BPF_BW
[0]
name
6dB
attenuation
Attenuation
band width
1
0/1
0/1
F0
±7.5kHz
±15kHz
0
0
0
F1
±6kHz
±12.5kHz
0
0
1
F2
±4.5kHz
±11kHz
0
1
0
F3
±3kHz
±9kHz
0
1
1
F4
±2kHz
±7.5kHz
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[AK2365]
LOFREQ[1:0]: Local frequency setting
LOFREQ
[1]
LOFREQ
[0]
Local frequency
0
0
45.9MHz
0
1
50.4MHz
1
0
57.6MHz
Note: Do no set the combination of the code which is not defined in the table given above.
Address 0x02 (Control Register 2)
Name
D7(MSB)
Control Register 2
D6
D5
D4
Reserved
Initial Value
0
0
D3
D2
AGC_TIME[1:0]
1
1
0
0
D1
D0(LSB)
AGC1_S
TEP
CAL
1
0
AGC_TIME[1:0]: AGC response time setting
This register set response time for AGC1 gain and AGC2 gain to change by 1step.
AGC response time [ms]
AGC_TIME
[1]
AGC_TIME
[0]
AGC1_STEP=0 setting
AGC1_STEP=1 setting
State A
State B
State C
State A
State B
State C
0
0
0.56
8.50
8.50
0.38
4.35
4.35
0
1
0.92
8.79
8.79
0.56
4.50
4.50
1
0
1.64
9.37
9.37
0.93
4.79
4.79
1
1
3.08
10.52
10.52
1.66
5.38
5.38
Note 1: Values above indicate response time during AGC gain changes from maximum to minimum or
from minimum to maximum.
State A: AGC1 output level is beyond the upper limit.
State B: AGC1 output level is within the upper limit and AGC2 output level is beyond the upper limit.
State C: AGC2 output level is under the lower limit.
Operation
Data
AGC1_ST
EP
CAL
Function
AGC1 gain switching
range setting
Discriminator circuit
calibration start
trigger (Note2)
Notes
0
1
±1dB
±2dB
Invalid
Start
Note 2: calibration is performed synchronized with the rising edge of {CAL}. After calibration is
completed, this register is set to “0” automatically. It takes 1.3ms before calibration is completed.
Refer to “calibration procedure” for further information.
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[AK2365]
Address 0x03 (Control Register 3)
Name
D7(MSB)
D6
D5
Control Register 3
D4
D3
D2
Reserved
Initial Value
0
0
D1
D0(LSB)
IFOG[1:0]
0
0
0
0
0
0
D5
D4
D3
D2
D1
D0(LSB)



IFOG[1:0]: IFBUF Gain setting
IFOG
[1]
IFOG
[0]
IFBUF Gain[dB]
0
0
6
0
1
9
1
0
12
1
1
15
Address 0x04 (Software Reset)
Name
D7(MSB)
D6
SRST[7:0]
Software-reset

Initial Value




When data 0x04:10101010 is written to the SRST[7:0] register, software reset is performed.
Refer to System Reset for further information.
Address 0x0B (Control Register 4)
Name
D7(MSB)
D6
D5
Control Register 4
BPF_BW
[2]
AGC_
OFF
Initial Value
0
0
D4
D3
D2
D1
D0(LSB)
0
1
AGC1_G[5:0]
0
0
0
0
Operation
Data
Function
Notes
0
1
BPF_BW[2]
F0
(±7.5kHz)
OFF
ON
AGC_
OFF
AGC function
Disable
(AGC Auto
operation)
Enable
(AGC manual
operation)
AGC1_G[5:0]
AGC1 gain adjustment
21 to -19dB by 1dB step
MS1453-E-02
Available only
{AGC_OFF}=1
2014/5
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[AK2365]
AGC1_G[5]
AGC1_G[4]
AGC1_G[3]
AGC1_G[2]
AGC1_G[1]
AGC1_G[0]
Gain [dB]
0
1
0
1
0
1
0
1
0
1
0
0
0
1
0
0
1
1
0
1
0
0
1
0
0
1
0
0
0
1
0
1
0
0
0
0
0
0
1
1
1
1
0
0
1
1
1
0
0
0
1
1
0
1
0
0
1
1
0
0
0
0
1
0
1
1
0
0
1
0
1
0
0
0
1
0
0
1
0
0
1
0
0
0
0
0
0
1
1
1
0
0
0
1
1
0
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
1
1
1
1
0
1
0
1
1
1
0
0
1
1
1
1
0
0
0
1
1
0
1
1
1
1
1
0
1
1
0
1
1
0
1
0
1
1
1
0
1
0
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
0
0
1
1
1
0
0
0
0
1
0
1
1
1
1
1
0
1
1
1
0
1
0
1
1
0
1
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
-11
-12
-13
-14
-15
-16
-17
-18
-19
Note: Do not set the combination of the code which is not defined in the table given above.
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[AK2365]
Address 0x0C (Control Register 5)
Name
D7(MSB)
Control Register 5
D6
D5
D4
D3
Reserved
Initial Value
1
D2
D1
D0(LSB)
0
0
AGC2_G[4:0]
0
0
0
0
0
Operation
Data
Function
Notes
0
AGC2_G[4:0]
AGC2 gain adjustment
1
Available only
{AGC_OFF}=1
12 to 0dB by 1dB step
AGC2_G[4]
AGC2_G[3]
AGC2_G[2]
AGC2_G[1]
AGC2_G[0]
0
1
1
0
0
0
1
0
1
1
0
1
0
1
0
0
1
0
0
1
0
1
0
0
0
0
0
1
1
1
0
0
1
1
0
0
0
1
0
1
0
0
1
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
Gain [dB]
12
11
10
9
8
7
6
5
4
3
2
1
0
Note: Do not set the combination of the code which is not defined in the table given above.
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[AK2365]
15. Calibration Procedure
AK2365 employs a function to calibrate free-running frequency of VCO in Discriminator and
demodulated signal level. Before starting RX Operation, calibration is required in order to acquire
proper VCO operation range and demodulated signal level.
Following procedure is required before calibration.
<1> Start up the external TCXO and continuously supply LO signal to AK2365.
<2> Set “110” to 0x01 {BS[2:0]} and start up all circuits. After this operation, the circuits necessary
for calibration (LOBUF, VIREF, Discriminator) will be powered on and calibration can be
possible in 500us.
<3> Calibration is begun by setting "1" to address 0x02 {CAL}. When the calibration is executed
once, the calibration operation cannot be stopped excluding master reset. Even if "0" is written
in {CAL}, the calibration is completely executed.
<4> Calibration data is maintained excluding the time when the master reset is executed or DVDD
power supply is down.
<5> It takes 1.5ms for Discriminator to become steady after the calibration is completed.
Power-up sequence recommendation
LOIN（external）
{BS[1:0]}
Unstable
“11”
“01”
(500μs)
LOBUF
VIREF
Discriminator
Unstable
Stable
(1.3ms)
Reset itself automatically after calibration is completed
{CAL}
(1.5ms)
Internal
Discriminator
Unstable
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[AK2365]
16. AGC Operation
AK2365 has two AGC circuits, AGC1 and AGC2. The signal level from IFIP pin is adjustable
automatically by AGC1/2. The following graphs show IFIP input vs. IFOUT output characteristics by
setting {AGC1_STEP}=0/1, {IFOG[1:0]}=00, {AGC_OFF}=0. Setting {AGC_OFF}=1 can disable
automatic gain adjustable operation and also enable manual gain operation by {AGC1_G[5:0]},
{AGC2_G[4:0]} registers.
IFIP level vs. IFOUT level
(VDD=3V, AGC1_STEP=0)
20
IFOUT output level [dBm]
10
0
-10
-20
-30
-40
-50
-110 -100
-90
-80
-70
-60
-50
-40
-30
-20
-10
-30
-20
-10
IFIP input level [dBm]
IFIP level vs. IFOUT level
(VDD=3V, AGC1_STEP=1)
20
IFOUT output level [dBm]
10
0
-10
-20
-30
-40
-50
-110 -100
-90
-80
-70
-60
-50
-40
IFIP input level [dBm]
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[AK2365]
17. Recommended External Application Circuits
1) Power supply stabilizing capacitors
Connect capacitors between VDD and VSS pins to eliminate ripple and noise included in power
supply. For maximum effect, the capacitors should be placed at a shortest distance between the
pins.
25
DVDD
C1=0.1µF (Ceramic cap)
C1
C2
C2=10µF (Electrolytic cap)
26
DVSS
8
AVDD
C2
C1
7
AVSS
LSI
2) AGND stabilizing capacitors
It is recommended that capacitors with 1μF or lager be connected between VSS and the AGND
and AGNDIN pins to stabilize the AGND signal. The capacitors must be placed as close to the
pins as possible.
30
AGNDIN
29
AGNDOUT
C
AVSS
C=1µF (Electrolytic capacitor)
C
AVSS
LSI
3) BIAS pin
9
BIAS
R1
R1=47kΩ±1%
AVSS
LSI
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[AK2365]
4) VREFA output
It is recommended that capacitors with 220nF or lager be connected between AVSS and VREFA
pin to stabilize the VREFA signal. The capacitors must be placed as close to the pins as possible.
6
VREFA
C1
C1=220nF
AVSS
LSI
5) VREFD output
It is recommended that capacitors with 220nF or lager be connected between DVSS and VREFD
pin to stabilize the VREFD signal. The capacitors must be placed as close to the pins as possible.
27
VREFD
C1
C1=220nF
DVSS
LSI
6) MIX
IFIP
1
C1
IF_INPUT
C2
C1=22pF, L1=470nH for 46.35MHz
L1
R1
C1=18pF, L1=470nH for 50.85MHz
C1=13pF, L1=470nH for 58.05MHz
C2=10nF
R1=750Ω
LSI
7) LOIN
LOIN
32
LO_INPUT
C1
C2
31
C1=C2=100pF
LOCAP
AVSS
LSI
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[AK2365]
8) Discriminator
15
R1
PDOUT
C1=1000pF
C1
R1=220kΩ
14
DISCOUT
R2=1MΩ
R2
LSI
9) Noise AMP
The following gives a sample configuration of a BPF when input frequency is 31kHz.
Some parameters can be calculated using following (1) to (3) equations.
11
NAMPO
C1=0.47uF
C2
C2=C3=220pF
R3
R1 C1
C3
_
+
12
NAMPI
R2
Noise Amp
R1=10kΩ
R2=5.6kΩ
AVSS
R3=150kΩ
LSI
(1) f 0 =
1
2π R3 ( R1 // R2 )C2
(2) Gv =
R3
2 R1
(3) Q 2 =
R3
4( R1 // R2 )
MS1453-E-02
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[AK2365]
10) NECTO pin
Rise time of noise detection is proportionate to C1=0.1μF and internal resistance 75kΩ
10
NRECTO
C1
C1=0.1µF
AVSS
LSI
11) RSSIOUT pin
16
RSSIOUT
R1=51kΩ
C1
R1
C1=1000pF
AVSS
LSI
12) DETO
DVDD
24
DETO
R1
R1=100kΩ
LSI
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[AK2365]
18. Packaging
□ Marking
2365
YWWL
●
［Contents of YWWL］
Y： Last digit of calendar year. (Year 2011->1, 2012->2)
WW: Manufacturing week number.
L: Lot identification, given to each product lot which is made in a week.
LOT ID is given in alphabetical order (A, B, C…).
□ Mechanical Outline
Package：32pin QFN (4.0 x 4.0 x 0.7mm, 0.4mm pitch)
B
2.80±0.10
17
24
25
32
9
8
1
A
0.35±0.10
2.80±0.10
4.00±0.10
16
C0.35
4.00±0.10
0.20±0.05
0.10 M C A B
0.75±0.05
0.08 C
C
0.40 BSC
0.05 MAX
Note）The exposure pad(Exposed Pad）of the center of the package back is connected to opening
or VSS.
MS1453-E-02
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[AK2365]
19. Important Notice
IMPORTANT NOTICE
 These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales
office of Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to current
status of the products.
 Descriptions of external circuits, application circuits, software and other related information
contained in this document are provided only to illustrate the operation and application examples
of the semiconductor products. You are fully responsible for the incorporation of these external
circuits, application circuits, software and other related information in the design of your
equipments. AKM assumes no responsibility for any losses incurred by you or third parties arising
from the use of these information herein. AKM assumes no liability for infringement of any patent,
intellectual property, or other rights in the application or use of such information contained herein.
 Any export of these products, or devices or systems containing them, may require an export
license or other official approval under the law and regulations of the country of export pertaining
to customs and tariffs, currency exchange, or strategic materials.
 AKM products are neither intended nor authorized for use as critical componentsNote1) in any
safety, life support, or other hazard related device or systemNote2), and AKM assumes no
responsibility for such use, except for the use approved with the express written consent by
Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be
expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of
the device or system containing it, and which must therefore meet very high standards of
performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or
maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other
fields, in which its failure to function or perform may reasonably be expected to result in loss
of life or in significant injury or damage to person or property.
 It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or
otherwise places the product with a third party, to notify such third party in advance of the above
content and conditions, and the buyer or distributor agrees to assume any and all responsibility
and liability for and hold AKM harmless from any and all claims arising from the use of said
product in the absence of such notification.
MS1453-E-02
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