AK2347B

ASAHI KASEI
[AK2347B]
AK2347B
Two-way Radio Audio & Sub-Audio Processor
1. Features
• Audio processing
• TX and RX amplifier
• Pre/De-emphasis circuit
• Compressor and Expander with no external components
• Scrambler and De-scrambler in frequency inversion type (3.388kHz or 3.290kHz)
• Limiter with level adjuster
• Splatter filter for wide and narrow band
• Digital controlled amplifier for microphone, modulator and demodulator sensitivity
• Sub-Audio filter with level adjuster for CTCSS and DCS
• Low power supply operation: 2.7 to 3,3V
• Wide range operating for temperature: -40 to 85 °C
• Oscillator circuit for 3.6864MHz and 3.579545MHz crystal
• Serial control interface operation
• Compact plastic packaging, 24-pin SSOP
2. Description
AK2347B includes audio filter, limiter, splatter filter, compandor, scrambler, which is highly integrated
two-way radio baseband functions for FRS and LMR.
Audio high-pass filter shows a high attenuation in magnitude response characteristics under 250Hz
that supports to eliminate a subaudio tone clearly.
TX limiter for deviation control has a limiting level adjuster by applying a DC voltage via external
components. Splatter filter has the magnitude response for narrowband(fc=2.55kHz) and
wideband(3.0kHz) to meet various regulatory agencies in the world wide.
Compandor is no adjustment type because it includes all parametric components inside the chip.
Scrambler circuit is composed of frequency inversion circuit by double balanced mixer that has
3.388kHz and 3.290kHz carrier clock.
Sub-Audio filter with level adjuster is available for pre- or post-filter for CTCSS and DCS.
There are four signal level adjusters for microphone, modulator and demodulator sensitivity by digital
controlled amplifier (volume).
• Pin Assignment (Top view)
AGNDIN
1
24
RXIN
AGND
2
23
RXINO
TXINO
3
22
FILTERO
TXIN
4
21
RXOUT
EXTIN
5
20
DINO
EXTINO
6
19
DIN
LIMLV
7
18
RSAOUT
MOD
8
17
TSAOUT
VSS
9
16
VDD
SDATA
10
15
XOUT
SCLK
11
14
XIN
CSN
12
13
TEST
MS1419-E-00
2012/05
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ASAHI KASEI
[AK2347B]
3. Contents
1. Features .................................................................................................. 1
2. Description .............................................................................................. 1
3. Contents .................................................................................................. 2
4. Block Diagram ......................................................................................... 3
5. Block Functions ....................................................................................... 4
6. Pin Functions .......................................................................................... 5
7. Absolute Maximum Ratings ..................................................................... 7
8. Recommended Operating Conditions ...................................................... 7
9. Digital DC Characteristics........................................................................ 7
10. Clock Input Characteristics .................................................................... 8
11. Current Consumption............................................................................. 8
12. Analog Characteristics ........................................................................... 9
13. Level Diagram ..................................................................................... 15
14. Digital AC Timing ................................................................................. 16
15. Register Function Description ............................................................. 18
16. Recommended External Application Circuits ....................................... 28
17. Packaging ........................................................................................... 33
18. Important Notice .................................................................................. 34
MS1419-E-00
2012/05
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ASAHI KASEI
[AK2347B]
4. Block Diagram
MS1419-E-00
2012/05
-3-
ASAHI KASEI
[AK2347B]
5. Block Functions
Block
TXA1
VR1
(HPF)
Compressor
Pre-emphasis
TX/RX_HPF
Scrambler/
Descrambler
Function
Operational amplifier for gain adjustment of transmit audio signal and for the filter for
preventing aliasing noise of the SCF circuit in the subsequent stage. Use external
resistors and capacitors to set the gain to 30dB or less and the cut-off frequency to
around 10kHz.
This circuit controls the volume for adjusting the input level of transmit audio signal.
Setting registers: VR12 to VR10, adjustment range: -6.0dB to +4.5dB in 1.5dB steps
This circuit compresses the amplitude of transmit audio signal by 1/2 in dB scale.
Cross-point: -10dBx. This circuit is turned on and off by the TC register.
This circuit emphasizes the high-frequency component of transmit audio signal to
improve the S/N ratio of the modulation signal.
High-pass filter to eliminate low-frequency components lower than 250Hz which are
included in transmit and receive audio signals. This circuit is turned on and off by the
HPF register.
This circuit inverts the spectrum distribution of transmit and receive audio signals with
respect to the carrier frequency.
The carrier frequency is 3.388kHz or 3.290kHz.
The Scrambler/Descrambler or emphasis circuit can be selected using the EM and
PCONT registers. These circuits cannot be used at the same time.
TXA2
Operational amplifier for gain adjustment of external tone signal. Use external resistors
and capacitors to set the gain to 0dB or less and the cut-off frequency to around 10kHz.
Adder
This circuit adds together the audio signal and external tone input signal. This circuit is
controlled by the TXSW2 and TXSW1 register.
Limiter
VR2
Splatter
SMF
RXA1
VR3
RXLPF
De-emphasis
Expander
VR4
Amplitude limiting circuit to suppress frequency deviation in the modulation signal.
The limit level can be adjusted by applying a DC voltage to the LIMLV pin. When the
pin is left open, the level predetermined within the device is output. This circuit is turned
on and off by the LMT register.
This circuit controls the volume for adjusting the output level on the MOD pin. Setting
registers: VR25 to VR20, adjustment range: -3.2dB to +3.0dB in 0.2dB steps. For
coarse adjustment, switching between -6.4dB and 0dB is possible.
Low-pass filter to eliminate high-frequency components higher than 3kHz which are
included in the limiter output signal. The cut-off frequency can be adjusted with the SPL
register.
Smoothing filter to eliminate the high-frequency and clock components generated in the
SCF circuit.
Operational amplifier for gain adjustment of the receive demodulation signal and for the
filter for preventing aliasing noise in the SCF circuit in the subsequent stage. Use
external resistors and capacitors to set the gain to 20dB or less and the cut-off frequency
to around 40kHz.
This circuit controls the volume for adjusting the input level of the receive demodulation
signal.
Setting registers: VR33 to VR30, adjustment range: -4.0dB to +3.5dB in 0.5dB steps
Low-pass filter to eliminate high-frequency components higher than 3kHz which are
included in the receive demodulation signal.
This circuit restores the original state of the signal of which high-frequency component
has been emphasized by the Pre-emphasis.
This circuit expands the signal compressed twice by the Compressor in dB scale to
restore the original signal state.
Cross-point: -10dBx. The Expander is turned on and off with the TC register.
This circuit controls the volume for adjusting the RX output level.
Setting registers: VR45 to VR40 Adjustment range: -18.0dB, -4.5dB to +4.5dB in
0.25dB steps
MS1419-E-00
2012/05
-4-
ASAHI KASEI
Block
DTA1
Sub-Audio
Programmable LPF
VR5
AGND
[AK2347B]
Function
Operational amplifier for gain adjustment of the Sub-Audio LPF input signal and for the
filter for preventing aliasing noise in the SCF circuit in the subsequent stage. Use
external resistors and capacitors to set the gain to 0dB or less and the cut-off frequency
to around 10kHz.
Low-pass filter to eliminate components of the DAT1 signal in the transmit operation and
of RXA1 signal in the receive. This circuit is controlled by the SASW register for transmit
or receive and by the SA5 to SA0 for cut-off frequency.
This circuit controls the volume for adjusting the output level from the Sub-Audio LPF
signal.
Setting registers: VR54 to VR50, adjustment range: -6.0dB to +6.0dB in 0.5dB steps
This circuit generates the reference voltage (1/2VDD) for internal analog signals.
This circuit generates a 3.6864MHz or 3.579545MHz reference clock signal from an
external resistor and crystal oscillator. This circuit is controlled by the MCKSL register.
Control registers set the switch status and volume for level adjustment inside the IC
according to the serial input data consisting of 1-bit instruction and 4-bit address and
8-bit data. At power-up, the registers are set to the power-down values by the power-on
reset circuit. This circuit has a software reset named RSTN register.
(See the description of the registers)
OSC
Control
Register
6. Pin Functions
Pin
number
Pin name
Pin
type
Powerdown
status
Function
Analog ground input pin
This pin is connected to a capacitor to stabilize the analog ground
level.
Analog ground output pin
This pin is connected to a capacitor to stabilize the analog ground
level.
1
AGNDIN
AI
*3)
2
AGND
AO
*3)
3
TXINO
AO
Z
4
TXIN
AI
Z
5
EXTIN
AI
Z
6
EXTINO
AO
*3)
Output pin of TXA2 *1)
Limit level adjustment pin
The limit level can be adjusted by applying a DC voltage to this pin.
When this pin is left open, the limit level predetermined within the
device is set.
Output pin of TXA1 *1)
Transmit audio signal input pin
This pin is the inverting input pin of TXA1. This pin, with resistors
and capacitors externally connected, forms a microphone amplifier.
External input pin
This pin is the inverting input pin of TXA2. This pin, with resistors
and capacitors externally connected, forms a amplifier.
An external signal such as a tone signal other than the audio signal
can be input.
7
LIMLV
AI
*4)
8
MOD
AO
Z
Modulated transmit signal output pin *2)
9
VSS
PWR
-
Negative power supply pin
Normally, apply 0V.
10
SDATA
DB
Z
Serial data input and output control pin
MS1419-E-00
2012/05
-5-
ASAHI KASEI
Pin
number
Pin name
[AK2347B]
Pin
type
Powerdown
status
11
SCLK
DI
Z
12
CSN
DI
Z
13
TEST
DO
L
14
XIN
DB
*5)
15
XOUT
DI
*5)
Function
Serial data clock input pin
Serial data chip select input
This signal is active low.
Output pin for testing
This pin is assigned to test pin for pre-delivery inspection in factory.
Do not connect anything in normal operation.
Pin for connecting a crystal oscillator
A reference clock used within this IC is generated by connecting a
3.6864MHz or 3.579545MHz oscillator between this pin and the
adjacent XOUT pin. For detailed information about the connection
method and the method for supplying an external clock, see
“Recommended External Application Circuits”.
Pin for connecting a crystal oscillator
PWR
−
Positive power supply pin
Connect this pin to a power supply ranging from 2.7V to 3.3V with
less noise. Connect a bypass capacitor of 0.1µF or higher between
this pin and the VSS pin.
TSAOUT
AO
Z
Transmit Sub-Audio signal output pin *2)
RSAOUT
AO
Z
Receive Sub-Audio signal output pin *2)
16
VDD
17
18
19
DIN
AI
Z
Data input pin
This pin is the inverting input pin of DTA1. This pin, with resistors
and capacitors externally connected, forms a amplifier.
An external signal such as a tone signal through CPU port can be
input.
20
DINO
AO
Z
Output pin of DTA1 *1)
21
RXOUT
AO
Z
Receive audio signal output pin *2)
22
FILTERO
AO
Z
RXLPF or TX/RX_HPF block output pin
This pin can be used as a monitor pin for a signal such as a tone
signal.
The output signal on this pin includes a 57.6kHz
sampling-clock component.
So, perform waveform processing
externally as required. *2)
23
RXINO
AO
Z
Output pin of RXA1 *1)
24
RXIN
AI
Z
Demodulated receive signal input pin
Inverting input pin of RXA1. This pin, with resistors and capacitors
externally connected, forms a pre-filter.
Note) A: Analog, D: Digital, PWR: Power, I: Input, O: Output, B: Bi-directional, Z: High-Z, L: Low
*1)
*2)
Output load requirement: [load impedance] > 30kΩ, [load capacitance] < 50pF
Output load requirement: [load impedance] > 10kΩ, [load capacitance] < 50pF
*3)
*4)
AGND (=1/2VDD) level
AGND + 0.256(VDD-AGND) level
*5)
When XOUT pin is set to low level, XIN pin goes to High-Z.
When XOUT pin is set to high level, XIN pin outputs low level.
MS1419-E-00
2012/05
-6-
ASAHI KASEI
[AK2347B]
7. Absolute Maximum Ratings
Parameter
Power Supply Voltage
Ground Level
Input Voltage
Input Current
(Except power supply pin)
Storage Temperature
Symbol
VDD
VSS
VIN
Min.
-0.3
0
-0.3
Max.
4.6
0
VDD+0.3
Units
V
V
V
IIN
-10
+10
mA
Tstg
-55
130
°C
Note) All voltages are relative to the VSS pin.
Caution) If the device is used in conditions exceeding these values, the device may be
destroyed. Normal operations are not guaranteed in such extreme conditions.
8. Recommended Operating Conditions
Parameter
Operating Temperature
Power Supply Voltage
Symbol
Condition
Ta
VDD
AGND
Analog Reference Voltage
Note) All voltages are relative to the VSS pin.
Min.
−40
2.7
Typ.
3.0
1/2VDD
Max.
85
3.3
Units
°C
V
V
Max.
Units
9. Digital DC Characteristics
Parameter
High level input voltage
Low level input voltage
Symbol
VIH1
VIH2
VIL1
VIL2
High level input current
IIH
Low level input current
IIL
High level output voltage
VOH
Low level output voltage
VOL
Condition
SDATA
SCLK, CSN
Min.
0.7VDD
0.8VDD
SDATA
SCLK, CSN
VIH=VDD
SDATA, SCLK, CSN
VIL=0V
SDATA, SCLK, CSN
IOH=+0.2mA
SDATA
IOL=−0.4mA
SDATA
MS1419-E-00
Typ.
V
0.3VDD
0.2VDD
V
10
µA
µA
-10
VDD−0.4
VDD
V
0.0
0.4
V
2012/05
-7-
ASAHI KASEI
[AK2347B]
10. Clock Input Characteristics
Parameter
Symbol
Master Clock Frequency
MCK
High level input voltage
VMCK1_IH
Low level input voltage
VMCK1_IL XIN
Input amplitude
*1)
*2)
VMCK2
Condition
XIN,
XOUT
XIN
XIN
Min.
Typ.
3.6864
3.579545
Max.
Remarks
MHz
1.5
0.2
Units
V
*1)
0.4
V
*1)
1.0
VPP
*2)
When directly connects to XIN pin, refer to “Recommended External Application” 7) Oscillator
circuit Fig. 7.
When connects to XIN pin via capacitor, refer to “Recommended External Application” 7)
Oscillator circuit Fig. 8.
11. Current Consumption
Parameter
Symbol
IDD0
IDD1
Current
Consumption
IDD2
IDD3
IDD4
Condition
Mode 0
OSC:OFF, Audio: OFF, Sub-Audio: OFF
Mode 1
OSC: ON , Audio: OFF, Sub-Audio: OFF
Mode 2
OSC: ON , Audio: ON , Sub-Audio: OFF
Mode 3
OSC: ON , Audio: OFF, Sub-Audio: ON
Mode 4
OSC: ON , Audio: ON , Sub-Audio: ON
MS1419-E-00
Min.
Typ.
Max.
0.08
0.14
0.7
1.0
4.5
5.8
1.6
2.1
5.3
6.7
Units
mA
2012/05
-8-
ASAHI KASEI
[AK2347B]
12. Analog Characteristics
Unless otherwise specified, the following apply: MCK=3.6864MHz, f=1kHz, Emphasis: on,
Compandor: on, Scrambler: off, VR1=VR2=VR3=VR4=0dB, HPF=LMT=1 with the external circuit
shown in page.28 to 32.
“dBx” is a standardized notation to match the operating voltage and is defined by equation 0dBx =
-5+20log(VDD/2)dBm. 0dBm=0.775Vrms.
1) TX Audio system characteristics
Parameter
Condition
Standard input level
@TXINO, EXTINO
Absolute gain
TXINO to MOD
Min.
Typ.
Max.
-10
EXTIN to MOD
EXTIN to MOD, EXTINO=-3dBx
Distortion
When LMT is set to 0
30kHz Low-pass filtering
Limit level
EXTIN to MOD
Without external R adjustment
With external R adjustment
Compressor linearity
TXINO to MOD
TXINO=-44dBx
TXINO=-50dBx
Relative value to 0dB for MOD
level of -10dBx TXINO.
Compressor distortion TXINO to MOD
TXINO=-10dBx
30kHz Low-pass filtering
Noise level with no TXINO to MOD
signal input
C-Message filtering
VR1
TXINO to MOD
Attenuation error
-6.0 dB to 4.5dB, 1.5dB/step
VR2 ATT error
TXINO to MOD
(VR24,23,22,21,20)
-3.2dB to +3.0dB, 0.2dB/step
VR2 ATT error
TXINO to MOD
(VR25=0)
Relative value when -6.4/0dB
is set
Units
Remarks
dBx
-1.5
0
+1.5
dB
-1.5
0
+1.5
dB
-35
dB
dBx
-8.6
-7.6
-6.6
-6.6
-20.0
-24.0
-17.0
-20.0
-14.0
-16.0
dB
-35
dB
-36.5
dBm
-1.5
+1.5
dB
-0.2
+0.2
dB
-6.8
-6.4
-6.0
dB
Min.
Typ.
Max.
Units
2) RX Audio system characteristics
Parameter
Standard Input Level
Absolute gain
Condition
@RXINO
-10
RXINO to FILTERO
RXINO to RXOUT
Expander linearity
RXINO to RXOUT
RXINO=-25dBx
RXINO=-30dBx
Relative value to 0dB for RXOUT
level of -10dBx RXINO
Expander distortion
RXINO to RXOUT
RXINO=-5dBx
30kHz Low-pass filtering
Noise level with no RXINO to RXOUT
signal input
C-Message Filtering
MS1419-E-00
Remarks
dBx
-1.5
0
+1.5
dB
-1.5
0
+1.5
dB
-33.0
-45.0
-30.0
-40.0
-27.0
-35.0
dB
-35
dB
-70
dBm
2012/05
-9-
ASAHI KASEI
Parameter
VR3
Attenuation error
VR4
Attenuation error
VR4 ATT error
(VR45…40=0,0,0,0,0,
0)
[AK2347B]
Condition
RXIN0 to RXOUT
-4.0dB to +3.5dB, 0.5dB/step
RXIN0 to RXOUT
-4.5 to +4.5dB, 1.5dB/step
RXIN0 to RXOUT
Relative value when –18/0dB
is set
Min.
Typ.
Max.
Units
-0.5
+0.5
dB
-0.25
+0.25
dB
-20
-18
-16
dB
Min.
Typ.
-57
Max.
-40
-9.5
+9.0
+8.5
-18
-9.5
+9.0
+10.5
-12
-26
+11.5
-8.5
-40
Units
dB
Remarks
3) Audio Filter Characteristics
3.1) Emphasis: on, Compandor: off, Scrambler: off
Parameter
TX overall
characteristics
Condition
250Hz
300Hz
2.5kHz
3.0kHz
6.0kHz
300Hz
2.5kHz
3.0kHz
6.0kHz
250Hz
300Hz
3.0kHz
6.0kHz
TXINO to MOD
Relative value
to gain at 1kHz
RX overall
characteristics
RXINO to RXAF
Relative value
to gain at 1kHz
-12.5
+6.0
+4.5
-23
-12.5
+6.0
+7.0
-17
-38
+8.5
-11.5
-52
3.2) Emphasis: off, Compandor: off, Scrambler: off
target values)
Parameter
TX overall
characteristics
Condition
TXINO to MOD
Relative value
to gain at 1kHz
300Hz to 2.5kHz
3.0kHz
6.0kHz
RX overall
characteristics
RXINO to RXAF
Relative value
to gain at 1kHz
250Hz
300Hz
350Hz to 3.0kHz
6.0kHz
MS1419-E-00
dB
SPL=0
fc=2.55
K
dB
SPL=1
fc=3.0K
dB
(Design
Min.
250Hz
300Hz to 2.0kHz
2.5kHz
3.0kHz
6.0kHz
Remarks
Typ.
-50
-32
Max.
-38
+1.0
+1.0
-1.0
-28
dB
-26
+1.0
+1.0
-22
-38
+1.0
+1.0
-28
dB
-1.0
-1.5
-4.0
-1.0
-1.5
-49
-1.5
-1.0
-38
Units
dB
Remarks
dB
SPL=0
fc=2.55
K
SPL=1
fc=3.0K
2012/05
- 10 -
ASAHI KASEI
[AK2347B]
• Audio path frequency response for TX
20
10
GAIN(dB)
0
-10
SPL=0
SPL=1
-20
-30
-40
-50
-60
1.E+02
1.E+03
1.E+04
FREQUENCY(Hz)
Figure 1:
TX overall response with pre-emphasis.
20
10
GAIN(dB)
0
-10
SPL=0
SPL=1
-20
-30
-40
-50
-60
1.E+02
1.E+03
1.E+04
FREQUENCY(Hz)
Figure 2:
TX overall response without pre-emphasis.
MS1419-E-00
2012/05
- 11 -
ASAHI KASEI
[AK2347B]
• Audio path frequency response for RX
20
10
GAIN(dB)
0
-10
-20
-30
-40
-50
-60
1.E+02
1.E+03
1.E+04
FREQUENCY(Hz)
Figure 3:
RX overall response with de-emphasis.
20
10
GAIN(dB)
0
-10
-20
-30
-40
-50
-60
1.E+02
1.E+03
1.E+04
FREQUENCY(Hz)
Figure 4:
RX overall response without de-emphasis.
MS1419-E-00
2012/05
- 12 -
ASAHI KASEI
[AK2347B]
4) Scrambler Characteristics
4.1) Scrambler: on, Emphasis: off, Compandor: off, MCKSL=1, SCSL=0/1…3.388kHz
MCKSL=0, SCSL=0 …3.290kHz
Parameter
Carrier frequency
Modulated output
High frequency
rejection
Carrier signal
leakage
Original signal
leakage
Condition
Min.
Typ.
3.388
3.290
Max.
-10
-8
dBx
-50
dBx
-50
dBx
-50
dBx
Modulated output
Remarks
kHz
TXINO to MOD, RXINO to RXOUT
Input level
1.0kHz -10dBx
Measuring-freq. 2.388kHz (3.388kHz)
Measuring-freq. 2.290kHz (3.290kHz)
TXINO to MOD, RXINO to RXOUT
Input level
-12
1.0kHz -10dBx
Measuring-freq. 4.388kHz (3.388kHz)
Measuring-freq. 4.290kHz (3.290kHz)
TXINO to MOD, RXINO to RXOUT
Input level
No signal
Measuring-freq. 3.388kHz
Measuring-freq. 3.290kHz
TXINO to MOD, RXINO to RXOUT
Input level
1.0kHz -10dBx
Measuring-freq. 1.0kHz
4.2) Scrambler: on, Emphasis: off, Compandor: off, MCKSL=0, SCSL=1
Parameter
Carrier frequency
Units
Condition
Min.
Typ.
(Design target values)
Max.
3.390
Units
Remarks
kHz
TXINO to MOD, RXINO to RXOUT
Input level
1.0kHz -10dBx
Measuring-freq. 2.390kHz
High frequency
rejection
TXINO to MOD, RXINO to RXOUT
Carrier signal
leakage
TXINO to MOD, RXINO to RXOUT
Original signal
leakage
TXINO to MOD, RXINO to RXOUT
Input level
1.0kHz -10dBx
Measuring-freq. 4.390kHz
Input level
No signal
Measuring-freq. 3.390kHz
Input level
1.0kHz -10dBx
Measuring-freq. 1.0kHz
MS1419-E-00
-12
-10
-8
dBx
-50
dBx
-50
dBx
-25
dBx
2012/05
- 13 -
ASAHI KASEI
[AK2347B]
5) Sub-Audio filter Characteristics
Unless otherwise specified, the following apply: MCKSL=1, SA5=1, SA4=1, SA3=0, SA2=0, SA1=0,
SA0=1(fc=260.9Hz), VR5=0dB, 250.3Hz sinusoidal wave.
5.1) Analog characteristics
Parameter
Condition
Standard input level
Transmit CTCSS
signal gain
Transmit CTCSS
signal distortion
Min.
@ TSAOUT
Receive CTCSS
signal gain
Receive CTCSS
signal distortion
-2
Units
+2
dB
DINO to TSAOUT
250.3Hz,Duty50%,
585mVp-p(@3V)rectangular wave
30kHz Low-pass filtering
-37
-32
dB
@ RSAOUT
-10
-2
RXINO to RSAOUT
RXINO=-10dBx input
30kHz Low-pass filtering
RXINO to RSAOUT
-6.0 to +6.0dB, 0.5dB/step
dBx
0
+2
dB
-37
-32
dB
+0.5
dB
Max.
+1.0
+1.0
-38
Units
-0.5
Remarks
dBx
0
RXINO to RSAOUT
VR5 Attenuation error
Max.
-10
DINO to TSAOUT
Standard input level
Typ.
5.2) Filter characteristics
Parameter
Condition
Overall characteristics
@fc=260.9Hz
DINO to TSAOUT
Relative value to
gain at 100Hz
50～240Hz
250Hz
300Hz
Min.
-1.0
-1.5
Typ.
Remarks
dB
20
10
GAIN(dB)
0
-10
-20
-30
-40
-50
-60
1.E+01
1.E+02
1.E+03
FREQUENCY(Hz)
Fig.5 Sub-Audio response characteristics
MS1419-E-00
2012/05
- 14 -
ASAHI KASEI
[AK2347B]
13. Level Diagram
1) TX system: TXRX=0
TXA2
EXTIN
f=1kHz
TXINO
TXA1
TXIN
G = 30dB
VR1
Compressor
Pre-emphasis
+4.5
dB
0
-6.0
Crosspoint
-10dBx
0dB
TXHPF
0dB
Splatter
+VR2
Limiter
SMF
+3.0
dB
0
-9.6
-7.6dBx
MOD
0dB
Scrm
/Descrm
0dB
dBx
10
0
0
-5
-5.5
-7.0
-10dBx (Audio)
-10
-10
-10
-10
-19.2
-16
-20
-27
-27dBx
-30
-30dBx
-30
-40
-44
-50
-50
-60
-70
-80
-90
2) RX system: TXRX=1
f=1kHz
RXIN
FILTERO
RXINO
VR3
RXA1
G = 20dB
0
+3.5
dB
-4.0
RXLPF
RXHPF
0dB
+5dB
De-emphasis
Expander
-5dB
Crosspoint
-10dBx
Scrm
/Descrm
VR4
SMF
+4.5
dB
0
-18.0
G = 0dB
RXOUT
-5dB
dBx
10
0
0
-5
-5
-10
-20
-25
-10
-14
-10
-5.5
-10dBx (Typ.)
-20
-25
-28
-25
-30
-40
0dBx (Max.)
-6.5
-40
-30
-40dBx
-45
-50
-50dBx
-50
-60
Note)
dBx is a standardized notation to match the operating voltage and is defined by equation
0dBx = -5 + 20log(VDD/2)dBm.
MS1419-E-00
2012/05
- 15 -
ASAHI KASEI
[AK2347B]
14. Digital AC Timing
1) Serial Interface Timing
AK2347B is connected to a CPU by three-wired interface through CSN, SCLK and SDATA pins,
which can make reading and writing data for control registers.
Serial data named SDATA is consist of 1-bit read and write instruction(R/W), 4-bit address (A3 to
A0) and 8-bit data(D7 to D0) in one frame.
Write mode
CSN
SCLK
SDATA
(Input)
SDATA
(Output)
R/W
A3
A2
A1
A0
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D4
D3
D2
D1
D0
Hi-Z
Read mode
CSN
SCLK
SDATA
(Input)
SDATA
(Output)
R/W
R/W
Hi-Z
Hi-Z
D7
D6
D5
D0
: Instruction bit controls to write data to AK2347B or read back from it.
When set to low, AK2347B is in write mode. When set to high, AK2347B is in read
mode.
A3 to A0: Register address to be accessed.
D7 to D0: Write or read date to be accessed.
(1)
CSN(Chip select) is normally selected high for disable.
When CSN is set to low, serial interface becomes active.
(2)
In write mode, instruction, address and data input from SDATA pin are synchronized and
latched with the rising edge of 14 iterations of SCLK clock. Set to low between address A0
and data D7.
In read mode, instruction and address are synchronized and latched with the rising edge of 5
iterations of SCLK clock. And the register data are output from SDATA pin synchronized with
the falling edge of 9 iterations of SCLK clock. The date between address A0 and data D7 is
unstable.
A CPU port to SDATA pin is fixed to High-Z during the interval that SDATA outputs the read
data.
(3)
AK2347B assumes that write and read is set by 14 iterations SCLK clock while CSN sets to
Low. If SCLK iterations are less or more than 14 clocks, serial data would not set properly.
MS1419-E-00
2012/05
- 16 -
ASAHI KASEI
[AK2347B]
2) Detail Timing Chart
Write mode
Tcsh
Tcss
CSN
Twh
Twl
SCLK
Tds
SDATA
(Input)
R/W
SDATA
(Output)
Hi-Z
Tdh
A3
A2
A1
A0
D7
D6
D1
D0
Read mode
Tcsh
Tcss
Tcd
CSN
Tdd
Tsd
SCLK
Hi-Z
SDATA
(Input)
R/W
SDATA
(Output)
Hi-Z
A3
A2
A1
A0
D7
D6
D1
D0
Rising and falling time
Tr
Tf
SCLK
VIH
VIL
Parameter
CSN setup time
SDATA setup time
SDATA hold time
SCLK high time
SCLK low time
CSN hold time
SDATA Hi-Z setup time
SCLK to SDATA
delay time
CSN to SDATA
delay time
SCLK rising time
SCLK falling time
Symbol
Tcss
Tds
Tdh
Twh
Twl
Tcsh
Tsd
Condition
Tdd
20pF load
Tcd
20pF load
Tr
Tf
Min.
100
100
100
500
500
100
500
Typ.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
500
ns
100
ns
100
100
ns
ns
Note) In digital input timing, rising time is relative to VIH and falling time is relative to VIL.
In digital output timing, rising time is relative to VOH and falling time is relative to VOL.
MS1419-E-00
2012/05
- 17 -
ASAHI KASEI
[AK2347B]
15. Register Function Description
1) Register configuration
Address
Data
Function
D7
D6
D5
D4
D3
D2
D1
D0
Control register 1
BS3
BS2
BS1
TXRX
TXSW2
TXSW1
RXSW
MCKSL
1
Control register 2
TC
EM
PCONT
SPL
SCSL
LMT
HPF
SASW
1
0
Volume register 1
VR54
VR53
VR52
VR51
VR50
VR12
VR11
VR10
0
1
1
Volume register 2
FILSW2
FILSW1
VR25
VR24
VR23
VR22
VR21
VR20
0
1
0
0
Volume register 3
−
−
−
−
VR33
VR32
VR31
VR30
0
1
0
1
Volume register 4
−
−
VR45
VR44
VR43
VR42
VR41
VR40
0
1
1
0
−
−
SA5
SA4
SA3
SA2
SA1
SA0
0
1
1
1
Sub-Audio
frequency
Software-reset &
Revision register
−
−
−
RSTN
1
0/1
0/1
0/1
Reserved
X
X
X
X
A3
A2
A1
A0
0
0
0
0
0
0
0
0
0
0
REVNUM[3:0]
X
X
X
X
Note1) The mark “−” means that a write to those bits does not have any influence on the LSI
operation and read back the writing data.
Note2)
All registers except address 0111 are write and readable registers.
Caution) Never access the mark “X” test register and unlisted bits of VR33 to VR30, VR45 to
VR40 and SA5 to SA1. If an access is made to these addresses inadvertently, the
LSI operation is not guaranteed.
MS1419-E-00
2012/05
- 18 -
ASAHI KASEI
[AK2347B]
2) Descriptions of registers
2.1) Control register 1
Address
Data
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
BS3
BS2
BS1
TXRX
TXSW2
TXSW1
RXSW
MCKSL
0
0
0
1
1
1
1
1
When power-down
2.1.1) Operation mode setting
OSC and AGND
system
TX and RX audio
system
Sub-Audio
system
OFF
OFF
OFF
ON
OFF
OFF
ON
ON
OFF
Mode 3
ON
OFF
ON
Mode 4
ON
ON
ON
BS3
BS2
BS1
Mode name
0
0
0
0
0
1
0
1
0
Mode 0
(Power-down)
Mode 1
(standby)
Mode 2
0
1
1
1
0/1
0/1
2.1.2) TX and RX setting
Data
Item
TXRX
TX-RX switch
RXSW
RX audio mute
Master clock
frequency
MCKSL
Function
Remarks
0
1
TX operation
*1)
RX operation
*2)
*3)
Mute
Normal operation
*4)
3.579545MHz
3.6864MHz
2.1.3) TX path setting
TXSW2
TXSW1
1
1
0
1
1
0
0
0
Function
Remarks
Mute
(AGND → Limiter → Splatter)
Audio system operation
(HPF → Limiter→ Splatter)
External signal operation
(EXTIN pin → Limiter → Splatter)
Audio signal and external signal added together
(HPF+EXTIN pin → Adder → Limiter → Splatter)
*1) When TXRX is set to 0 and RXSW is set to 1, the signal input from the TXIN pin can be output to
the RXOUT pin. In this case, because use of the Scrambler/Descrambler is inhibited, be sure to
set PCONT to 1.
When RXSW is set to 0, the RXOUT pin output is muted.
*2) When TXRX is set to 1 and TXSW2 and TXSW1 are set to 0 and 1 respectively, the signal input
from the RXIN pin can be output to the MOD pin. In this case, because use of the
Scrambler/Descrambler is inhibited, be sure to set PCONT to 1. When TXSW2 and TXSW1 are
set to 1 and 1 respectively, the MOD pin output is muted.
*3) Set the gain level for each circuit block properly according to the level diagrams on page 15.
*4) If RXSW is set to 0, the FILTERO pin output is not muted.
MS1419-E-00
2012/05
- 19 -
ASAHI KASEI
[AK2347B]
2.2) Control register 2
Address
Data
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
1
TC
EM
PCONT
SPL
SCSL
LMT
HPF
SASW
1
1
1
1
0
1
1
1
When power-down
Data
Function
Item
TC
Compandpr
SPL
Splatter
Cut-off frequency
SCSL
Scrambler carrier
frequency
MCKSL is set to 0
MCKSL is set to 1
0
1
OFF (Bypass)
ON (Active)
2.55kHz
3.0kHz
3.290kHz
3.390kHz
3.388kHz
3.388kHz
LMT
Limiter
OFF (Bypass)
ON (Active)
HPF
TX/RX HPF
Sub-Audio
operation
OFF (Bypass)
ON (Active)
SASW
DIN pin → TSAOUT pin
Remarks
RXIN pin → RSAOUT pin
EM
PCONT
Function
1
1
Emphasis: ON (Active),
0
1
Emphasis: OFF (Bypass), Scrambler/Descrambler:OFF (Bypass)
0/1
0
Emphasis: OFF (Bypass), Scrambler/Descrambler:ON (Active)
Remarks
Scrambler/Descrambler: OFF (Bypass)
MS1419-E-00
2012/05
- 20 -
ASAHI KASEI
[AK2347B]
2.3) Volume Register 1
Address
Data
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
0
VR54
VR53
VR52
VR51
VR50
VR12
VR11
VR10
0
1
1
0
0
1
0
0
When power-down
VR54
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
VR53
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
VR52
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
VR51
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
VR50
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
VR12
VR11
VR10
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
MS1419-E-00
VR5 gain (dB)
-6.0
-5.5
-5.0
-4.5
-4.0
-3.5
-3.0
-2.5
-2.0
-1.5
-1.0
-0.5
0.0
+0.5
+1.0
+1.5
+2.0
+2.5
+3.0
+3.5
+4.0
+4.5
+5.0
+5.5
+6.0
VR1 gain (dB)
-6.0
-4.5
-3.0
-1.5
0.0
+1.5
+3.0
+4.5
2012/05
- 21 -
ASAHI KASEI
[AK2347B]
2.4) Volume Register 2
Address
Data
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
1
FILSW2
FILSW1
VR25
VR24
VR23
VR22
VR21
VR20
1
1
1
1
0
0
0
0
When power-down
Remarks
Function
FILSW2
FILSW1
1
1
FILTERO pin output is muted.
0
1
RXLPF circuit signal is output on FILTERO pin.
0/1
0
TX/RX_HPF circuit signal is output on FILTERO pin.
VR25
0
1
VR24
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VR23
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
VR2 gain (dB)
-6.4
0.0
VR22
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
VR21
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
MS1419-E-00
VR20
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
VR2 gain (dB)
-3.2
-3.0
-2.8
-2.6
-2.4
-2.2
-2.0
-1.8
-1.6
-1.4
-1.2
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
+0.2
+0.4
+0.6
+0.8
+1.0
+1.2
+1.4
+1.6
+1.8
+2.0
+2.2
+2.4
+2.6
+2.8
+3.0
2012/05
- 22 -
ASAHI KASEI
[AK2347B]
2.5) Volume Register 3
Address
Data
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
−
−
−
−
VR33
VR32
VR31
VR30
−
−
−
−
1
0
0
0
When power-down
VR33
VR32
VR31
VR30
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
MS1419-E-00
VR3 gain (dB)
-4.0
-3.5
-3.0
-2.5
-2.0
-1.5
-1.0
-0.5
0.0
+0.5
+1.0
+1.5
+2.0
+2.5
+3.0
+3.5
2012/05
- 23 -
ASAHI KASEI
[AK2347B]
2.6) Volume Register 4
Address
Data
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
−
−
VR45
VR44
VR43
VR42
VR41
VR40
−
−
0
1
0
0
1
1
When power-down
VR45
VR44
VR43
VR42
VR41
VR40
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
MS1419-E-00
VR4 gain (dB)
-18.0
-4.50
-4.25
-4.00
-3.75
-3.50
-3.25
-3.00
-2.75
-2.50
-2.25
-2.00
-1.75
-1.50
-1.25
-1.00
-0.75
-0.50
-0.25
0.00
+0.25
+0.50
+0.75
+1.00
+1.25
+1.50
+1.75
+2.00
+2.25
+2.50
+2.75
+3.00
+3.25
+3.50
+3.75
+4.00
+4.25
+4.50
2012/05
- 24 -
ASAHI KASEI
[AK2347B]
2.7) Sub-Audio LPF frequency
Address
Data
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
0
−
−
SA5
SA4
SA3
SA2
SA1
SA0
−
−
1
1
0
0
0
1
When power-down
MCKSL=0(3.579545M)
SA5
SA4
SA3
SA2
SA1
SA0
Divide
*1)
MCKSL=1(3.6864MHz)
Cut-off
Target
Cut-off
Target
Frequency
CTCSS
Frequency
CTCSS
(Hz)
(Hz)
(Hz)
(Hz)
0
0
0
0
0
0
640
59.4
-
61.1
-
0
0
0
0
0
1
630
60.3
-
62.1
-
0
0
0
0
1
0
620
61.3
-
63.1
-
0
0
0
0
1
1
610
62.3
-
64.1
-
0
0
0
1
0
0
600
63.3
-
65.2
-
0
0
0
1
0
1
590
64.4
-
66.3
-
0
0
0
1
1
0
580
65.5
-
67.5
-
0
0
0
1
1
1
570
66.7
-
68.6
-
0
0
1
0
0
0
560
67.8
-
69.9
-
0
0
1
0
0
1
550
69.1
-
71.1
-
0
0
1
0
1
0
540
70.3
-
72.5
67.0
0
0
1
0
1
1
530
71.7
67.0
73.8
-
0
0
1
1
0
0
520
73.1
-
75.2
69.3
0
0
1
1
0
1
510
74.5
69.3
76.7
71.9
0
0
1
1
1
0
500
76.0
-
78.3
-
0
0
1
1
1
1
490
77.6
71.9
79.8
74.4
0
1
0
0
0
0
480
79.2
-
81.5
-
0
1
0
0
0
1
470
80.6
74.4
83.3
77.0
0
1
0
0
1
0
460
82.6
77.0
85.1
79.7
0
1
0
0
1
1
450
84.4
-
87.0
-
0
1
0
1
0
0
440
86.3
79.7
89.0
82.5
0
1
0
1
0
1
430
88.4
82.5
91.0
85.4
0
1
0
1
1
0
420
90.4
-
93.2
-
0
1
0
1
1
1
410
92.7
85.4
95.5
88.5
0
1
1
0
0
0
400
95.0
88.5
97.8
91.5
0
1
1
0
0
1
390
97.4
91.5
100.3
-
0
1
1
0
1
0
380
100.0
-
103.0
94.8
0
1
1
0
1
1
370
102.7
94.8
105.8
97.4
0
1
1
1
0
0
360
105.6
97.4
108.7
100.0
0
1
1
1
0
1
350
108.6
100.0
111.8
103.5
0
1
1
1
1
0
340
111.8
103.5
115.1
107.2
0
1
1
1
1
1
330
115.1
107.2
118.6
110.9
MS1419-E-00
2012/05
- 25 -
ASAHI KASEI
[AK2347B]
MCKSL=0(3.579545M)
SA5
SA4
SA3
SA2
SA1
SA0
Divide
*1)
MCKSL=1(3.6864MHz)
Cut-off
Target
Cut-off
Target
Frequency
CTCSS
Frequency
CTCSS
(Hz)
(Hz)
(Hz)
(Hz)
1
0
0
0
0
0
320
118.8
110.9
122.3
114.8
1
0
0
0
0
1
310
122.5
114.8
126.2
118.8
1
0
0
0
1
0
300
126.6
118.8
123.0
1
0
0
0
1
1
290
131.0
123.0
130.5
135.0
1
0
0
1
0
0
280
135.7
127.3
139.8
131.8
1
0
0
1
0
1
270
140.7
131.8
144.9
136.5
1
0
0
1
1
0
260
146.2
136.5
150.5
141.3
1
0
0
1
1
1
250
152.0
156.5
146.2
1
0
1
0
0
0
240
158.3
141.3
146.2
151.4
163.0
151.4
1
0
1
0
0
1
230
165.2
156.7
170.1
1
0
1
0
1
0
220
172.7
177.9
1
0
1
0
1
1
210
180.9
162.2
167.9
173.8
156.7
162.2
167.9
186.4
173.8
1
0
1
1
0
0
200
190.0
179.9
195.6
179.9
186.2
1
0
1
1
0
1
190
200.0
186.2
192.8
205.9
192.8
1
0
1
1
1
0
180
211.1
203.5
217.3
1
0
1
1
1
1
170
222.9
229.6
1
1
0
0
0
0
160
237.5
1
1
0
0
0
1
150
253.2
1
1
0
0
1
0
140
271.3
1
1
0
0
1
1
130
292.4
210.7
218.1
225.7
233.6
241.8
250.3
(254.1)
(268.8)
300.9
203.5
210.7
218.1
225.7
233.6
241.8
250.3
(254.1)
(268.8)
-
1
1
0
1
0
0
120
316.7
-
326.0
-
1
1
0
1
0
1
110
345.3
-
355.8
-
1
1
0
1
1
0
100
379.9
-
391.3
-
1
1
0
1
1
1
90
422.2
(403.2)
434.7
(403.2)
1
1
1
0
0
0
80
475.0
-
489.0
-
1
1
1
0
0
1
70
542.7
-
559.1
-
*1)
244.5
260.9
279.5
127.3
Divide = 10 x [64 – (register setting value)]
This equation states that Divide is divided number of master clock.
MS1419-E-00
2012/05
- 26 -
ASAHI KASEI
[AK2347B]
2.8) Software reset & revision register
Address
Data
A3
A2
A1
A0
D7
D6
D5
D4
0
1
1
1
−
−
−
RSTN
−
−
−
1
When power-down
D3
D2
D1
D0
REVNUM[3:0]
0
0
1
0
2.8.1) Software rest
When D4: RSTN data is set to 0, software reset is executed and all register data is set to power-down
status and. This register is a write only register and set to 1 automatic after completing software reset.
2.8.2) Revision register
When D3 to D0 data is accessed, users can read the number of mask revision.
This register is a read only register.
MS1419-E-00
2012/05
- 27 -
ASAHI KASEI
[AK2347B]
16. Recommended External Application Circuits
1) TXA1 amplifier
This circuit can be used as the TX microphone amplifier. Set the gain to 30dB or less. If there
is a possibility that a high frequency noise component over 100kHz is input, form a first or second
order anti-aliasing filter. The following gives a sample configuration of a second order LPF with a
gain of 30dB and cut-off frequency of 10kHz:
3
C1=0.47uF
TXINO
C2=33pF
R3
C2
_
+
4
TXIN
R1 C1
R2
C3
TXA1
C3=2200pF
R1=R2=10kΩ
R3=330kΩ
2
AGND
LSI
2) TXA2 amplifier
This amplifier is used for adjusting the gain of the tone signal. Set the gain to 0dB or less.
For high frequency noise over 100kHz, form an anti-aliasing filter. The following gives a sample
configuration of a second order LPF with a gain of 0dB and cut-off frequency of 13kHz:
6
C1=0.47uF
EXTINO
C2=100pF
R3
C2
_
+
R1 C1
5
EXTIN R2
2
AGND
C3
C3=470pF
R1=R2=R3=51kΩ
TXA2
LSI
MS1419-E-00
2012/05
- 28 -
ASAHI KASEI
[AK2347B]
3) RXA1 amplifier
This amplifier is used for adjusting the gain of the RX signal. Set the gain to 20dB or less.
For high frequency noise over 100kHz, form an anti-aliasing filter. The following gives a sample
configuration of a second order LPF with a gain of 20dB and cut-off frequency of 39kHz:
23
C1=0.47uF
RXINO
C2=33pF
R3
C2
_
+
24
RXIN
2
AGND
R1 C1
R2
C3
RXA1
C3=560pF
R1=10kΩ
R2=9.1kΩ
R3=100kΩ
LSI
4) DTA1
amplifier
This amplifier is used for adjusting the gain of the signal to Sub-Audio Programmable LPF.
Set the gain to 0dB or less. For high frequency noise over 100kHz, form an anti-aliasing filter.
The following gives a sample configuration of a second order LPF with a gain of 0dB and cut-off
frequency of 7.2kHz:
20
C1=0.47uF
DINO
C2=220pF
R2
C2
_
+
R1 C1
DIN
19
C3=470pF
R1=R2=100kΩ
DTA1
LSI
MS1419-E-00
2012/05
- 29 -
ASAHI KASEI
[AK2347B]
5) Power supply stabilizing capacitors
Connect capacitors between VDD and VSS pins to eliminate ripple and noise included in power
supply. For maximum effect, the capacitors should be placed at a shortest distance between the
pins.
VDD
16
VDD
C1=22uF (Electrolytic cap)
C2
C1
C2=0.1uF (Ceramic cap)
VSS
9
VSS
LSI
6) AGND stabilizing capacitors
It is recommended that capacitors with 0.3µF or lager be connected between VSS and the AGND
and AGNDIN pins to stabilize the AGND signal. The capacitors must be placed as close to the
pins as possible.
1
AGNDIN
2
AGND
C
C
C=1uF
LSI
MS1419-E-00
2012/05
- 30 -
ASAHI KASEI
[AK2347B]
7) Oscillator circuit
When the built-in oscillator circuit is to be used, connect a 3.6864MHz or 3.579545MHz crystal
oscillator and a capacitor as shown in Fig. 6. The internal buffer is designed to allow stable
oscillation of a crystal oscillator for the electrical equivalent circuitry with a resonance resistance of
150Ω (Max.) and a shunt capacitance of 5pF (Max.).
It is recommended that 22pF capacitors be connected externally so that the total load capacitance
is 16pF (5pF + 22pF//22pF) or less. Place the oscillator, resistor, and capacitors as close to the
XIN and XOUT pins as possible.
When an external clock is to be supplied, connect the clock line as shown in Fig. 7 or Fig. 8
according to the clock amplitude level.
The circuit in the first stage of the XIN pin has a constant threshold voltage (0.8V). Therefore, if
the high level of the input clock is 1.5V or higher and the low level is 0.4V or lower, connect the
clock signal as shown in Fig. 7. If the input clock amplitude (p-p value) is between 0.2V and 1.0V,
connect the clock signal as shown in Fig. 8.
When the clock is to be shared with peripheral ICs, the clock must be input and output on the XIN
pin. The clock amplitude must not exceed the absolute maximum ratings.
External Clock IN
22pF
XIN
14
3.6864MHz
1MΩ
XIN
3.6864MHz
3.579545MHz
3.579545MHz
XOUT
15
22pF
XOUT
LSI
LSI
Fig. 7
Fig. 6
XIN
0.01uF
External Clock IN
3.6864MHz
1MΩ
3.579545MHz
XOUT
LSI
Fig. 8
MS1419-E-00
2012/05
- 31 -
ASAHI KASEI
[AK2347B]
8) LIMLV pin
The LIMLV pin is used for adjusting the limit level of the limiter circuit. This pin may be left open
or may be used by connecting resistors as shown in the figure below.
When the pin is left open, a predetermined limit level can be obtained. The limit level is
expressed as follows:
HVref = 0.256 × (VDD - AGND) [Vo-p]
For example, let VDD be 3V. The limit level is calculated as follows:
Hvref = 0.256 × (3.0 - 1.5) = 0.384Vo-p Then, 1.5 ±0.384V is the typical value of the limit level.
When a DC voltage higher than the AGND voltage level (= 1/2VDD) is applied to the pin through
resistors, the limit level can be adjusted. The limit level is the difference between LIMLV and
AGND and is expressed as AGND ±(LIMLV - AGND).
Let VDD be 3V. The limit level is calculated as follows:
LIMLV=1.6V
→
1.5 ±0.1V
1.7V
→
1.5 ±0.2V
1.8V
→
1.5 ±0.3V
1.9V
→
1.5 ±0.4V
1.933V →
1.5 ±0.433V (equivalent to -6.6dBx (Max.))
Then, the above values are obtained as the typical limit levels.
Because AGND level is used as the reference level for the limiter circuit operation as mentioned
above, when resistors are connected, they should be connected so that VDD and AGND are
separated by these resistors to supply a DC level to the LIMLV pin. In addition, make
adjustments so that the sum of resistance (R1 + R2) is around 51kΩ.
VDD
R1
7
LIMLV
R2
R1+R2
2
AGND
VSS
LSI
MS1419-E-00
2012/05
- 32 -
ASAHI KASEI
[AK2347B]
17. Packaging
• Marking
AKM
AK2347
YWWLZ
[ Contents of YWWLZ ]
Y:
Last digit of calendar year. (Year 2011->1, 2012->2)
WW: Manufacturing week number.
L:
Lot identification, given to each product lot which is made in a week.
LOT ID is given in alphabetical order (A, B, C…).
Z:
Assembly plant code
8.40 Max
13
1
12
5.9 Max
24
7.90±0.20
0.22±0.05
0° to 8°
0.13 M
0.65±0.08
0.60±0.15
• 24-pin SSOP Mechanical Outline
0.30±0.10
Unit : mm
MS1419-E-00
2.10 Max
0.10±0.10
0.10
2012/05
- 33 -
ASAHI KASEI
[AK2347B]
18. Important Notice
IMPORTANT NOTICE
 These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales
office of Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to current
status of the products.
 Descriptions of external circuits, application circuits, software and other related information
contained in this document are provided only to illustrate the operation and application examples
of the semiconductor products. You are fully responsible for the incorporation of these external
circuits, application circuits, software and other related information in the design of your
equipments. AKM assumes no responsibility for any losses incurred by you or third parties arising
from the use of these information herein. AKM assumes no liability for infringement of any patent,
intellectual property, or other rights in the application or use of such information contained herein.
 Any export of these products, or devices or systems containing them, may require an export
license or other official approval under the law and regulations of the country of export pertaining
to customs and tariffs, currency exchange, or strategic materials.
 AKM products are neither intended nor authorized for use as critical componentsNote1) in any
safety, life support, or other hazard related device or systemNote2), and AKM assumes no
responsibility for such use, except for the use approved with the express written consent by
Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be
expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of
the device or system containing it, and which must therefore meet very high standards of
performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or
maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other
fields, in which its failure to function or perform may reasonably be expected to result in loss
of life or in significant injury or damage to person or property.
 It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or
otherwise places the product with a third party, to notify such third party in advance of the above
content and conditions, and the buyer or distributor agrees to assume any and all responsibility
and liability for and hold AKM harmless from any and all claims arising from the use of said
product in the absence of such notification.
MS1419-E-00
2012/05
- 34 -