[AK2331] AK2331 DAC Type 8-bit 4-channel Electronic Volume Features • 8-bit 4 channels of built-in multiplication D/A converters • Support for external one-path, internal three-path D/A converter reference voltages • Built-in buffer amplifier with low distortion (-60dB typ.) and rail-to-rail operation • Support for 3V control and 5V operation because of the three-wire serial system with separate power supplies • Operating voltage range: 2.6 to 5.5V • Operating temperature range: -40 to +85°C • Package： 16-pin QFNJ (3.0mm x 3.0mm x 0.70mm, 0.5-mm pitch) Overview The AK2331 is an electronic volume into which 8 bit 4 channels of multiplication D/A converters are integrated on a single chip. The reference voltage of the D/A converter can be selected from one external path (VREF pin level) and internal three paths (VSS, AVDD, AVDD/2) for each channel and it can be used as a normal D/A converter or an electronic volume that attenuates signals from input pins VIN0 to VIN3. A buffer amplifier is incorporated as the subsequent stage of the D/A converter, which provides rail-to-rail output and a signal with a distortion of -60dB. In operational setting, the three-wire serial system, which synchronizes serial input (SDATA) consisting of a 4-bit address and 8-bit data with the CSN and SCLK signals, is adopted, a power supply (DVDD) is provided separately from the D/A converter, and 3V serial control and 5V D/A converter operation are enabled. In addition, settings can be made so that the AVDD/2 level, which was generated internally, is output to VOUT0 to VOUT3 pins through the buffer amplifier by bypassing the D/A converter or the buffer amplifier is powered down. A 16-pin small and low-profile QFNJ package (3.0mm square x 0.70mm height) is employed to achieve high-density packaging. MS0903-E-00 2008/03 -1- [AK2331] Contents Features......................................................................................................... 1 Overview ........................................................................................................ 1 Contents......................................................................................................... 2 Block Diagram................................................................................................ 3 Pin Assignments ............................................................................................ 3 Block Functions.............................................................................................. 4 Pin Functions ................................................................................................. 5 Absolute Maximum Ratings ........................................................................... 6 Recommended Operating Conditions ............................................................ 6 Current Consumption..................................................................................... 6 Digital DC Characteristics .............................................................................. 7 System Reset................................................................................................. 7 Analog Characteristics ................................................................................... 8 Digital AC Timing ......................................................................................... 11 Register Functions ....................................................................................... 12 Recommended External Circuit Examples................................................... 15 Package ....................................................................................................... 16 Important Notice........................................................................................... 17 MS0903-E-00 2008/03 -2- [AK2331] Block Diagram 8-bit Latch0 8 8-bit DAC0 8 8-bit DAC1 8 8-bit DAC2 8 8-bit DAC3 − + VOUT0 VIN0 CSN SCLK SDATA RSTN Control Register 8 8-bit Latch1 Channel & Address Decoder 8-bit Latch2 − + VOUT1 VIN1 − + VOUT2 VIN2 DVDD + 8-bit Latch3 VSS − + VOUT3 VIN3 + AVDD AVDD, AVDD/2, VSS VREF Pin Assignments VREF AVDD VSS DVDD Pin assignments (top view) 12 11 10 9 VOUT2 14 7 SCLK VOUT3 15 6 CSN VIN3 16 5 RSTN 1 2 3 4 VIN1 SDATA VOUT1 8 VOUT0 13 VIN0 VIN2 MS0903-E-00 2008/03 -3- [AK2331] Block Functions Block Control register Channel & address decoder 8-bit Latch0 to Latch3 Function The control register inputs serial data (SDATA) consisting of a 4-bit address and 8-bit data in sync with the CSN and SCLK signals to set register data. When a system reset is performed through the RSTN pin on power-up, all registers are initialized. The same reset (soft reset) can also be made by the SRST register (refer to register descriptions). The channel & address decoder decodes the data set by the control register and sets the corresponding D/A converter and reference voltage. The 8-bit Latch0 to Latch3 store the register data of the control register. 8-bit DAC0 to DAC3 The 8-bit DAC0 to DAC3 are 8-bit D/A converters set by the data latched in the previous stage. Buffer The buffer is a buffer amplifier that performs rail-to-rail operation. MS0903-E-00 2008/03 -4- [AK2331] Pin Functions Pin No. Pin name Pin type Pin status at system reset 5 RSTN DI Z Reset pin 6 CSN DI Z Chip select input pin for serial interface data 7 SCLK DI Z Clock input pin for serial interface data 8 SDATA DI Z I/O pin for serial interface data 9 DVDD PWR - 10 VSS PWR - 11 AVDD PWR - 12 VREF AI Z 1 VIN0 AI L 4 VIN1 AI L 13 VIN2 AI L 16 VIN3 AI L 2 VOUT0 AO Z 3 VOUT1 AO Z 14 VOUT2 AO Z 15 VOUT3 AO Z Note Function Digital VDD power supply pin Connect this pin to a 2.6 to 5.5V power supply. Connect a bypass capacitor of 0.1μF or greater between this pin and the VSS pin. VSS power supply pin Always apply a voltage of 0V to this pin. Analog VDD power supply pin Connect this pin to a 2.6 to 5.5V power supply. Connect a bypass capacitor of 0.1μF or greater between this pin and the VSS pin. Apply a voltage so that DVDD is equal to or less than AVDD. D/A converter reference voltage input pin D/A converter input pin D/A converter/buffer amplifier output pin A: Analog, D: Digital, PWR: Power, I: Input, O: Output, Z: High-Z, L: Low MS0903-E-00 2008/03 -5- [AK2331] Absolute Maximum Ratings Parameter Symbol Min. Max. Unit AVDD -0.3 6.5 V DVDD -0.3 6.5 V Ground level VSS 0 V Input voltage VIN -0.3 Input current (excluding power pins) IIN -10 0 AVDD+0.3 DVDD+0.3 +10 mA Storage temperature Tstg -55 130 °C Power supply voltage Note V All voltages are relative to the VSS pin. Caution If the device is used in conditions exceeding these values, the device may be destroyed. Normal operation is not guaranteed in such extreme conditions. Recommended Operating Conditions Parameter Symbol Condition Min. Typ. Max. Unit +85 °C Operating temperature Ta -40 Operating power supply voltage AVDD 2.6 5.0 5.5 V 2.6 5.0 5.5 V 100 pF Typ. Max. Unit 1 20 μA 0.6 1.2 mA 0.75 1.5 mA Analog output load capacity Note DVDD DVDD ≤ AVDD AOC All voltages are relative to the VSS pin. Current Consumption Parameter Symbol SIDD Current consumption IDD1 IDD2 Note Condition DVDD = AVDD = 5V VIN = AVDD, DAREF:VSS (On a system reset) DVDD = AVDD = 5V VIN = AVDD, DAREF:VSS VOUT[7:0] = 0x80 DVDD = AVDD = 5V VIN = AVDD, DAREF:AVDD/2 VOUT[7:0] = 0x00 Min. DACREF shows the internal setting level of DAC reference voltage. Current consumption does not include VIN pins input current and output load current. MS0903-E-00 2008/03 -6- [AK2331] Digital DC Characteristics Parameter Symbol High level input voltage VIH Low level input voltage VIL High level input current IIH Low level input current IIL Condition CSN, SCLK, SDATA, RSTN CSN, SCLK, SDATA, RSTN VIH = DVDD CSN, SCLK, SDATA, RSTN VIL = 0V CSN, SCLK, SDATA, RSTN Min. Typ. Max. 0.8DVDD Unit V 0.2DVDD V 1 μA μA -1 System Reset Parameter Symbol Hardware reset signal input width tRSTN Condition RSTN pin Min. Typ. Max. 1 SRST register Software reset Unit Remarks μs *1) *2) *1) 35ms or more after power-on, be sure to perform a hardware reset operation (register initialization). When a low pulse is input for 1μs or more, a reset is made. At this time, set the digital input (DI) pins: RSTN to high, CSN to high, and SCLK to low. tRSTN VIH RSTN VIL *2) When the SRST[7:0] register is set to 0xAA (10101010), a software reset is made. This setting initializes all registers. For details, refer to "Register Functions". MS0903-E-00 2008/03 -7- [AK2331] Analog Characteristics Unless otherwise specified, the following apply: AVDD = 4.5 to 5.5V, VSS = 0V, AVDD ≥ VIN, VREF = 0V to AVDD, Ta = -40 to +85°C. DACREF shows an internal setting level of DAC reference voltage. Parameter Symbol Condition VREF pin leak current IVREF VIN = AVDD = 5V VREF = 0V VREF pin input voltage range VVREF VIN = AVDD = 5V Resolution RES Min. 0.2 Max. Unit 10 μA AVDD-0.2 V 8 VIN = AVDD = 5V -1 DACREF: VSS Nonlinearity |IAO| = 0μA INL -1.5 *1) VOUT = 0x02 to 0xFF |IAO| = 0μA VIN = AVDD, DACREF: VSS VOUT[7:0] = 0x00 VAO1 |IAO| = 0μA VIN = AVDD, AVDD-0.1 DACREF:VSS Buffer amplifier output VOUT[7:0] = 0xFF voltage range |IAO| ≤ 1mA VIN = AVDD, DACREF: VSS VOUT[7:0] = 0x00 VAO2 |IAO| ≤ 1mA VIN = AVDD, AVDD-0.4 DACREF: VSS VOUT[7:0] = 0xFF AVDD/2 output voltage AVDD = 5V, VAO3 2.45 |IAO| ≤ 1mA when AVDD2O[7:0] is set AVDD = 5V, DACREF: AVDD/2 Maximum input frequency FIN VIN = 3Vp-p, 10kHz 2.7 VOUT[7:0] = 0xFF RL = 22kΩ, CL = 100pF AVDD = 5V, DACREF: AVDD/2 VIN = 3Vp-p, 1kHz Output distortion SINAD VOUT[7:0]=0x0A to 0xFF 56 RL = 22kΩ, CL = 100pF 30kHz LPF used *4) Differential nonlinearity Typ. DNL MS0903-E-00 bit +1 LSB +1.5 LSB 0.1 V V 0.4 V V 2.5 2.55 V 3.0 Vp-p 60 dB 2008/03 -8- [AK2331] Parameter Symbol Condition DAC output settling time tLDD1 VOUT[7:0] = 0x10↔0xEF Until output reaches the half LSB of the final value. RS = 2.2kΩ, RL = 22kΩ, CL = 1000pF *3) VIN pin input impedance RIN 135 kΩ ROUT 20 Ω VOUT pin output impedance Min. Typ. Max. Unit 300 μs *1) Error between the I/O curve and the ideal line connecting the output voltage for the 02 setting and the output voltage for the FF setting. Unless otherwise specified, the following apply: AVDD = 2.6 to 3.3V, VSS = 0V, AVDD ≥ VIN, VREF = 0V to AVDD, Ta = -40°C to +85°C DACREF shows an internal setting level of DAC reference voltage. Parameter Resolution Symbol Condition Min. RES Max. 8 VIN = AVDD = 3V -1 DACREF: VSS Nonlinearity |IAO| = 0μA INL -1.5 *2) VOUT = 0x02 to 0xFF |IAO| ≤ 600μA VIN = AVDD, DACREF: VSS VOUT[7:0] = 0x00 Buffer amplifier output VAO4 voltage range |IAO|≤ 600μA VIN = AVDD, AVDD-0.4 DACREF: VSS VOUT[7:0] = 0xFF AVDD = 3V, DACREF: AVDD/2 VIN = 1.8Vp-p, 1kHz Output distortion DISTN VOUT[7:0]=0x0A to 0xFF 45 RL = 22kΩ, CL = 100pF 30kHz LPF used *4) Differential nonlinearity Typ. DNL Unit bit +1 LSB +1.5 LSB 0.4 V V 55 dB *2) Error between the I/O curve and the ideal line connecting the output voltage for the 02 setting and the output voltage for the FF setting. MS0903-E-00 2008/03 -9- [AK2331] *3) Load condition when AK2331 is used as DAC (Load condition when “DAC output settling time” is measured) R RS=2.2kΩ _ + CL=1000pF RL=22kΩ VOUT0…3 LSI *4) Load condition when AK2331 is used as Attenuator (Load condition when “Output distortion” is measured) R _ + CL=100pF RL=22kΩ VOUT0…3 LSI MS0903-E-00 2008/03 - 10 - [AK2331] Digital AC Timing Serial interface timing The AK2331 writes data via the three-wire synchronous serial interface by means of CSN, SCLK, and SDATA. SDATA (serial data) consists of a register address (starting from the MSB, A3 to A0) and control data (starting from the MSB, D7 to D0). <1> CSN (chip select) is normally set to the high level. When CSN is set to the low level, the serial interface becomes active. <2> When a write operation is performed, an address and data are input in synchronization with the rising edges of 12 SCLK clock pulses while CSN is low. <3> A write setting is made on the assumption that 12 clock pulses are input from SCLK while CSN is low. Note that if clock pulses more than or less than 12 clock pulses are input, data cannot be set correctly. tCSLH tCSS tCSHH CSN tWH tWL SCLK tDS SDATA A3 tDH A2 A1 A0 D7 D6 D1 D0 Rising and falling times tR tF SCLK VIH VIL Parameter CSN setup time SDATA setup time SDATA hold time SCLK high time SCLK low time CSN low hold time CSN high hold time DAC output setting time SCLK rising time SCLK falling time Symbol tCSS tDS tDH tWH tWL tCSLH tCSHH tLDD Condition VOUT[7:0]= 0x10↔0xEF Until output reaches the half LSB of the final value. RS=2.2kΩ, L=22kΩ, CL=1000pF tR tF Min. 100 100 100 500 500 100 100 Typ. Max. Unit ns ns ns ns ns ns ns 300 μs 100 100 ns ns Note Digital input timing measurements are made at 0.5DVDD for rising and falling edges. MS0903-E-00 2008/03 - 11 - [AK2331] Register Functions 1) Register configuration Address Data Function D7 D6 D5 D4 D3 D2 D1 D0 VOUT0 register VOUT07 VOUT06 VOUT05 VOUT04 VOUT03 VOUT02 VOUT01 VOUT00 1 VOUT1 register VOUT17 VOUT16 VOUT15 VOUT14 VOUT13 VOUT12 VOUT11 VOUT10 1 0 VOUT2 register VOUT27 VOUT26 VOUT25 VOUT24 VOUT23 VOUT22 VOUT21 VOUT20 0 1 1 VOUT3 register VOUT37 VOUT36 VOUT35 VOUT34 VOUT33 VOUT32 VOUT31 VOUT30 0 1 0 0 Not used − − − − − − − − 0 1 0 1 Not used − − − − − − − − 0 1 1 0 Not used − − − − − − − − 0 1 1 1 Not used − − − − − − − − 1 0 0 0 VREF register DA3REF1 DA3REF0 DA2REF1 DA2REF0 DA1REF1 DA1REF0 DA0REF1 DA0REF0 1 0 0 1 Not used − − − − − − − − 1 0 1 0 AVDD/2 register − − − − AVDD2O3 AVDD2O2 AVDD2O1 AVDD2O0 1 0 1 1 BUFON register − − − − BUFON3 BUFON2 BUFON1 BUFON0 1 1 0 0 Software reset 1 1 0 1 VOUT0 to VOUT3 Output control － － － － CTRL3 CTRL2 CTRL1 CTRL0 1 1 1 0 Not used − − − − − − − − 1 1 1 1 Not used − − − − − − − − A3 A2 A1 A0 0 0 0 0 0 0 0 0 0 0 Note SRST[7:0] An access to data indicated by "-" does not have any effect on the LSI operation. 2) Descriptions of registers 2.1) VOUT register Address A3 A2 A1 A0 Data D7 D6 D5 D4 D3 D2 D1 D0 VOUT06 VOUT05 VOUT04 VOUT03 VOUT02 VOUT01 VOUT00 0 0 0 0 VOUT07 ↓ 0 ↓ 0 ↓ 1 ↓ 1 ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ VOUT37 VOUT36 VOUT35 VOUT34 VOUT33 VOUT32 VOUT31 VOUT30 0 0 0 0 0 0 0 0 Initial value D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 VOUT = (VIN - VREF) • 0/256 + VREF 0 0 0 0 0 0 0 1 VOUT = (VIN - VREF) • 1/256 + VREF 0 0 0 0 0 0 1 0 VOUT = (VIN - VREF) • 2/256 + VREF 0 0 0 0 0 0 1 1 VOUT = (VIN - VREF) • 3/256 + VREF ↓ 1 ↓ 1 ↓ 1 ↓ 1 ↓ 1 ↓ 1 ↓ 1 ↓ 0 ↓ VOUT = (VIN - VREF) • 254/256 + VREF 1 1 1 1 1 1 1 1 VOUT = (VIN - VREF) • 255/256 + VREF MS0903-E-00 VOUT0 to VOUT3 output 2008/03 - 12 - [AK2331] 2.2) VREF registers Address Data A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 DA3REF1 DA3REF0 DA2REF1 DA2REF0 DA1REF1 DA1REF0 DA0REF1 DA0REF0 0 0 0 0 0 0 0 0 Initial value DA3REF1 to DA0REF1 DA3REF0 to DA0REF0 DAC reference voltage 0 0 VSS (internal) 0 1 AVDD (internal) 1 0 AVDD/2 (internal) 1 1 VREF (external) 2.3) A3 AVDD/2 register Address A2 A1 A0 1 0 1 0 Initial value Data AVDD2O3 to AVDD2O0 Note 2.4) Remarks Data D7 D6 D5 D4 D3 D2 D1 D0 － － － － AVDD2O3 AVDD2O2 AVDD2O1 AVDD2O0 0 0 0 0 0 0 0 0 Function Item Remarks 1 Bypasses the DAC and Internal AVDD/2 DAC output outputs the AVDD/2 level output through buffer. Internal generated AVDD/2 level can be output to VOUT0 to VOUT3 pins by setting this register. 0 BUFON register Address Data A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 1 － － － － BUFON3 BUFON2 BUFON1 BUFON0 0 0 0 0 0 0 0 0 Initial value Data Item BUFON3 to BUFON0 DAC buffer operation 2.5) Function 0 Powers down buffer and outputs Hi-Z. Buffer output Software reset register Address A3 A2 A1 A0 1 1 0 0 Initial value Remarks 1 Data D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 SRST[7:0] 0 0 0 0 0 When the SRST[7:0] register is set to 0xAA (10101010), a software reset is performed. This setting initializes all registers. Upon completion of a software reset, the register is set to 0. MS0903-E-00 2008/03 - 13 - [AK2331] 2.6) VOUT0～VOUT3 Control register Address Data A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 1 − − − − CTRL3 CTRL2 CTRL1 CTRL0 − − − − 0 0 0 0 Initial Value Data CTRL3 to CTRL 0 Item VOUT0 to VOUT3 Output control Function 0 1 VOUT［7:0］data is output VOUT［7:0］data is held Remarks Latch-timing of each DAC data can be matched by the CTRL register setting. After VOUT[7:0] is set, when CTRL register is set to “0”, VOUT[7:0] data is reflected in the DAC output immediately. When CTRL register is set to “1”, DAC output will not be affected regardless of changes made in VOUT[7:0] data. In this case VOUT[7:0] data output by DAC will remain the same as that of data when setting CTRL register to “1”. The data will be reflected in the DAC output when the timing is set to “0”. MS0903-E-00 2008/03 - 14 - [AK2331] Recommended External Circuit Examples 1) Power supply stabilizing capacitors Connect capacitors between the VDD and VSS pins to eliminate ripple and noise included in the power supply as shown below. For maximum effect, the capacitors should be placed at a shortest distance between the pins. AVDD DVDD C1 = 0.1μF (Ceramic cap) C2 C1 C2 = 4.7μF (Electrolytic cap) VSS LSI 2) External VIN0 to VIN3 capacitor When inputting an analog signal to the VIN pin, connect a capacitor to adjust the DC offset of the input signal and the internal operation point in the LSI device. This forms a high-pass filter with fc being about 130Hz. VIN0 to VIN3 C C = 0.01μF LSI MS0903-E-00 2008/03 - 15 - [AK2331] Package 1) Marking 2331 XYYZK ● 2331 X: Least significant digit of the year of production Y: Week of production Z: Identification code of production lot K: Consignment code Part number Date code 2) External dimensions Package type: 16-pin QFNJ (3.0mm x 3.0mm x 0.70mm, 0.5-mm pitch) 3.00±0.10 1.80 B 1.50±0.05 12 13 5 16 1.50±0.05 8 0.75 A 1.50 3.00±0.10 9 0.10 S A B 0.30±0.07 4 1 0.22±0.05 1.80 1.50 CO.3 0.05 M S A B 0.05 S 0.12～ 0.23 0.50 0.00～ 0.05 A 0.70 0.75MAX 0.05MAX S 0.17～ 0.27 【 Detail figure of A】 Note The exposed pad at the center of the back of the package must be connected to VSS or opened. MS0903-E-00 2008/03 - 16 - [AK2331] Important Notice IMPORTANT NOTICE z These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status of the products. z AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. z Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z AKEMD products are neithe r intended nor authorized for use as critical components N o t e 1 ) in any safety, life support, or other hazard related device or system N o t e 2 ) , and AKEMD assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKEMD. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any and all claims arising from the use of said product in the absence of such notification. MS0903-E-00 2008/03 - 17 -