AK2346A

[AK2346A]
AK2346A
Two-way Radio Audio Processor
1. Features
• Audio processing
• TX and RX amplifier
• Pre/De-emphasis circuit
• Compressor and Expander with no external components
• Scrambler and De-scrambler in frequency inversion type with 16 different carrier clocks
• Limiter with level adjuster
• Splatter filter for wide and narrow band
• Digital controlled amplifier for microphone, modulator and demodulator sensitivity
• 1200/2400bit/s MSK Modem with frame detection
• Wide range operation voltage: 2.6V to 5.5V, temperature: -40 to 85 °C
• Oscillator circuit for 14.7456MHz crystal
• Serial control interface operation
• Compact plastic packaging, 24-pin QFNJ (4.0 x 4.0 x 0.75mm 0.5mm pitch)
2. Description
AK2346A includes audio filter, limiter, splatter filter, Compandor, scrambler, MSK Modem, which is
highly integrated two-way radio baseband functions for FRS and LMR.
Audio high-pass filter shows a high attenuation in magnitude response characteristics less than
250Hz that supports to eliminate a sub-audio tone clearly.
TX limiter for deviation control has a limiting level adjuster controlled by a 4-bit signal level adjuster.
Splatter filter has the magnitude response for narrowband (fc=2.55kHz) and wideband (3.0kHz) to
meet various regulatory agencies in the world wide.
Compandor is no adjustment type because it includes all parametric components inside the chip.
Scrambler circuit is composed of frequency inversion circuit by double balanced mixer that has 16
different carrier clocks.
MSK Modem for data communication can be chosen either 2400bit/s or 1200bit/s. 2400bit/s data rate
provides a high speed data transmission and 1200bit/s supports a low BER (bit error rate)
performance that is suitable for under weak electrical field condition application.
There are four signal level adjusters for microphone, modulator and demodulator sensitivity by digital
controlled amplifier (volume).
MS1289-E-04
2013/12
-1-
[AK2346A]
3. Contents
1. Features ··········································································································· 1
2. Description ········································································································ 1
3. Contents ··········································································································· 2
4. Block Diagram ··································································································· 3
5. Circuit Configuration ··························································································· 4
6. Pin/Function ······································································································ 5
7. Absolute Maximum Ratings ·················································································· 8
8. Recommended Operating Conditions ····································································· 8
9. Digital DC Characteristics ···················································································· 8
10. Clock Input Characteristics ················································································· 9
11. System Reset ·································································································· 9
12. Power Consumption ·························································································10
13. Analog Characteristics ······················································································11
14. Level Diagram ·································································································16
15. Serial Interface Configuration ·············································································17
16. Digital AC Timing ·····························································································27
17. MSK Modem Description ···················································································30
18. Recommended External Application Circuits ·························································33
19. Packaging ······································································································36
20. Important Notice ······························································································37
MS1289-E-04
2013/12
-2-
[AK2346A]
16
TXINO
20
TC
19
+
TXA1
TXIN
VR1
(HPF)
Adder
1
Compressor
10
RXIN
17
+
TXA2
PreEmphasis
DAC
TX/RX
_HPF
+
RXA1
VR3
TXRX
PCONT
RXLPF
LIMSW
22
Adder
2
fc = 300Hz
TXRX
21
TXSW2,1,0
-18 to +4.5/1.5dB
11
RXINO
EM
EXTIN2
EXTIN1
EXTINO
4. Block Diagram
VR2
Limiter
Scrambler/
Descrambler
HPFSW
TXRX
PCONT
-4 to +3.5/0.5dB
-9.6 to +3.0
/0.2dB
MOD
SMF
fc = 2.55kHz
/3.0kHz
13
PCONT
DeEmphasis
Expander
RXSW
12
Splatter
EM
SMF
VR4
TC
RXOUT
-18,-4.5 to +4.5
/0.25dB
FILTERO
FILSW1,0
6
DIV
MSK
BPF
MSK
Demodulator
XIN
OSC 5
XOUT
MSK
Modulator
Power ON
Power ON
at Mode 1,2,3,4 at Mode 2,4
Control
Register
Power ON
at Mode 2,3,4
Power ON
at Mode 3,4
AGND
MSKSW1,0
15
+
+
AGND
+
AGNDIN
14
AVDD
+
DVDD
VSS2
MS1289-E-04
9
8
VSS1
7
18
23
RSTN
4
DIR
3
SCLK
2
DIO
MSKDATA
MSKCLK
1
24
2013/12
-3-
[AK2346A]
5. Circuit Configuration
Block
TXA1
VR1
(HPF)
Compressor
Pre-emphasis
TX/RXHPF
Scrambler/
Descrambler
Adder1/2
Limiter
DAC
VR2
Splatter
SMF
RXA1
VR3
RXLPF
De-emphasis
Expander
VR4
TXA2
Description
The operational amplifier for transmit audio gain adjustment and for the filter to eliminate
aliasing noise by the SCF(switched capacitor filter) in the following stage. Please select
an external resistor and capacitor to set the gain less than 30dB and the cut-off frequency
to about 10kHz.
Digitally controlled amplifier (volume) for transmit audio signal level which is adjustable in
1.5dB steps over a –18.0dB to +4.5dB range by setting VR13 to VR10 register.
The circuit to compress transmits audio signal level by 1/2 in dB scale.
Standard cross-point is –10dBx. TC register sets OFF/ON to the circuit.
The circuit to emphasis the high-frequency component of transmit audio signal to improve
S/N ratio of the modulation signal.
The High-pass filter to eliminate the low-frequency component less than 250Hz for
transmit and receive audio signal.
This circuit is turned on and off by HPFSW register.
Scramble/De-scramble circuit to inverse transmit and receive audio spectrum by 2.844 to
3.491kHz carrier signal.
EM and PCONT register can set scramble/de-scramble or emphasis circuit. Both circuits
can not be used simultaneously.
The circuit to add audio signal and external tone signal.
TXINSW,TXSW2,1,0 registers are used to set this block.
An amplitude limiting circuit to suppress the frequency deviation of the modulation signal.
The limitation level can be adjusted by internal DAC.
Digitally controlled amplifier (volume) for the limitation level of the limiter circuit which is
adjustable in 0.5dB steps over a -17.6dB to -2.1dB range by setting LIMLV3 toLIMLV0
register.
Digitally controlled amplifier (volume) for MOD output level which is adjustable in 0.2dB
steps over a –3.2dB to +3.0dB range by setting VR25 to VR20 register. VR25 is a
–6.4/0dB coarse bit.
The circuit to eliminate the high frequency component higher than 3kHz included in the
limiter output signal or the MSK modulator signal. The cut-off frequency can be selected
by SPL register.
The smoothing filter to eliminate the high frequency and clock component caused in SCF
circuits.
The operational amplifier for receives audio gain adjustment and for the filter to eliminate
aliasing noise by the SCF in the following stage. Please select an external resistor and
capacitor to set the gain less than 20dB and the cut-off frequency to about 40kHz.
Digitally controlled amplifier (volume) for receive audio signal level which is adjustable in
0.5dB steps over a –4.0dB to +3.5dB range by setting VR33 to VR30 register.
The Low-pass filter to eliminate the high frequency component higher than 3kHz for
receive audio signal.
The circuit to de-emphasis the emphasized signal by pre-emphasis circuit.
The circuit to expand the receive audio signal level to double in dB scale compressed by
compressor
Standard cross-point is –10dBx. TC register sets OFF/ON to the circuit.
Digitally controlled amplifier (volume) for Expander output level which is adjustable in
0.25dB, steps over a –18dB and –4.5dB to +4.5dB range by setting VR42 to VR40
register.
The operational amplifier for transmit audio gain adjustment and for the filter to eliminate
aliasing noise by the SCF(switched capacitor filter) in the following stage. Please select
an external resistor and capacitor to set the gain less than 30dB and the cut-off frequency
to about 10kHz.
MS1289-E-04
2013/12
-4-
[AK2346A]
Block
MSK BPF
MSK Demodulator
MSK Modulator
AGND
OSC
DIV
Control
Register
Description
The Band-pass filter to eliminate the low and high frequency component for received MSK
signal.
The circuit to reproduce the 1200/2400bit/s receive clock and data from MSK signal at
RXIN pin.
The circuit to generate a MSK signal according to the received digital data from
MSKDATA pin.
The circuit to generate the reference voltage (1/2VDD) for internal analog signal.
The circuit to oscillate the 14.7456MHz reference clock with an external crystal oscillator
and resistor and capacitors.
The circuit to generate 1/2,1/3 or 1/4 frequency-divided output When a signal whose
frequency is twice, three times, or four times higher than 3.6864MHz is input from the
outside, this circuit divides the signal frequency by two, three, or four.
MCKSL[1:0] register is used to set this block.
The control register controls the status of internal switches and digitally controlled
amplifiers of IC by serial data that consists of 4 address bits and 8 data bits.
The data buffer stores 8 bits of the MSK received data to smooth the signal interface with
microprocessor.
At the start up, RSTN-pin is used for system reset. SRST register is used for software
reset. (Refer to the control register map)
6. Pin/Function
Package
Signal
1
MSKCLK
DO
Conditions
at power
down
H
2
DIO
DB
Z
3
SCLK
DI
Z
Clock input and output pin for MSK signal.
Serial data input and output pin.
Input for register setting data and output for MSK receive data.
Clock input pin for serial data I/O.
4
DIR
DI
Z
Serial data I/O control pin.
5
XOUT
DO
*2)
Pin No
Name
6
XIN
7
Type
DI
*2)
DVDD
PWR
-
8
VSS1
PWR
-
9
AVDD
PWR
-
Function
Crystal oscillator connecting input pin.
Crystal oscillator connecting input and output pin.
To connect a 14.7456MHz crystal oscillator between this pin
and XOUT pin generates the reference clock internally.
In case of externally supplied clock operation, connect to this
pin. For more information, please refer to external application
circuits.
Digital VDD power supply pin.
Normally connect to 2.6V to 5.5V power-supply. Also this pin
must be decoupled to VSS pin by 0.1uF capacitor mounted
close to the device pins.
VSS power supply pin.
Normally supply 0V to this pin.
Analog VDD power supply pin.
Normally connect to 2.6V to 5.5V power-supply. Also this pin
must be decoupled to VSS pin by 0.1uF capacitor mounted
close to the device pins.
Applied voltage must be DVDD ≤ AVDD
MS1289-E-04
2013/12
-5-
[AK2346A]
Package
Pin No
Signal
Name
Type
Conditions
at power
down
10
RXIN
AI
Z
11
RXINO
AO
Z
12
FILTERO
AO
Z
13
RXOUT
AO
Z
14
AGNDIN
AI
*1)
15
AGND
AO
*1)
16
EXTIN1
AI
Z
17
EXTINO
AO
Z
18
VSS2
PWR
-
19
TXIN
AI
Z
20
TXINO
AO
Z
21
EXTIN2
AI
Z
22
MOD
AO
Z
23
RSTN
DI
Z
Function
Demodulated audio signal input pin.
This is the inverting input of RXA1. It composes a pre-filter with
external resistor and capacitor.
RXA1 feedback output pin.
RXLPF circuit and TX/RX_HPF circuit output pin. LPF output
pin. This is a monitor pin for tone signal. 57.6kHz
sampling-clock is included, so please eliminate this signal
component by LPF externally.
Receive audio signal output pin.
Analog ground input pin.
Connect the capacitor to stabilize the analog ground level.
Analog ground output pin.
Connect the capacitor to stabilize the analog ground level.
TXA2 feedback input pin.
This is the inverting input pin for TXA2. It composes a
microphone amplifier with an external resistor and capacitor.
TXA2 feedback output pin.
VSS power supply pin.
Normally supply 0V to this pin.
Transmit audio signal input pin.
This is the inverting input pin for TXA1. It composes a
microphone amplifier with an external resistor and capacitor.
TXA1 feedback output pin.
External input pin.
This pin is available for external tone signal.
The modulated transmit signal output pin.
Note
Reset pin.
MSK signal MSK signal transmitted and received data input and
output pin.
In transmission, AK2346A reads data synchronized with the
rising edge of MSKCLK.
This pin outputs 2 kinds of information according to the
setting of FSL register.
This pin puts out two types of signal that depends on the status
of register named FSL.
MSKDATA
DB
Z
In case FSL equal “1”, it is received flag mode (RDF). So the pin
puts out low level after 8 bits of MSK receive signal have been
written to the internal register.
In case FSL equal “0”, it is frame detection mode (FD). So the
low pulse is put out after a frame pattern is detected.
When MSKSW[1:0] register is set to “1/0”, RDATA signal is put
out.
A: Analog, D: Digital, PWR: Power, I: Input, O: Output, B: Bidirectional, Z: High-Z, L: Low
*1)
*2)
AGND level
When XIN pin is set to low level, XOUT pin goes to high level.
24
MS1289-E-04
2013/12
-6-
[AK2346A]
RXOUT
AGNDIN
AGND
EXTIN1
EXTINO
VSS2
• Pin Assignment
18 17 16 15 14 13
11
RXINO
EXTIN2
21
10
RXIN
MOD
22
9
AVDD
RSTN
23
8
VSS1
MSKDATA
24
7
DVDD
1
2
3
4
5
6
XIN
20
XOUT
TXINO
DIR
FILTERO
SCLK
12
DIO
19
MSKCLK
TXIN
MS1289-E-04
2013/12
-7-
[AK2346A]
7. Absolute Maximum Ratings
Parameter
Ground Level
Symbol
AVDD
DVDD
VSS
Input Voltage
VIN
Power Supply Voltage
Input Current
IIN
(Except power supply pin)
Storage Temperature
Tstg
Note : All voltages with respect to the VSS pin.
Min.
-0.3
-0.3
0
-0.3
-0.3
Max.
6.5
6.5
0
AVDD+0.3
DVDD+0.3
Units
V
V
V
V
V
-10
+10
mA
-55
130
°C
Caution : Exceeding these maximum ratings can result in damage to the device.
Normal operation cannot be guaranteed under this extreme.
8. Recommended Operating Conditions
Parameter
Operating Temperature
Symbol
Condition
Ta
AVDD
Power Supply Voltage
DVDD
DVDD≤AVDD
AGND
Analog Reference Voltage
RL1
MOD, RXOUT, FILTEROO
Output Load Resistance
RL2
TXINO, RXINO, RXOUT
CL1
MOD, RXOUT, FILTEROO
Output Load Capacitance
CL2
TXINO, RXINO, RXOUT
Note : All voltages with respect to the VSS pin.
Min.
-40
2.6
2.6
Typ.
3.0
3.0
1/2AVDD
Max.
85
5.5
5.5
10
30
Units
°C
V
V
V
kΩ
50
15
pF
Max.
Units
9. Digital DC Characteristics
Parameter
Symbol
Condition
Min.
High level input voltage
VIH
DIO,SCLK,DIR,MSKDATA,
RSTN
0.8VDD
Low level input voltage
VIL
DIO,SCLK,DIR,MSKDATA,
RSTN
High level input current
IIH
Low level input current
IIL
High level output voltage
VOH
Low level output voltage
VOL
VIH=DVDD
DIO,SCLK,DIR,MSKDATA,
RSTN
VIL=0V
DIO,SCLK,DIR,MSKDATA,
RSTN
IOH=+0.2mA
MSKCLK,MSKDATA,DIO
IOL=-0.4mA
MSKCLK,MSKDATA,DIO
MS1289-E-04
Typ.
V
0.2VDD
V
10
µA
-10
µA
VDD-0.4
VDD
V
0.0
0.4
V
2013/12
-8-
[AK2346A]
10. Clock Input Characteristics
Parameter
Clock frequency
Symbol
Condition
MCK0
XIN,XOUT
MCK1
XIN
High level input voltage VMCK1_IH
XIN
Low level input voltage
VMCK1_IL
XIN
Input amplitude
VMCK2
XIN
Min.
Typ.
Max.
14.7456
3.6864
7.3728
11.0592
14.7456
Unit
Remarks
MHz
MHz
*1), *2)
V
*1)
0.4
V
*1)
1.0
VPP
*2)
1.5
0.2
*1) These values apply when the clock signal is input on the XIN pin directly. For details, refer to 6),
"Oscillator circuit", in "Recommended External Circuit Examples".
*2) These values apply when the clock signal is input on the XIN pin via DC cut. For details, refer
to 6), "Oscillator circuit", in "Recommended External Circuit Examples".
11. System Reset
Parameter
Symbol Condition
Hardware reset signal
tRSTN RSTN pin
input width
Typ.
Max.
1
SRST
register
Software reset
*1)
Min.
Unit
Remarks
µs
*1)
*2)
After power-on, be sure to perform a hardware reset operation (register initialization). The
system is reset by a low pulse input of 1µs (min.) and enters the normal operation state. At this
moment, the digital (DI) pins are set as follows: RSTN pin to high, MSKDATA pin to low, SCLK
pin to high, DIR pin to low.
tRSTN
VIH
RSTN
VIL
*2)
When data 0xAA:10101010 is written to the SRST[7:0] register, software reset is performed.
This setting initializes the registers and the operation mode is set to mode 0 (power down).
After software reset is completed, this register comes to “0”.
MS1289-E-04
2013/12
-9-
[AK2346A]
12. Power Consumption
Parameter
Symbol
IDD0
IDD1
Consumption
Current
IDD2
IDD3
IDD4
Condition
Mode 0
OSC:OFF, Audio: OFF, Modem:OFF
Mode 1
OSC:ON , Audio: OFF, Modem:OFF
Mode 2
OSC:ON , Audio: ON , Modem:OFF
Mode 3
OSC:ON , Audio: OFF, Modem:ON
Mode 4
OSC:ON , Audio: ON , Modem:ON
MS1289-E-04
Min.
Typ.
Max.
0.1
0.3
0.8
1.5
5.4
8.7
1.8
3.2
6.0
9.5
Units
mA
2013/12
- 10 -
[AK2346A]
13. Analog Characteristics
For the following conditions unless otherwise specified: f=1kHz, Emphasis: on, Compandor: on,
Scrambler: off, VR1=VR2=VR3=VR4=0dB with the external circuit shown in example page.33 to 35.
“dBx” is standardized unit for 2.6V to 5.5V operation, 0dBx=-5+20log(VDD/2)dBm, 0dBm=0.775Vrms.
1) TX Audio System
Parameter
Condition
Standard Input Level
@TXINO
Absolute Gain
Limit Level
Compressor
Linearity
TXINO to MOD
EXTLIMIN to MOD
TXINO to MOD
TXINO=-44dBx
TXINO=-50dBx
Relative value to 0dB for MOD
level of -10dBx TXINO.
TXINO to MOD
TXINO=-10dBx
30kHz Low-pass filtering
TXINO to MOD
C-Message filtering
TXINO to MOD
-18.0 dB to 4.5dB, 1.5dB/step
TXINO to MOD
-3.2dB to +3.0dB, 0.2dB/step
TXINO to MOD
When -6.4dB setting
Relative error for -6.4/0dB
MOD
-10～+5.5dB, 0.5dB/step
Compressor
Distortion
Noise Level with no
signal input
VR1
Attenuation Error
VR2 ATT Error
(VR24,23,22,21,20)
VR2 ATT Error
(VR25=0)
Limiter DAC Error
(VR25=0)
2) RX Audio System
Parameter
Standard Input Level
Absolute Gain
Condition
Min.
Typ.
Max.
Units
-1.5
-8.6
-10
0
-7.6
+1.5
-6.6
dBx
dB
dBx
-20.0
-24.0
-17.0
-20.0
-14.0
-16.0
dB
-35
dB
-36.5
dBm
-1.5
+1.5
dB
-0.2
+0.2
dB
-6.0
dB
+0.5
dB
-6.8
-6.4
-0.5
Min.
Typ.
Max.
Units
RXINO to FILTERO
-1.5
-10
0
+1.5
dBx
dB
RXINO to RXOUT
-1.5
0
+1.5
dB
-33.0
-45.0
-30.0
-40.0
-27.0
-35.0
dB
-35
dB
-70
dBm
-0.5
+0.5
dB
-0.25
+0.25
dB
-16
dB
@RXINO
Expander
Linearity
RXINO to RXOUT
RXINO=-25dBx
RXINO=-30dBx
Relative value to 0dB for RXOUT
level of -10dBx RXINO
Expander
RXINO to RXOUT
Distortion
RXINO=-5dBx
30kHz Low-pass filtering
Noise Level with no RXINO to RXOUT
signal input
C-Message Filtering
VR3
RXIN0 to RXOUT
-4.0dB to +3.5dB, 0.5dB/step
Attenuation Error
VR4
RXIN0 to RXOUT
-4.5 to +4.5dB, 0.25dB/step
Attenuation Error
RXIN0 to RXOUT
VR4 ATT Error
When -18dB setting
(VR42,41,40=0,0,0)
Relative error for -18/0dB
MS1289-E-04
-20
-18
Notes
Notes
2013/12
- 11 -
[AK2346A]
3) Audio Filter Characteristics
3.1) Emphasis: off, Compandor: off, Scrambler: off
(Design target values)
Parameter
Condition
Min.
Typ.
Max.
TX overall
250Hz
-50
-38
TXINO to MOD
characteristics
300Hz to 2.0kHz
-1.0
+1.0
2.5kHz
-1.5
+1.0
Relative value
3.0kHz
-4.0
-1.0
to gain at
6.0kHz
-38
-28
1kHz
300Hz to 2.5kHz
-1.0
+1.0
3.0kHz
-1.5
+1.0
6.0kHz
-43
-22
RX overall
250Hz
-49
-38
RXINO to RXOUT
characteristics
300Hz
-1.5
+1.0
-1.0
+1.0
350Hz to 3.0kHz
Relative value
6.0kHz
-38
-28
to gain at 1kHz
3.2) Emphasis: on, Compandor: off, Scrambler: off
Parameter
Condition
TX overall
250Hz
TXINO to MOD
characteristics
300Hz
2.5kHz
3.0kHz
Relative value
6.0kHz
to gain at
300Hz
1kHz
2.5kHz
3.0kHz
6.0kHz
RX overall
250Hz
RXINO to RXOUT
characteristics
300Hz
3.0kHz
Relative value
6.0kHz
to gain at 1kHz
MS1289-E-04
Min.
Typ.
-57
-12.5
+6.0
+4.5
-29
-12.5
+6.0
+7.0
-34
-38
+8.5
-11.5
-52
Max.
-40
-9.5
+9.0
+8.5
-18
-9.5
+9.0
+10.5
-12
-26
+11.5
-8.5
-40
Units
dB
dB
dB
Notes
SPL=0
fc=2.55K
SPL=1
fc=3.0K
dB
Units
dB
dB
dB
Notes
SPL=0
fc=2.55K
SPL=1
fc=3.0K
dB
2013/12
- 12 -
[AK2346A]
• Audio path frequency response (Emphasis:off)
20
10
GAIN(dB)
0
-10
SPL=0
-20
SPL=1
-30
-40
-50
-60
1.E+02
1.E+03
1.E+04
FREQUENCY(Hz)
Figure 1:
TX overall response without pre-emphasis.
20
10
GAIN(dB)
0
-10
-20
-30
-40
-50
-60
1.E+02
1.E+03
1.E+04
FREQUENCY(Hz)
Figure 2:
RX overall response without de-emphasis.
MS1289-E-04
2013/12
- 13 -
[AK2346A]
• Audio path frequency response (Emphasis:on)
20
10
GAIN(dB)
0
-10
SPL=0
-20
SPL=1
-30
-40
-50
-60
1.E+02
1.E+03
1.E+04
FREQUENCY(Hz)
Figure 3:
TX overall response with pre-emphasis.
20
10
GAIN(dB)
0
-10
-20
-30
-40
-50
-60
1.E+02
1.E+03
1.E+04
FREQUENCY(Hz)
Figure 4:
RX overall response with de-emphasis.
MS1289-E-04
2013/12
- 14 -
[AK2346A]
4) Scrambler Characteristics (Scrambler: on, Emphasis: off, Compandor: off)
Parameter
Condition
Min.
Typ.
Max.
Carrier Frequency
3.388
Modulated Output
Level
High Frequency
Rejection Level
Carrier Signal
Leakage Level
TXINO to MOD,
RXINO to RXOUT
Input level
1.0kHz -10dBx
Measuring-freq. 2.388kHz
-12
-10
TXINO to MOD,
RXINO to RXOUT
Input level
1.0kHz -10dBx
Measuring-freq. 4.388kHz
TXINO to MOD,
RXINO to RXOUT
Input level
No signal
Measuring-freq. 3.388kHz
Original Signal
Leakage Level
TXINO to MOD,
RXINO to RXOUT
Input level
1.0kHz -10dBx
Measuring-freq. 1.0kHz
5) MSK Modem Characteristics
Parameter
TX Signal Level
@MOD
TX Signal Distortion
RX Signal Level
Condition
1.2kHz signal out
@MOD
1.2kHz signal out
@RXINO
1.2kHz signal out
-8
dBx
-50
dBx
-50
dBx
-50
dBx
Typ.
Max.
Units
-12
-11
-10
dBx
-32
dB
-1
dBx
-11
Notes
kHz
Min.
-17
MS1289-E-04
Units
Notes
2013/12
- 15 -
[AK2346A]
14. Level Diagram
1) TX audio system : TXRX=0
MSK
Modulator
f=1kHz
TXA1
TXIN
EXTIN2
TXINO
VR1
+4.5
dB
0
-18
G = 30dB
Compressor
Pre-emphasis
Crosspoint
-10dBx
0dB
TXHPF
0dB
Splatter
+VR2
Limitter
SMF
+3.0
dB
0
-9.2
-7.6dBx
MOD
0dB
Scrm
/Descrm
0dB
dBx
10
0
0
-5
-5.5
-7.0
-10dBx (Audio)
-10
-10
-10
-11
-11dBx (MSK)
-19.2
-20
-27
-27dBx
-30
-30dBx
-18
-30
-40
-44
-50
-50
-60
-70
-80
-90
2) RX audio system : TXRX=1
FILTERO
f=1kHz
RXIN
RXINO
VR3
RXA1
G = 20dB
0
+3.5
dB
-4.0
RXLPF
RXHPF
0dB
+5dB
De-emphasis
Expander
-5dB
Crosspoint
-10dBx
Scrm
/Descrm
VR4
SMF
+4.5
dB
0
-18.0
G = 0dB
RXOUT
-5dB
dBx
10
0
0
-5
-6.5
-20
-25
-10
-14
-10
-5.5
-10dBx (Typ.)
-20
-25
-28
-25
-30
-40
0dBx (Max.)
-5
-10
-30
-40
-40dBx
-45
-50
-50dBx
-50
-60
“dBx” is standardized unit for 2.6V to 5.5V operation, 0dBx=-5+20log(VDD/2)dBm, 0dBm=0.775Vrms.
MS1289-E-04
2013/12
- 16 -
[AK2346A]
15. Serial Interface Configuration
1) Register Configuration
Address
Function
Data
D7
D6
D5
D4
D3
D2
D1
D0
BS3
BS2
BS1
TXRX
TXINSW
TXSW2
TXSW1
TXSW0
FILSW1
FILSW0
RXSW
LIMSW
TC
EM
PCONT
SPL
0
TXA2PW
MSKSW1
MSKSW0
MSKSL
FCLN
FSL
HPFSW
0
0
0
0
VR13
VR12
VR11
VR10
0
0
VR25
VR24
VR23
VR22
VR21
VR20
0
0
0
0
VR33
VR32
VR31
VR30
0
0
VR45
VR44
VR43
VR42
VR41
VR40
A3
A2
A1
A0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
Software Reset
SRST[7:0]
1
1
0
1
Test register 1
Test register 1 for LSI test operation (not accessible)
1
1
1
0
Test register 2
Test register 2 for LSI test operation (not accessible)
1
1
1
1
Test register 3
Test register 3 for LSI test operation (not accessible)
Control
register 1
Control
register 2
Control
register 3
Volume
register 1
Volume
register 2
Volume
register 3
Volume
register 4
Modem
register 1
Modem
register 2
Volume
register 5
Control
register 4
Control
register 5
Lower 8 bit of Modem Flame pattern
Upper 8 bit of Modem Flame pattern
0
0
0
LIMLV4
LIMLV3
LIMLV2
LIMLV1
LIMLV0
0
0
0
0
SCR3
SCR2
SCR1
SCR0
0
0
0
0
0
MCKCNT
MCKSL1
MCKSL0
Modem
register 3
Modem Receive data
MS1289-E-04
2013/12
- 17 -
[AK2346A]
2) Register Map
2.1) Control Register 1
Address
A3
A2
A1
A0
0
0
0
0
Initial Value
Data
D7
D6
D5
D4
D3
D2
D1
D0
BS3
BS2
BS1
TXRX
TXINSW
TXSW2
TXSW1
TXSW0
0
0
0
1
1
1
1
1
2.1.1) Operation mode setting
BS3
BS2
BS1
Mode
OSC,AGND
TX, RX, Audio
Modem
0
0
0
Mode0(power OFF)
OFF
OFF
OFF
0
0
1
Mode1(Standby)
ON
OFF
OFF
ON
ON
OFF
Mode2
0
1
1
ON
OFF
ON
Mode3
1
0
0
ON
ON
ON
Mode4
Note : Do no set the combination of the code which is not defined in the table given above.
0
1
0
2.1.2) TX, RX Setting
Data
Function
TXRX
TX, RX Switch
TXINSW
TX Signal
Operation
Notes
0
1
TX Operation
Note 1
RX Operation
Note 2
Note 3
TXA1+TXA2 Operation
TXA1 Operation
Note 4
2.1.3) TX audio path setting
EXTINO Signal
EXTIN2 Signal
1
1
1
OFF
OFF
OFF
OFF
1
1
0
ON
OFF
OFF
OFF
1
0
1
OFF
ON
OFF
OFF
1
0
0
ON
OFF
ON
OFF
0
1
1
ON
OFF
OFF
ON
0
1
0
OFF
OFF
ON
OFF
0
0
1
OFF
OFF
OFF
ON
Note : Do no set the combination of the code which is not defined in the table given above.
TXSW2
TXSW1
TXSW0
TX Audio
Modem
Note 1: TXIN to RXOUT path is available by setting TXRX=0 and RXSW=1 in register.
However, Scrambler/Descrambler circuit does not work properly on this setting, so please set
PCONT=1 (disable). To set RXSW=0 makes RXOUT pin mute in operation.
Note 2: RXIN to MOD path is available by setting
TXRX=1 and TXSW2/TXSW1/TXSW0=1/1/0 in register.
However, Scrambler/Descrambler circuit does not work properly on this setting, so please set
PCONT=1 (disable). To set TXSW2/TXSW1/TXSW0=1/1/1 makes MOD pin mute in operation.
Note 3: Please set a gain level properly in each circuit block according to level diagram in page 16.
Note 4: In case of TXA1+TXA2 Operation (TXINSW=0),
please set the register to other than TXSW2/TXSW1/TXSW0=1/0/0 nor
TXSW2/TXSW1/TXSW0=0/1/0
MS1289-E-04
2013/12
- 18 -
[AK2346A]
2.2) Control Register 2
Address
A3
A2
A1
A0
0
0
0
1
Initial Value
FILSW1
Data
D7
D6
D5
D4
FILSW1
FILSW0
RXSW
1
1
1
LIMSW
1
D3
D2
D1
D0
TC
EM
PCONT
SPL
1
1
1
1
Notes
Operation
FILSW0
FILTERO pin is mute
RXLPF circuit signal to FILTERO pin
0
1
TX/RX_HPF circuit signal to FILTERO pin
0
0
Note : Do no set the combination of the code which is not defined in the table given above.
1
1
Data
RXSW
RX Audio
LIMSW
Limiter
Compressor/
Expander
TC
SPL
Operation
Function
Splatter
cut-off frequency
Notes
0
1
mute
OFF (bypass)
Normal operation
ON (active)
OFF (bypass)
ON (active)
2.55kHz
3.0kHz
Note 5
Note 5: FILTERO pin cannot be controlled by setting RXSW=0.
Notes
Operation
EM
PCONT
1
1
Emphasis : ON (enable)
Scrambler : OFF(disable)
0
1
Emphasis : OFF(disable)
Scrambler : OFF(disable)
0
0
Emphasis : OFF(disable)
Scrambler : ON (enable)
Note : Do no set the combination of the code which is not defined in the table given above.
2.3) Control Register 3
Address
A3
A2
A1
A0
0
0
1
0
Initial Value
Data
D7
0
0
D6
D5
D4
D3
D2
D1
D0
TXA2PW
MSKSW1
MSKSW0
MSKSL
FCLN
FSL
HPFSW
0
1
1
1
1
1
1
Operation
MSKSW1
MSKSW0
1
1
0
1
TX clock (TCLK) is out put TX data (MSKDATA) can be input
from MSKCLK pin.
from MSKDATA pin.
1
0
Rx clock (RCLK) is out put
from MSKCLK pin.
RX data (RDATA) is output from
MSKDATA pin.
High output
RDF/FD signal is output from
MSKDATA pin.
Select MSK RX flag (RDF) and
input clock to SCLK pin, then Rx
data is output from DIO pin.
0
0
MSKCLK pin
MSKDATA pin
High output
High-Z
Input High or Low
MS1289-E-04
Notes
MSK
transmission
:OFF
MSK
transmission
:ON
2013/12
- 19 -
[AK2346A]
Operation
Data
Function
TXA2PW
TXA2 power down
control
MSKSL
Modem data rate
FCLN
FSL
1
TXA2 power down
TXA2 operation
2400bit/s
1200bit/s
ON (enable)
OFF (disable)
FD enable
RDF enable
OFF (bypass)
ON (active)
Modem flame detect
RDF/FD Switch
HPFSW
TX/RX_HPF
2.4) Volume Register 1
Address
A3
A2
A1
A0
0
0
1
1
Initial Value
VR13
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Notes
0
However in case of
mode0, TXA2 comes
to power down.
Data
D7
0
0
VR12
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D6
0
0
D5
0
0
VR11
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
MS1289-E-04
D4
0
0
D3
D2
D1
D0
VR13
VR12
VR11
VR10
1
1
0
0
VR10
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
VR1 gain(dB)
-18.0
-16.5
-15.0
-13.5
-12.0
-10.5
-9.0
-7.5
-6.0
-4.5
-3.0
-1.5
0.0
+1.5
+3.0
+4.5
2013/12
- 20 -
[AK2346A]
2.5) Volume Register 2
Address
A3
A2
A1
A0
0
1
0
0
Initial Value
Data
D7
0
0
D6
0
0
D5
D4
D3
D2
D1
D0
VR25
VR24
VR23
VR22
VR21
VR20
1
1
0
0
0
0
VR25
VR2 gain(dB)
-6.4
0.0
0
1
VR24
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VR23
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
VR22
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
VR21
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
MS1289-E-04
VR20
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
VR2 gain(dB)
-3.2
-3.0
-2.8
-2.6
-2.4
-2.2
-2.0
-1.8
-1.6
-1.4
-1.2
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
+0.2
+0.4
+0.6
+0.8
+1.0
+1.2
+1.4
+1.6
+1.8
+2.0
+2.2
+2.4
+2.6
+2.8
+3.0
2013/12
- 21 -
[AK2346A]
2.6) Volume Register 3
Address
A3
A2
A1
A0
0
1
0
1
Initial Value
Data
D7
0
0
D6
0
0
D5
0
0
D4
0
0
D3
D2
D1
D0
VR33
VR32
VR31
VR30
1
0
0
0
VR33
VR32
VR31
VR30
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
MS1289-E-04
VR3 gain (dB)
-4.0
-3.5
-3.0
-2.5
-2.0
-1.5
-1.0
-0.5
0.0
+0.5
+1.0
+1.5
+2.0
+2.5
+3.0
+3.5
2013/12
- 22 -
[AK2346A]
2.7) Volume Register 4
Address
Data
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
0
0
0
VR45
VR44
VR43
VR42
VR41
VR40
0
0
0
1
0
0
1
1
Initial Value
VR45
VR44
VR43
VR42
VR41
VR40
VR4 gain (dB)
0
0
0
0
0
0
-18.0
0
0
0
0
0
1
-4.50
0
0
0
0
1
0
-4.25
0
0
0
0
1
1
-4.00
0
0
0
1
0
0
-3.75
0
0
0
1
0
1
-3.50
0
0
0
1
1
0
-3.25
0
0
0
1
1
1
-3.00
0
0
1
0
0
0
-2.75
0
0
1
0
0
1
-2.50
0
0
1
0
1
0
-2.25
0
0
1
0
1
1
-2.00
0
0
1
1
0
0
-1.75
0
0
1
1
0
1
-1.50
0
0
1
1
1
0
-1.25
0
0
1
1
1
1
-1.00
0
1
0
0
0
0
-0.75
0
1
0
0
0
1
-0.50
0
1
0
0
1
0
-0.25
0
1
0
0
1
1
0.00
0
1
0
1
0
0
+0.25
0
1
0
1
0
1
+0.50
0
1
0
1
1
0
+0.75
0
1
0
1
1
1
+1.00
0
1
1
0
0
0
+1.25
0
1
1
0
0
1
+1.50
0
1
1
0
1
0
+1.75
0
1
1
0
1
1
+2.00
0
1
1
1
0
0
+2.25
0
1
1
1
0
1
+2.50
0
1
1
1
1
0
+2.75
0
1
1
1
1
1
+3.00
1
0
0
0
0
0
+3.25
1
0
0
0
0
1
+3.50
1
0
0
0
1
0
+3.75
1
0
0
0
1
1
+4.00
1
0
0
1
0
0
+4.25
1
0
0
1
0
1
+4.50
Note : Do no set the combination of the code which is not defined in the table given above.
MS1289-E-04
2013/12
- 23 -
[AK2346A]
2.8) Modem Register
Address
A3
A2
A1
A0
0
1
1
1
Initial Value
1
0
0
0
Initial Value
2.9) Volume Register 5
Address
A3
A2
A1
A0
1
0
0
1
Initial Value
LIMLV4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
LIMLV3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Data
D7
D6
D5
D4
D3
D2
D1
D0
F07
F06
F05
F04
F03
F02
F01
F00
1
0
1
0
1
0
0
0
F15
F14
F13
F12
F11
F10
F09
F08
0
0
0
1
1
0
1
1
D4
D3
D2
D1
D0
LIMLV4
LIMLV3
LIMLV2
LIMLV1
LIMLV0
0
1
0
1
1
Data
D7
0
0
D6
0
0
D5
0
0
LIMLV2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
LIMLV1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
MS1289-E-04
LIMLV0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
gain(dB)
5.5 (-2.1)
5.0 (-2.6)
4.5 (-3.1)
4.0 (-3.6)
3.5 (-4.1)
3.0 (-4.6)
2.5 (-5.1)
2.0 (-5.6)
1.5 (-6.1)
1.0 (-6.6)
0.5 (-7.1)
0 (-7.6dBx)
-0.5 (-8.1)
-1.0 (-8.6)
-1.5 (-9.1)
-2.0 (-9.6)
-2.5 (-10.1)
-3.0 (-10.6)
-3.5 (-11.1)
-4.0 (-11.6)
-4.5 (-12.1)
-5.0 (-12.6)
-5.5 (-13.1)
-6.0 (-13.6)
-6.5 (-14.1)
-7.0 (-14.6)
-7.5 (-15.1)
-8.0 (-15.6)
-8.5 (-16.1)
-9.0 (-16.6)
-9.5 (-17.1)
-10.0 (-17.6)
2013/12
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[AK2346A]
2.10) Control Register 4
Address
A3
A2
A1
A0
1
0
1
0
Initial Value
Data
D7
0
0
D6
0
0
D5
0
0
D4
0
0
D3
D2
D1
D0
SCR3
SCR2
SCR1
SCR0
1
1
0
1
SCR3
SCR2
SCR1
SCR0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2.11) Control Register 5
Address
A3
A2
A1
A0
1
0
1
1
Initial Value
Data
Function
Carrier Frequency
(kHz)
2.844
2.880
2.916
2.954
2.992
3.032
3.072
3.114
3.156
3.200
3.245
3.291
3.339
3.388
3.439
3.491
Data
D7
0
0
D6
0
0
D5
0
0
D4
0
0
D3
0
0
D2
D1
D0
MCKCNT
MCKSL1
MCKSL0
1
1
1
Operation
0
1
a crystal oscillator
(14.7456MHz)
Notes
MCKCNT
External input
switch
MCKSL1
MCKSL0
Operation
Notes
0
0
Master Clock: 3.6864MHz
External input only
1
0
Master Clock: 7.3728MHz
External input only
0
1
Master Clock: 11.0592MHz
External input only
External input
1
1
Master Clock: 14.7456MHz
Note : Set MSKSL[1:0] register when Mode0 or Mode1.
MS1289-E-04
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[AK2346A]
2.12) Software Reset Register
Address
A3
A2
A1
A0
1
1
0
0
Initial Value
Data
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
SRST[7:0]
0
0
0
0
0
When data 0xAA:10101010 is written to the SRST[7:0] register, software reset is performed.
Refer to “System Reset” for further information.
2.13) Modem receive data register
Address
A3
A2
A1
A0
D7
RD7
－
－
－
－
Data
Function
RD7 to 0
MSKSL=0
MSKSL=1
Data
D6
D5
D4
D3
D2
D1
D0
RD6
RD5
RD4
RD3
RD2
RD1
RD0
MSK receive data
0
2.4kHz
1.8kHz
1
1.2kHz
1.2kHz
MS1289-E-04
Notes
Data received
first is RD7.
2013/12
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[AK2346A]
16. Digital AC Timing
1) Serial Interface Timing
Parameter
Symbol
Min.
ta
tb
tc
td
te
tf
tg
th
ti
500
500
100
100
100
100
100
Clock pulse width 1
Clock pulse width 2
DIO Set up time
DIO Hold time
DIR Set up time
DIR Hold time
DIR Falling to SCLK Falling time
SCLK Input rising time
SCLK Input falling time
Typ.
Max.
Units
ns
ns
ns
100
100
ns
tb
ta
SCLK
tc
td
A3
DI/O
A2
A0
A1
D1
D0
tf
te
DIR
tg
th
ti
0.8VDD
0.2VDD
SCLK waveform
MS1289-E-04
2013/12
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[AK2346A]
2) MSK Modulator Timing
Parameter
MSKSW1 Falling to MSKCLK Rising
MSKSL=”0”
MSKSL=”1”
MSKCLK Period
MSKSL=”0”
MSKSL=”1”
MSKDATA Set up time
MSKDATA Hold time
MSKDATA Hold time2
Symbol
Min.
Typ.
Max.
Units
T1
208.3
416.7
us
T2
416.7
833.3
us
TS
TH
TH2
1
1
2
us
MSKCLK
MSKSW0
Register data
T1
T2
MSKSW1
TH2
TS
TH
MSKDATA
MOD
(MSKSL=”0”)
(MSKSL=”1”)
Note: The timing of setting the internal registers TXSW1 and TXSW2 is synchronized with the falling
edge of DIR pin.
3) MSK Demodulator Timing
Parameter
RCLK Period and FD pulse width
MSKSL=”0”
MSKSL=”1”
RDF Falling to SCLK Falling time
SCLK Rising to RDF Falling time
Symbol
Min.
T
tj
tk
MS1289-E-04
Typ.
416.7
833.3
100
600
Max.
Units
us
ns
2013/12
- 28 -
[AK2346A]
DIR
tj
SCLK
DIO
(Input)
MSKSW[1:0]=0/0
FSL=FCLN=0
FCLN=0
RXSW=0
FSL=1
DIO
(Output)
RD7~RD0
FSL
(Internal Register)
FCLN
FCLN=1 automatically
(Internal Register)
RCLK_n
(Internal Node)
T
RDATA_n
MD7
MD6 MD5
MD4
MD3 MD2
MD1
MD0
MD7
MD6
MD5
MD4
MD3 MD2
MD1
MD0 MD7
MD6
(Internal Node)
T
FD_n
(Internal Node)
tk
RDF_n
(Internal Node)
MS1289-E-04
2013/12
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[AK2346A]
17. MSK Modem Description
1)
MSK Modulator control flow
MSK data transmitter, Modulator interfaces with MSKCLK, MSKDATA and MOD pins and also
TXRX, TXSW2, TXSW1, TXSW0, MSKSW1 and MSKSW0 register as below.
TXRX=0
MSKSW[1:0]=0/1
TXSW[2:0]=1/0/1
: MSK data transmit start
MSK data are transmitted
synchronized to MSKCLK clock
: MSK data transmitting
N
Required bit
number completed
Y
Y
: MSK data transmit compete
MSKSW1=1
Waiting 2ms or more
: Switching to audio signal
TXSW[2:0]=”1/1/0”
(1)
(2)
(3)
(4)
Setting TXRX=0, MSKSW1=0, MSKSW0=1, TXSW2=1 and TXSW1=0, MSK data transmit is
provided.
A 1200/2400Hz clock is put out from MSKCLK pin. Synchronizing with the rising edge of
MSKCLK,
AK2346A reads the MSK transmit data from MSKDATA pin and puts out them to MOD pin.
After transmitting the necessary bit number, please set MSKSW1=1
Afterwards, before switching to audio signal mode, please wait for at least 2ms after setting
MSKSW1=1 to complete sending the MSK data final data bit transmit. Then set
TXSW[2:0]=”1/1/0”.
MS1289-E-04
2013/12
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[AK2346A]
2) MSK Demodulator control flow
2.1) When frame detection is used
MSK data receiver, Demodulator interfaces with RXIN, MSKDATA, SCLK, DIO and DIR pins and
also FSL, RXSW and FCLN registers as below.
N
FCLN=0
: Setting flame detect (FD) enable
FSL=0
: Setting for FD signal put out from
MSKDATA pin.
: Synchronized frame pattern
detect or not ?
MSKDATA “Low”
Y
: FD is disable automatically
FCLN=1 (automatically)
: Receive audio mute
RXSW=0
: Setting for received flag (RDF) signal
put out from MSKDATA pin.
FSL=1
N
MSKDATA “Low”
: 8 bit data received or not ?
Y
Reading receive data
N
Have all receive data
been read out?
: Having read 8bit data, MSKDATA pin
puts out high level.
Y
FCLN=0
: Waiting for the next synchronized
flame.
(1)
Set MSKSW1=0 and MSKSW0=0 for flame detect mode.
(2)
Setting FCLN=0 and FSL=0 and also SCLK pin sets high level and DIR pin sets low level,
MSKDATA pin puts out high level and wait for synchronized frame.
(3)
After a synchronized frame is detected, MSKDATA pin works as frame detect (FD) mode.
FD goes to low level during the period of time “T”, then FCLN is sets to “1” automatically.
MS1289-E-04
2013/12
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[AK2346A]
(4)
Monitoring low level of MSKDATA pin, set RXSW=0 for audio signal mute. Then set FSL=1 for
received flag (RDF), signal put out from MSKDATA pin.
(5)
After 8 bit received data (MD7…0) have been entered to the internal buffer from node RDATA,
MSKDATA pin goes to low level as RDF mode.
(6)
After CPU detects this low level at MSKDATA pin, please puts in 8 clock to SCLK pin. Then
modulated data (RD7…0) put out from DIO pin synchronized with falling edge of SCLK clock.
(7)
After 8 clock have been put into SCLK pin completely, MSKDATA pin goes to high level that
shows all modulated data coming from DIO pin.
(8)
By repeating the steps (5), (6), (7), the data come out from DIO pin continuously.
(9)
After the necessary data have been read, DIR pin sets to high level and FCLN=0. Then
internal node RCLK and RDATA are set to “1” for initializing and system waits for the next
synchronization frame data.
This frame detection circuit does not have reset function. In case of stopping the sequence
during the steps (1) to (8), please set again from the first step (1). Especially, when
MSKDATA pin goes out low level on frame detecting, FCLN register is sets to “1” automatically
as written in (2). If you set FCLN=0 during this operation, the date set “0” is ignored. So
please set the data again after MSKDATA pin puts out high level.
2.2) When frame detection is not used
(1) When frame detection is not used, set MSKSW1 to 1 and MSKSW0 to 0 to start MSK
reception.
(2) When the MSK signal is received on the RXIN pin, demodulated data is output successively
on the MSKDATA pin via MSK-BPF and MSK-Demodulator in synchronization with the falling
edge of the 1200Hz or 2400Hz clock signal output on the MSKCLK pin.
(3) Setting MSKSW1=1 and MSKSW0=1, reception mode comes to a stop. High level is output
on the MSKDATA pin and MSKSW0 comes to High-Z. At this time input High level or Low
level to MSKDATA pin.
MS1289-E-04
2013/12
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[AK2346A]
18. Recommended External Application Circuits
1) TXA1 Amplifier
This is an operational amplifier required for typical transmit microphone. The gain should be less
than 30dB. To eliminate high frequency noise component over than 100kHz from input signal,
please compose 1st or 2nd order anti-aliasing filter. The following simplified schematic shows an
example of 2nd order anti-aliasing filter that has 30dB gain and 10kHz cut-off frequency.
20
C1=0.47uF
TXINO
C2=33pF
R3
C2
19
_
+
TXIN
R1 C1
R2
C3=2200pF
R1=R2=10kΩ
C3
TXA1
R3=330kΩ
LSI
2) TXA2 amplifier
This amplifier is used for adjusting the gain of the external tone signal. The gain should be less
than 30dB. To eliminate high frequency noise component over than 100kHz from input signal,
please compose 1st or 2nd order anti-aliasing filter. The following simplified schematic shows an
example of 2nd order anti-aliasing filter that has 30dB gain and 10kHz cut-off frequency.
17
C1=0.47uF
EXTINO
C2=33pF
R3
C2
_
+
16
R1 C1
EXTIN1 R2
C3=2200pF
R1=R2=10kΩ
C3
TXA2
R3=330kΩ
AGND
21
C4
C4=0.047uF
EXTIN2
LSI
MS1289-E-04
2013/12
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[AK2346A]
3) RXA1 Amplifier
This is an operational amplifier suitable for receive gain adjuster and anti-aliasing filter to
eliminate high frequency noise component over 100kHz The gain should be less than 20dB.
The following simplified schematic shows an example of 2nd order anti-aliasing filter that has
20dB gain and 39kHz cut-off frequency.
11
C1=0.47uF
RXINO
C2=33pF
R3
C2
_
+
10
RXIN
R1 C1
R2
C3=560pF
R1=10kΩ
C3
RXA1
R2=9.1kΩ
AGND
R3=100kΩ
LSI
4) Power supply stabilizing capacitors
To connect capacitors between VDD and VSS pin reduce the ripple and noise included in power
supply. These capacitors are mounted close to the device pins.
7
VDD
DVDD
C1=0.1µF (Ceramic cap)
C1
C2
C2=10µF (Electrolytic cap)
8
VSS1
9
C1
C2
VSS
AVDD
LSI
5) AGND, AGNDIN pin stabilizing
Please decouple to VSS level by the 0.3uF or larger capacitor. These capacitors are mounted
close to the device pins.
14
AGNDIN
15
AGND
C
C
MS1289-E-04
LSI
C=1µF (Electrolytic capacitor)
2013/12
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[AK2346A]
6) Clock Generation
The clock source can be chosen from either built-in crystal oscillator circuit or externally supplied.
When the built-in oscillator circuit is used, connect a 14.7456MHz crystal oscillator, a resistor,
and capacitors as shown in Fig. 1. AK2346A is designed to get a stable oscillation for the
electrical equivalent circuitry of quartz crystal unit: resonance resistance≤80Ω(Max.) and shunt
capacitance≤1.5pF(Max.). It is recommended that external 12pF capacitors should be connected
so that the total load capacitance does not exceed the load capacitance≤6pF (1.5pF+12pF//12pF)
or less. These external components are mounted as close to the device pins as possible.
When a clock signal is supplied externally, not only 3.6864MHz but also 7.3728MHz (twice higher
than 3.6864MHz), 11.0592MHz (three times higher than 3.6864MHz), and 14.7456MHz (four
times higher than 3.6864MHz) are supported. However, the internal frequency must always be
set to 3.6864MHz by selecting division by 2, 3, or 4 for the divider in the subsequent stage.
Connect the clock signal as shown in Fig. 2 or Fig. 3 according to the clock amplitude level.
The circuit in the first stage of the XIN pin has a constant threshold voltage (0.8V). Therefore, if
the high level of the input clock is 1.5V or higher and the low level is 0.5V or lower, connect the
clock signal as shown in Fig. 2. If the input clock amplitude (p-p value) is between 0.2V and 1.0V,
connect the clock signal as shown in Fig. 3.
When the clock is to be shared with peripheral ICs, the clock must be input and output on the XIN
pin. The clock amplitude must not exceed the absolute maximum rating.
XIN
12pF
External Clock IN
6
XIN
14.7456MHz
1MΩ
XOUT
3.6864MHz
7.3728MHz
11.0592MHz
5
12pF
LSI
14.7456MHz
LSI
Fig. 1
XIN
Fig. 2
0.01uF
External Clock IN
3.6864MHz
7.3728MHz
XOUT
11.0592MHz
LSI
14.7456MHz
Fig. 3
MS1289-E-04
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[AK2346A]
19. Packaging
• Marking
2346A
YWWL
●
[Contents of XXXYZ]
Y : Date of manufacturing, Last digit of the year
WW : Date of manufacturing, 2 digits of week number
L : Production lot number
• 24-pin QFNJ Mechanical Outline (4.0 x 4.0 x 0.75mm, 0.5mm pitch)
4.0±0.1
2.40
18
13
12
19
7
24
1
6
B
C0.30
2.0
0.05 M S
A
0.22±0.05
0.75MAX
0.12-0.18
0.17-0.27
0.00-0.05
0.05 S
0.70
0.5
0.05MAX
S
Part A
0.40±0.1
2.0
2.40
4.0±0.1
A
Detailed chart in part A
Note: The exposed pad at the center of the back of the package must be connected to
VSS or opened.
MS1289-E-04
2013/12
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[AK2346A]
20. Important Notice
IMPORTANT NOTICE
0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the information
contained in this document without notice. When you consider any use or application of AKM product
stipulated in this document (“Product”), please make inquiries the sales office of AKM or authorized
distributors as to current status of the Products.
1. All information included in this document are provided only to illustrate the operation and application
examples of AKM Products. AKM neither makes warranties or representations with respect to the accuracy
or completeness of the information contained in this document nor grants any license to any intellectual
property rights or any other rights of AKM or any third party with respect to the information in this
document. You are fully responsible for use of such information contained in this document in your product
design or applications. AKM ASSUMES NO LIABILITY FOR ANY LOSSES INCURRED BY YOU OR
THIRD PARTIES ARISING FROM THE USE OF SUCH INFORMATION IN YOUR PRODUCT
DESIGN OR APPLICATIONS.
2. The Product is neither intended nor warranted for use in equipment or systems that require extraordinarily
high levels of quality and/or reliability and/or a malfunction or failure of which may cause loss of human
life, bodily injury, serious property damage or serious public impact, including but not limited to,
equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment,
equipment used for automobiles, trains, ships and other transportation, traffic signaling equipment,
equipment used to control combustions or explosions, safety devices, elevators and escalators, devices
related to electric power, and equipment used in finance-related fields. Do not use Product for the above use
unless specifically agreed by AKM in writing.
3. Though AKM works continually to improve the Product’s quality and reliability, you are responsible for
complying with safety standards and for providing adequate designs and safeguards for your hardware,
software and systems which minimize risk and avoid situations in which a malfunction or failure of the
Product could cause loss of human life, bodily injury or damage to property, including data loss or
corruption.
4. Do not use or otherwise make available the Product or related technology or any information contained in
this document for any military purposes, including without limitation, for the design, development, use,
stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products
(mass destruction weapons). When exporting the Products or related technology or any information
contained in this document, you should comply with the applicable export control laws and regulations and
follow the procedures required by such laws and regulations. The Products and related technology may not
be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited
under any applicable domestic or foreign laws or regulations.
5. Please contact AKM sales representative for details as to environmental matters such as the RoHS
compatibility of the Product. Please use the Product in compliance with all applicable laws and regulations
that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS
Directive. AKM assumes no liability for damages or losses occurring as a result of noncompliance with
applicable laws and regulations.
6. Resale of the Product with provisions different from the statement and/or technical features set forth in this
document shall immediately void any warranty granted by AKM for the Product and shall not create or
extend in any manner whatsoever, any liability of AKM.
7. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written
consent of AKM.
MS1289-E-04
2013/12
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