データシート

[AK7782]
AK7782
24bit 5ch ADC & SRC
AK7782
5ch 24ADC
2ch
8
2
96kHz
DSP
2
FIR
[DSP1/DSP2
Dual DSP
ADC
ADC 7.35kHz96kHz
2560step / fs (48kHz
RAM 6kword 2
RAM
DSP
)
] DSP1, DSP2
□
□
□
: 28bit
:
8.1ns
2560fs
: fs= 48kHz,44.1kHz
fs= 8kHz,7.35kHz
fs= 96kHz,88.2kHz
□ : 24
□ : 24
□ ALU: 44bit
16
40bit
24
24bit
fs=48kHz
()
()
2560
15360
1280
4bit
24bit
□ : 1, 2, 4, 5, 8, 14, 15bit
1,2,3,4,8,14,15bit BUS
1,2,3,4,8,15bit
1,2,3,4,6,8,15bit BUS
□
RAM(PRAM) : 2048word 36bit
□
RAM(CRAM): 2048word 16bit
□ RAM(DRAM): 2048word
28bit
□
(OFREG): 64word 13bit
□ RAM(DLRAM): 168kbit
4
● 6kword 28bit
● 4kword 28bit + 4kword 14bit
● 3kword 28bit + 6kword 14bit
● 3kword 28bit + 3kword 28bit (Linear)
□ : 44bit
28bit
28bit
4 (ACC) ALU
12 (TMP) DBUS
6
(PTMP)
MS1337-J-00
DBUS
2011/11
- 1-
[AK7782]
[ADC ADC1, ADC2]
□ 24bit 2ch x 2
□ S/(N+D) 90dB (fs=48kHz)
□ D-range 96dBA (fs=48kHz)
□ S/N 96dBA (fs=48kHz)
□ 8ch
□ DC
HPF (
□ fs=7.35kHz ~ 96kHz
[ADC
)
]
□ 24bit 1ch
□ S/(N+D) 88dB (fs=48kHz)
□ D-range 95dBA (fs=48kHz)
□ S/N 95dBA (fs=48kHz)
□ DC
HPF (
□ fs=7.35kHz ~ 96kHz
□
)
[DSP1/DSP2
□
□
□
[SRC
]
14ch (ADC
)
16ch ( DSP
14ch
)
2
1
or I C BUS
SRC1, SRC2]
□ 2ch x 2
□ fs=7.35kHz ~ 96kHz
[
]
□ PLL
□ 3.3V 0.3V 1.8V ±0.1V
□
-40 ~ 85
□ 100pin LQFP
MS1337-J-00
2011/11
- 2-
[AK7782]
AINM
AINL8, AINR8
AINL5, AINR5
AINL6 AINR6
AINL7, AINR7
AINL3, AINR3
AINL4, AINR4
AINL+,AINR+
AINL+,AINR+
AINL2, AINR2
■
pull down
Hi-z
VSS2
DVDD18
I/O
VSS3
DVDD
ctrl reg sw
AVDD
VREFH
VCOM
VREFL
VSS1
OUTASEL1
0
1
2
3
SDIN7/JX2
SDIN6 / JX1
P1IN6SEL
SDIN5
P1IN5SEL
P1SDIN7
0 1
P2IN7SEL
P1SDOUT7
0
1
2
3
0
1
2
3
P1SDIN6
P2SDIN7
0
1
2
3
0
1
2
3
P1SDIN5
SDIN2(32bit)
P1SDOUT5
IRPT1
P2IN5SEL
0
1
2
3
P1SDOUT4
GPO11
0
OUTAEN
0
1
2
3
P2SDOUT7
P2SDIN3
P1SDIN1
P1SDOUT1
JX12
SRC1I SRC1O
SRC1LRCKO
SRC1BICKO
JX11
JX10
SRC1
OUT4SEL
P2SDOUT4
GPO21
JX11E
OUT4EN
P2SDOUT3
GPO20
SDOUT4(32bit)
OUT3SEL
0
1
2
3
OUT3EN
SDOUT3(32bit)
OUT2SEL
0
1
2
3
OUT2EN
SDOUT2(32bit)
OUT1SEL1
0
1
2
3
P2SDIN1
SDOUT5
OUT1EN
SDOUT1
P2SDOUT1
JX22E
JX22
P2IN1SEL
JX21E
JX21
JX10E
JX20E
JX20
JX0
WDT1EN
DSP1
SRC1LRCKI
SRC1BICKI
JX12E
OUT5EN
0
1
2
3
P2SDOUT2
0
1
2
3
SDOUT6
OUT5SEL1
P2SDOUT5
IRPT2
P2SDIN2
1
P2IN2SEL
OUT6SEL
P2SDOUT6
P1SDOUT2
0
0
1
2
3
P2SDIN5
SDOUT7
OUT7EN
OUT6EN
0
1
2
3
P2SDIN4
1
P2IN4SEL
P1SDOUT3
GPO10
P1SDIN2
SRCLRCK
SRCBICK
SDOUTA
3
0
1
2
3
P2SDIN6
0
RSRC1RSTN
1
MSEL
P2IN6SEL
1
P2IN3SEL
PSRCRSTN
2 3
P1SDOUT6
P1SDIN3
PSRCSMUTE
0
OUT7SEL
SDIN3(32bit)
RSRC1SMUTE
1
2
2
P1SDIN4
P1IN1SEL
OUTASEL2
3
P1IN7SEL
SDIN4(32bit)
SDIN1
0
WDT1
CRCE
SRC1UNLOCK
DSP2
SRC2LRCK
SRC2BICK
NC
STO
WDT2EN
WDT2
LOCK1E
LOCK2E
0
1
2
3
RSRC2SMUTE
SRC2I SRC2O
SRC2LRCKO
SRC2BICKO
CRC
RSRCRST2N
0
1
SRC2
0
1
MICIF
SRC2CKO
SRC2LRCKI
1
SRC2CKI
I2CSEL
SDA
2
0
2
SCLK/SCL
SO
0
2
SI/CAD0
RQN/CAD1
2
1
TESTO
SRC2ISEL
RDY
SRC2BICKI
SRC2UNLOCK
LRCLKO
BITCLKO
TESTI2
TESTI1
CKM[2:0] 3
XTI
XTO
CONTROLLER
CKRSTN
PCKRSTN
RCKRSTN
PDSPRSTN
RDSPRSTN
(Master="H",Slave="L")
SMODE
DSPRSTN
SRESETN
PADRSTN
RADRSTN
ADRSTN
LFLT
CLKO1
LRCLKI
BITCLKI
INITRSTN
Figure 1.
MS1337-J-00
2011/11
- 3-
[AK7782]
■ DSP
(DSP1, DSP2
)
DLP0, DLP1
DP0, DP1
CP0, CP1
DLRAM
6kw x 28bit
DRAM
2048w x 28bit
CRAM
2048w x 16bit
etc
OFREG
64w x 13bit
CBUS(16bit)
DBUS(28bit)
MPX16
Micon I/F
MPX24
X
Control
DEC
Y
PRAM
2048w x 36bit
Multiply
16bit x 24bit → 40bit
PC
Stack: 5level(max)
TMP
28bit
40bit
12 x 28bit
PTMP(LIFO) 6 x 28bit
MUL
44bit
A
DBUS
2 x 24/24.4bit
SDIN7
SHIFT
2 x 24/24.4bit
SDIN6
44bit
2 x 24/24.4bit
SDIN5
2 x 24/20/16/32/24.4bit
SDIN4
2 x 24/20/16/32/24.4bit
SDIN3
2 x 24/20/16/32/24.4bit
SDIN2
2 x 24/24.4bit
SDIN1
B
ALU
44bit
Overflow Margin: 4bit
44bit
DR0-3
44bit
Over Flow Data
Generator
Division 24÷24→24
Serial I/F
2 x 24/24.4bit
SDOUT7
2 x 24/24.4bit
SDOUT6
2 x 24/24.4bit
SDOUT5
2 x 24/16/32/24.4bit
SDOUT4
2 x 24/16/32/24.4bit
SDOUT3
2 x 24/16/32/24.4bit
SDOUT2
2 x 24/24.4bit
SDOUT1
Peak Detector
MS1337-J-00
2011/11
- 4-
[AK7782]
■
-40 ∼ +85°C
100pin LQFP (0.5mm pitch)
Evaluation Board for AK7782
AK7782VQ
AKD7782
RDY
STO
SDOUTA1
SDOUT6
SDOUT7
DVDD
DVDD18
VSS3
SDIN7/JX2
SDIN6/JX1
JX0
SDIN1
SRCBICK
SRCLRCK
SDA
PSRCRSTN
DVDD18
VSS3
DVDD
TESTI2
PSRCSMUTE
VSS2
NC
VSS1
AVDD
■
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
NC
76
50
SO
AINM
49
48
DVDD
AINR4
77
78
VSS3
AINL4
79
47
DVDD18
AINR3
80
46
SCLK/SCL
AINL3
45
44
SI/CAD0
AINR2
81
82
AINL2
83
43
PDSPRSTN
AVDD
42
41
PADRSTN
VREFH
84
85
VCOM
86
40
INITRSTN
VREFL
87
39
VSS3
VSS1
38
37
DVDD18
AINR-
88
89
AINR+
90
36
BITCLKI
AINL-
35
34
SDIN5
AINR+
91
92
AINR5
93
33
SDIN3
AINL5
94
32
SDIN2
AINR6
31
30
DVDD18
AINL6
95
96
AINR7
97
29
DVDD
AINL7
28
27
CLKO1
AINR8
98
99
AINL8
100
26
SDOUT4
100 pin LQFP
(TOP VIEW)
RQN/CAD1
PCKRSTN
LRCLKI
SDIN4
VSS3
SDOUT5
SDOUT3
SDOUT2
SDOUT1
BITCLKO
LRCLKO
VSS3
DVDD
DVDD18
CKM[2]
CKM[0]
DVDD18
CKM[1]
XTO
VSS3
XTI
DVDD
VSS3
VSS2
SRC2BICK
SRC2LRCK
I2CSEL
AVDD
TESTI1
LFLT
VSS1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
pin
Input
Output
I/O
Power
Figure 2.
MS1337-J-00
2011/11
- 5-
[AK7782]
No. Pin Name
I/O
1
LFLT
O
2
3
VSS1
AVDD
-
4
TESTI1
I
5
I2CSEL
I
6
7
SRC2LRCK
SRC2BICK
I
I
8
VSS2
-
9
DVDD
-
10
VSS3
-
11
XTI
I
Function
AK7782
PLL RC
R=1.5kΩ, C=47nF
0V
Classification
9.(1)
3.3V (typ)
VSS3
I2CBUS
I2CSEL=“L”:
I2CSEL=“H”: I 2C
SCL, SDA
I2CSEL
“L(VSS3)”, “H(DVDD)”
SRC2 LR
SRC2 BIT
I2C
SRC2
VSS1
3.3V(typ)
0V
XTI pin
XTO pin
XTI pin
12
XTO
O
13
14
15
16
17
18
19
20
VSS3
DVDD18
CKM [1]
CKM [0]
CKM [2]
DVDD18
VSS3
DVDD
I
I
I
-
XTI pin
XTO pin
0V
1.8V(typ)
1.8V(typ)
0V
3.3V(typ)
MS1337-J-00
2011/11
- 6-
[AK7782]
No. Pin Name
I/O
21
LRCLKO
O
22
BITCLKO
O
23
SDOUT1
O
Function
Classification
LR
1fs
LRCLKI
64fs
BITCLKI
DSP
“L”
CONT7
“L”
CONT7
“L”
CONT7
“L”
CONT6
“L”
CONT6
D3, D2
DSP
24
SDOUT2
O
D5, D4
DSP
25
SDOUT3
O
D7, D6
DSP
26
SDOUT4
O
D1, D0
DSP
27
SDOUT5
O
D3, D2
1
28
CLKO1
O
29
30
31
DVDD
VSS3
DVDD18
-
“L”
32
33
34
35
SDIN2
SDIN3
SDIN4
SDIN5
I
I
I
I
3.3V(typ)
0V
1.8V(typ)
DSP
F24.4,
32bit, 24bit / 24bit, 20bit, 16bit
VSS3
DSP
F24.4,
32bit, 24bit / 24bit, 20bit, 16bit
VSS3
DSP
F24.4,
32bit, 24bit / 24bit, 20bit, 16bit
VSS3
DSP
24bit /
VSS3
24bit, 20bit, 16bit
MS1337-J-00
2011/11
- 7-
[AK7782]
No.
36
37
38
39
Pin Name
BITCLKI
LRCLKI
DVDD18
VSS3
I/O
I
I
-
40
INITRSTN
I
41
PCKRSTN
I
42
PADRSTN
I
43
44
45
PDSPRSTN
RQN
I
I
CAD1
I
SI
I
CAD0
I
SCLK
I
46
SCL
I
47
48
49
DVDD18
VSS3
DVDD
-
50
SO
O
Function
Classification
LR
1.8V(typ)
0V
N
INITRSTN= “L” AK7782
“L”
INITRSTN= “L”
CKM[2:0] pin
N
PCKRSTN= “L” AK7782
INITRSTN= “H”
PCKRSTN= “L”
pinRCKRSTN bit
= “L”
ADC
N
PADRSTN= “L” ADC1, ADC2, ADCM
RADRSTN bit= “L”
PADRSTN= “L”PDSPRSTN= “L”
CKM[2:0]
DSP
N
PDSPRSTN= “L” DSP1, DSP2
RDSPRSTN bit = “L”
PADRSTN= “L”
PDSPRSTN= “L”
I2CSEL= “L”
N
IF
RQN pin= “H”
I2CSEL= “H” I2C
I2CSEL= “L”
1
I2C
IF
SI pin= “L”
I2CSEL= “H” I2C
I2CSEL= “L”
0
I2C
IF
SCLK= “H”
I2CSEL= “H”
SCL I2C
I2C
1.8V(typ)
0V
3.3V(typ)
IF
RQN pin = “H”Hi-Z
“Hi-Z”
MS1337-J-00
2011/11
- 8-
[AK7782]
No. Pin Name
I/O
Function
51
RDY
O
52
STO
O
53
SDOUTA1
O
24bit
“L”
54
SDOUT6
O
24bit
“L”
55
SDOUT7
O
24bit
“L”
56
57
58
DVDD
VSS3
DVDD18
-
Classification
IF
“H”
SRCUNLOCK
Figure 1
“H”
WDTCRC
“L”
3.3V(typ)
0V
1.8V(typ)
DSP
SDIN7
I
JX2
I
SDIN6
I
JX1
I
61
JX0
I
62
SDIN1
I
63
64
SRCBICK
SRCLRCK
I
I
VSS3F24.4,
24-bit
VSS3F24.4,
24-bit
VSS3F24.4,
24-bit
59
VSS3
DSP
60
65
66
67
68
69
VSS3
VSS3
DSP/SRC
SRC
SRC LR
I2CSEL pin = “L”
O
SDA “L”
SDA
I2CSEL pin= “H”
I/O
SDA I2C
SRCN
PSRCRSTN I
PSRCRSTN= “L” SRC1, SRC2
R SRCRSTN= “L”
DVDD18
1.8V(typ)
VSS3
0V
DVDD
3.3V(typ)
70
VSS2
-
71
PSRC
SMUTE
I
VSS1
SRC
PSRCSMUTE pin= “H”SRC1, SRC2
RSRCSMUTE bit= “1”
MS1337-J-00
SRC1
I2C
SRC
2011/11
- 9-
[AK7782]
No. Pin Name
I/O
72
TESTI2
I
73
AVDD
-
74
VSS1
-
75
NC
-
76
NC
-
77
78
79
80
81
82
83
84
AINM
AINR4
AINL4
AINR3
AINL3
AINR2
AINL2
AVDD
I
I
I
I
I
I
I
-
85
VREFH
I
86
VCOM
O
87
VREFL
I
VSS1
AINRAINR+
AINLAINL+
AINR5
AINL5
AINR6
AINL6
AINR7
AINL7
AINR8
AINL8
I
I
I
I
I
I
I
I
I
I
I
I
88
89
90
91
92
93
94
95
96
97
98
99
100
Note 1.
Note 2.
Note 3. I2CSEL
Function
Classification
VSS3
3.3V (typ)
0V
NC
VSS1
NC
VSS1
ADCM
ADC1ADC2
ADC1ADC2
ADC1ADC2
ADC1ADC2
ADC1ADC2
ADC1ADC2
NC
NC
Rch4
Lch4
Rch3
Lch3
Rch2
Lch2
3.3V (typ)
AVDD
0.1μ F
0.1μF
10μF
VSS1
10μFVSS1
VSS1
0V
ADC1ADC2
ADC1ADC2
ADC1ADC2
ADC1ADC2
ADC1ADC2
ADC1ADC2
ADC1ADC2
ADC1ADC2
ADC1ADC2
ADC1ADC2
ADC1ADC2
ADC1ADC2
Rch
Rch
Lch
Lch
Rch5
Lch5
Rch6
Lch6
Rch7
Lch7
Rch8
Lch8
AINR-, AINR+, AINL-, AINL+, AINL2~8, AINR2~8, AINM
“L(VSS3)” “H(DVDD)”
MS1337-J-00
2011/11
- 10-
[AK7782]
■
AINL+, AINL-, AINR+, AINR-, AINL2, AINR2, AINL3, AINR3, AINL4,
AINR4, AINL5, AINR5, AINL6, AINR6, AINL7, AINR7, AINL8, AINR8, AINM
XTO, LRCLKO, BITCLKO, SDOUT1, SDOUT2, SDOUT3, SDOUT4, SDOUT5,
CLKO1, SO, RDY, STO, SDOTUA1, SDOUT6, SDOUT7, SDA(I2CSEL= “L”)
TESTI1, SRC2LRCK, SRC2BICK, XTI, SDIN2, SDIN3, SDIN4, SDIN5,
PCKRSTN, PADRSTN, SDIN7/JX2, SDIN6/JX1, JX0, SDIN1, SRCBICK,
VSS3
SRCLRCK, PSRCRSTN, PSRCSMUTE, TESTI2
Analog
Digital
I2CSELSDA
I2C
I2CSEL
L
L
H
H
INITRSTN
L
H
L
H
MS1337-J-00
SDA
L
L
“Hi-Z”pull-up
function
2011/11
- 11-
[AK7782]
(VSS1=VSS2=VSS3=0V; Note 4)
Parameter
Symbol
min
max
Unit
Analog (AVDD)
Digital (DVDD)
Digital (DVDD18)
|VSS1(VSS2) – VSS3| (Note 5)
(
)
VA
VD
VD18
GND
IIN
-0.3
-0.3
-0.3
-0.3
4.3
4.3
2.5
+0.3
10
V
V
V
V
mA
VINA
-0.3
(VA+0.3) 4.3
V
VIND
Ta
Tstg
-0.3
-40
-65
(VD+0.3) 4.3
85
150
V
AINL+, AINL-, AINR+, AINR-,
AINL2 8, AINR28, AINM
VREFH, VREFL
Note 4.
Note 5. VSS1, VSS2VSS3
:
(VSS1=VSS2=VSS3=0V; Note 4)
Parameter
Symbol
VA
AVDD
VD
DVDD
VD18
DVDD18
AVDD-DVDD
ΔVDD
(VREF)
VRH
VREFH
(Note 6)
VRL
VREFL
(Note 7)
Note 4.
Note 6. VREFHAVDD
Note 7. VREFLVSS1
Note 8.
<VREFH-VREFL>
Note 9. AVDD, DVDD, DVDD18INITRSTN pin = “L”
INITRSTN pin = “H”
Note 10. I2C BUS(I2CSEL= “H”)
ONAK7782OFF
SDA, SCLDVDD
DVDD
min
typ
max
Unit
3.0
3.0
1.7
-0.3
3.3
3.3
1.8
0
3.6
3.6
1.9
+0.3
V
V
V
V
VA
0.0
V
V
SDA, SCL Pin
:
MS1337-J-00
2011/11
- 12-
[AK7782]
(1)
1-1) ADC
(Ta=25
; AVDD=DVDD=3.3V; DVDD18=1.8V, VREFH=AVDD, VREFL=VSS1, BITCLK=64fs;
1kHz;
=20Hz20kHz@48kHz, 20Hz40kHz@96kHz; ADC
(ADC1, ADC2);
CKM Mode 0 (CKM[2:0]=000)SRC )
min
typ
max
Unit
24
Bits
ADC
S/(N+D)
fs = 48kHz (-1dBFS) Note 11)
82
90
dB
ADC1
fs = 96kHz (-1dBFS)
87
dB
ADC2
88
96
dB
fs = 48kHz (A)
Note 11, Note 12)
93
dB
fs = 96kHz
88
96
dB
S/N
fs = 48kHz (A)
Note 11)
93
dB
fs = 96kHz
90
115
dB
(f=1kHz)
Note 13)
DC
0.0
0.3
dB
Note 14)
Note 15)
Note 16)
1.85
1.85
22
2.00
2.00
33
2.15
2.15
24
Vp-p
Vp-p
k
Bits
ADC
ADCM
S/(N+D)
fs = 48kHz (-1dBFS)
fs = 96kHz (-1dBFS)
fs = 48kHz (A
fs = 96kHz
S/N
fs = 48kHz (A)
fs = 96kHz
78
)
Note 12)
87
87
Note 17)
Note 18)
Note 11.
Note 12. -60dBFSS/(N+D)
Note 13. -1dBFSLch-Rch
Note 14.
AINL+ AINL- AINR+ AINR( FS= (VREFH-VREFL)(2.0/3.3))
Note 15. AINL2
L8 AINR2
R8
(FS=(VREFH-VREFL)
(2.0/3.3))
Note 16. AINL+, AINL-, AINR+, AINR-, AINL2~L8, AINR2~R8
Note 17.
AINM
1.85
22
dB
dB
dB
dB
dB
dB
88
87
95
92
95
92
2.00
33
2.15
Vp-p
k
(FS=(VREFH-VREFL)(2.0/3.3))
Note 18. AINM
MS1337-J-00
2011/11
- 13-
[AK7782]
1-2) SRC
(Ta=25
°C; AVDD = 3.3V; DVDD=3.3V; DVDD18=1.8V; data = 24bit; measurement bandwidth =
20Hz∼ FSO/2)
Parameter
Symbol
min
typ
max
Unit
Resolution
24
Bits
Input Sample Rate
FSI
7.35
96
kHz
Output Sample Rate
FSO
7.35
96
kHz
THD+N
(Input= 1kHz, 0dBFS)
FSO/FSI=44.1kHz/48kHz
-112
dB
FSO/FSI=44.1kHz/96kHz
-112
dB
FSO/FSI=48kHz/44.1kHz
-112
dB
FSO/FSI=48kHz/96kHz
-112
dB
FSO/FSI=48kHz/8kHz
-111
-103
dB
FSO/FSI=8kHz/48kHz
-112
dB
FSO/FSI=8kHz/44.1kHz
-100
dB
Dynamic Range (Input= 1kHz, -60dBFS)
dB
113
FSO/FSI=44.1kHz/48kHz
dB
113
FSO/FSI=44.1kHz/96kHz
dB
113
FSO/FSI=48kHz/44.1kHz
dB
113
FSO/FSI=48kHz/96kHz
dB
109
112
FSO/FSI=48kHz/8kHz
dB
113
FSO/FSI=8kHz/48kHz
dB
113
FSO/FSI=8kHz/44.1kHz
Dynamic Range (Input= 1kHz, -60dBFS, A-weighted
dB
115
FSO/FSI=44.1kHz/48kHz
Ratio between Input and Output Sample Rate
FSO/FSI
0.167
6
MS1337-J-00
2011/11
- 14-
[AK7782]
DC
(Ta=-40°C~85°C, AVDD=DVDD=3.0~3.6V, DVDD18=1.7~1.9V)
Parameter
Symbol
min
VIH
80%DVDD
Note 19)
VIL
Note 19)
VIH
70%DVDD
SCL, SDA
VIL
SCL, SDA
VOH
DVDD-0.5
Iout=-100
μA
VOL
Iout=100
μA Note 20)
VOL
SDA
Iout=3mA
Iin
Note 21)
Iid
Note 22)
Iix
XTI pin
Note 19. SCL (I2CSEL= “1”), SDA pin(I2CSEL= “0”
SCLK pin
Note 20. SDA pin
Note 21. , XTI pin
Note 22. (Typ150k)
TESTI1, TESTI2
(Ta=25°C, AVDD=DVDD=3.0~3.6V(typ=3.3V
Parameter
(Note 23)
1) a) AVDD
b) DVDD
c) DVDD18
Note 23. DVDD18DSP
typ
max
20%DVDD
30%DVDD
0.5
0.4
10
22
26
Unit
V
V
V
V
V
V
V
μA
μA
μA
)
, max=3.6V), DVDD18=1.7~1.9V(typ=1.8V, max=1.9V))
min
MS1337-J-00
typ
max
Unit
52
8
140
70
15
210
mA
mA
mA
2011/11
- 15-
[AK7782]
1) ADC
: ADC1, ADC2
(Ta=-40°C~85°C; AVDD=DVDD=3.0~3.6V; DVDD18=1.7~1.9V; fs=48kHz (Note 24))
Parameter
Symbol
min
typ
PB
0
(0.005dB)
( Note 25)
21.768
(-0.02dB)
23.99
(-6.0dB)
SB
26.54
PR
(
Note 25)
SA
80
(Note 26, Note 27)
GD
GD
29
(Ts=1/fs)
20Hz~20.0kHz
Note 24. fs
Note 25. fs=48kHz
DC
Note 26. fs=48kHz
26.5kHz
Note 27. fs=48kHz3.072MHz
(n x 3.072MHz
2) ADC
max
21.5
0.005
0
0.01
Unit
kHz
kHz
kHz
kHz
dB
dB
μs
Ts
dB
21.5kHz
3.0455MHz
21.99kHz; n=0, 1, 2, 3 )
: ADCM
(Ta=-40°C ~85°C; AVDD=DVDD=3.0~3.6V; DVDD18=1.7~1.9V fs=48kHz; (Note 24))
Parameter
Symbol
min
typ
max
PB
0
21.5
(0.005dB) ( Note 25)
21.768
(-0.02dB)
23.99
(-6.0dB)
SB
26.54
PR
(
Note 25)
0.005
SA
80
(Note 26, Note 27)
0
GD
GD
29
(Ts=1/fs)
(
Note 28)
20Hz~20.0kHz
Note 24. fs
Note 25. fs=48kHz
DC
Note 26. fs=48kHz
26.5kHz
Note 27. fs=48kHz3.072MHz
(n x 3.072MHz
0.1
Unit
kHz
kHz
kHz
kHz
dB
dB
μs
Ts
dB
21.5kHz
3.0455MHz
21.99kHz; n=0, 1, 2, 3 )
Note 28. VOL + MUX1Ts
MS1337-J-00
2011/11
- 16-
[AK7782]
3) SRC (SRC1, SRC2 )
(Ta=-40°C ~85°C; AVDD=DVDD=3.0~3.6V, DVDD18=1.7~1.9V)
Parameter
Symbol
PB
-0.01dB
0.980FSO/FSI 6.000
PB
0.900FSO/FSI 0.990
PB
0.533FSO/FSI 0.909
PB
0.490FSO/FSI 0.539
PB
0.450FSO/FSI 0.495
PB
0.225FSO/FSI 0.455
PB
0.167FSO/FSI 0.227
SB
0.980FSO/FSI 6.000
SB
0.900FSO/FSI 0.990
SB
0.533FSO/FSI 0.909
SB
0.490FSO/FSI 0.539
SB
0.450FSO/FSI 0.495
SB
0.225FSO/FSI 0.455
SB
0.167FSO/FSI 0.227
PR
0.225FSO/FSI 6.000
PR
0.167FSO/FSI 0.227
0.450FSO/FSI 6.000
SA
SA
0.167FSO/FSI 0.455
GD
(Ts=1/fs)(
Note 29)
Note 29. L, R
SRCLRCK
LRCLKO
MS1337-J-00
min
0
0
0
0
0
0
0
0.5417FSI
0.5021FSI
0.2974FSI
0.2812FSI
0.2604FSI
0.1573FSI
0.1354FSI
typ
max
0.4583FSI
0.4167FSI
0.2182FSI
0.2177FSI
0.1948FSI
0.0917FSI
0.0917FSI
±0.01
±0.0612
95.2
92.3
56
L, R
Unit
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
dB
dB
dB
dB
Ts
2011/11
- 17-
[AK7782]
[16 #h (#=0, 1, 2,
9, A, B, C, D, E, F)]
1)
(Ta=-40°C~85°C, AVDD=DVDD=3.0~3.6V, DVDD18=1.7~1.9V)
Parameter
Symbol
min
XTI
CKM[2:0] 0h, 1h, 2h, 3h
a)
CKM[2:0]=0h, 2h
fXTI
CKM[2:0]=1h, 3h
fXTI
CKM[2:0]=0h, 2h
CKM[2:0]=1h, 3h
fXTI
fXTI
fs
typ
max
Unit
11.2896
12.288
16.9344
18.432
MHz
MHz
b)
LRCLKI
(Note 30)
40
11.0
16.5
7.35
50
48
60
12.4
18.6
96
%
MHz
MHz
kHz
BITCLKI
tBCLKH
tBCLKL
64
64
fBCLK
a) CKM[2:0]=2h, 3h
CKM[2:0]=2h, 3h
b) CKM[2:0]=4h, 5h
(Note 31)
CKM[2:0]=4h
CKM[2:0]=5h
Note 30. LRCLK
Note 31. BITCLKIMCLK
40
0.23
fBCLK
40
2.75
5.5
fBCLK
fBCLK
(fs)
ns
ns
64
50
64
50
60
6.2
60
3.1
6.2
1fsBITCLK
(Ta=-40°C ~85°C, AVDD=DVDD=3.0~3.6V, DVDD18=1.7~1.9V)
Parameter
Symbol
min
fs
7.35
SRCLRCK
(Note 30)
typ
48
fs
%
MHz
fs
%
MHz
MHz
64
max
96
Unit
kHz
SRCBICK
tBCLKH
tBCLKL
(Note 32)
Note 30. LRCLK
Note 32. 128fsfs=48kHz
64
64
fBCLK
32
40
0.23
ns
ns
50
128
60
6.2
fs
%
MHz
(fs)
MS1337-J-00
2011/11
- 18-
[AK7782]
2)
(Ta=-40°C ~85°C, AVDD=DVDD=3.0~3.6V; DVDD18=1.7~1.9V)
Parameter
Symbol
min
INITRSTN
(Note 33) tRST
600
PCKRSTN
tRST
600
PADRSTN
tRST
600
PDSPRSTN
tRST
600
PSRCRSTN
tRST
600
Note 33. “L”
typ
max
Unit
ns
ns
ns
ns
ns
3)
3-1) SDIN1~ SDIN7, SDOUT1~ SDOUT7, SDOUTA1 (fs =96kHz
I2S
(Ta=-40°C ~85°C, AVDD=DVDD=3.0~3.6V, DVDD18=1.7~1.9V, CL=20pF)
Parameter
Symbol
CKM[2:0]=2h, 3h, 4h, 5h
tBLRD
BITCLKI “↑”LRCLKI
(Note 34)
tLRBD
LRCLKI
BITCLKI “↑”
(Note 34)
tLRD
LRCLKI,LRCLKO
tBSOD
BITCLKI, BITCLKO
tBSIDS
tBSIDH
CKM[2:0]=0h, 1h
BITCLKO
BITCLKO
BITCLKO “↓”LRCLKO
LRCLKO
BITCLKO
Note 34. LRCLKI
min
tMBL
tLRD
tBSOD
tBSIDS
tBSIDH
typ
max
Unit
40
40
ns
ns
ns
ns
ns
ns
20
20
40
40
fBCLK
64
50
-20
40
40
40
40
40
fs
%
ns
ns
ns
ns
ns
BITCLKI
3-2) SDIN1, SDIN5 (SRC1I, SRC2I) (fs=96kHz
)
(Ta=-40°C ~85°C, AVDD=DVDD=3.0~3.6V, DVDD18=1.7~1.9V)
Parameter
Symbol
SRCBICK1“↑”SRCLRCK1
SRCLRCK1
SRCBICK1“↑” (
Note 35. SRCLRCK1
)
(Note 35)
Note 35)
tBLRD
tLRBD
tBSIDS
tBSIDH
min
20
20
40
40
typ
max
Unit
ns
ns
ns
ns
SRCBICK1
MS1337-J-00
2011/11
- 19-
[AK7782]
4
(Ta=-40°C ~85°C, AVDD=DVDD=3.0~3.6V; DVDD18=1.7~1.9V, CL=20pF)
Parameter
Symbol
min
SCLK
SCLK
SCLK
→AK7782
PDSPRSTN, PADRSTN“↓”RQN“
RQN“↑”PDSPRSTN, PADRSTN“
RQN
RQN“↓”SCLK“
↓”
SCLK“↑”RQN“
↑”
SI
SI
AK7782→
SCLK “↓”SO
SCLK “↑”SO
RQN“↓”SO Hi-Z
(Iout=±360μ
RQN“↑”SO Hi-Z
(Iout=±360μ
↓”
↑”
A)
A)
typ
max
Unit
2.1
fSCLK
tSCLKL
tSCLKH
200
200
MHz
ns
ns
tREW
tWRE
tWRQH
tWSC
tSCW
tSIS
tSIH
500
500
500
500
800
200
200
ns
ns
ns
ns
ns
ns
ns
tSOS
tSOH
tRQHR
tRQHS
MS1337-J-00
200
200
600
600
ns
ns
ns
ns
2011/11
- 20-
[AK7782]
5
I2C BUS
(Ta=-40°C ~85°C, AVDD=DVDD=3.0~3.6V, DVDD18=1.7~1.9V)
Parameter
Symbol
2
I C Timing
SCL clock frequency
fSCL
Bus Free Time Between Transmissions
tBUF
Start Condition Hold Time (prior to first Clock pulse)
tHD:STA
Clock Low Time
tLOW
Clock High Time
tHIGH
Setup Time for Repeated Start Condition
tSU:STA
min
max
tHD:DAT
0
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
tSU:DAT
tR
0.1
Fall Time of Both SDA and SCL Lines
tF
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed
By Input Filter
Capacitive load on bus
tSU:STO
tSP
0.6
0
Unit
400
KHz
μs
μs
μs
μs
μs
0.9
μs
0.3
μs
μs
0.3
μs
50
μs
ns
400
pF
1.3
0.6
1.3
0.6
0.6
SDA Hold Time from SCL Falling
Cb
typ
Note 36. I2C-bus NXP B.V.
MS1337-J-00
2011/11
- 21-
[AK7782]
■
1)
1/fXTI
1/fXTI
tXTI=1/fXTI
VIH
XTI
VIL
1/fs
ts=1/fs
1/fs
VIH
LRCLKI
SRCLRCK
VIL
1/fBCLK
1/fBCLK
tBCLK=1/fBCLK
VIH
BITCLKI
SRCBICK
VIL
tBCLKH
tBCLKL
Figure 3.
2)
INITRSTN
tRST
PCKRSTN
PADRSTN
VIL
PDSPRSTN
PSRCRSTN
Figure 4.
MS1337-J-00
2011/11
- 22-
[AK7782]
3)
LRCLKI
50%DVDD
LRCLKO
tBLRD
tMB tMBL
tLRBD
BITCLKI
50%DVDD
BITCLKO
tLRD
tBSOD
SDOUT *
50%DVDD
tBSIDS
tBSIDH
SDIN *
50%DVDD
SDIN * =SDIN1, SDIN2, SDIN3, SDIN4, SDIN5, SDIN6, SDIN7
SDOUT * =SDOUT1, SDOUT2, SDOUT3, SDOUT4, SDOUT5, SDOUT6, SDOUT7, SDOUTA1
Figure 5. I
2
C
SRCLRCK
SRCLRCK2
50%DVDD
tBLRD
tLRBD
50%DVDD
SRCBICK
SRCBICK2
tBSIDS
SRCI=
SDIN1,SDIN5
tBSIDH
50%DVDD
Figure 6. SRC
MS1337-J-00
2011/11
- 23-
[AK7782]
4)
VIH
VIL
RQN
VIH
VIL
SCLK
tSCLKL
tSCLKH
1/fSCLK
1/fSCLK
Figure 7.
tWRE
tREW
PDSPRSTN
VIL
PADRSTN
VIH
VIL
tWRQH
RQN
tWSC
VIH
SI
VIL
tSIS
tSIH
VIH
VIL
SCLK
tSCW
Figure 8.
tWSC
tSCW
→ AK7782
VIH
VIL
SCLK
VIH
SO
VIL
tSOS
tSOH
Figure 9. AK7782 →
Note 37. RUNPDSPRSTN,
PADRSTN “H”
MS1337-J-00
2011/11
- 24-
[AK7782]
VIH
VIL
RQN
tRQHS
tRQHR
Hi-Z
SO
Figure 10. SO
5) I2C
VIH
SDA
VIL
tBUF
tLOW
tR
tHIGH
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
tHD:DAT
tSU:DAT
Start
tSU:STA
tSU:STO
Start
Stop
Figure 11. I2C
MS1337-J-00
2011/11
- 25-
[AK7782]
■
1) CKM[2:0]
AK7782
CKM[2:0]
MCLK
CKM[2:0] pin
CKM
Mode
CKM
[2:0]
Master
Slave
(ICLK)
MCLK
0
000 Master
XTI
1
001 Master
XTI
2
010 Slave
XTI
3
011 Slave
XTI
4
100 Slave
BITCLKI
5
101 Slave
BITCLKI
6
110 TEST
N/A
7
111 TEST
N/A
Note 38. fs=44.1kHz44.1/48
16.9344MHZ
)
Note 39. CKM mode 6, 7
TEST
Note 40. CKM mode 0~3(fs)
Note 41. CKM mode 2, 3
(Master)(Slave)
ICLK
MCLK
(ICLK)
12.288MHz (Note 38)
18.432MHz (Note 38)
12.288MHz (Note 38)
18.432MHz (Note 38)
64fs(fs=48,44.1kHz)
64fs(fs=96,88.2kHz)
N/A
N/A
(
XTI
XTI
XTI, BITCLKI, LRCLKI
XTI, BITCLKI, LRCLKI
BITCLKI, LRCLKI
BITCLKI, LRCLKI
N/A
N/A
0, 211.2896MHz
1, 3
-
CONT00
XTILRCLKI
Note 42. CKM mode 4, 5fs
Note 43. CKM mode 4, 5 BITCLKI
BITCLKILRCLKI
LRCLKI64
[]
“L”
0,1
##h
0
“H”1
16(#=0, 1, 2, ~, 9, A, B, C, D, E, F)
MS1337-J-00
2011/11
- 26-
[AK7782]
ICLK
XTI pin
CKM Mode 0, 1, 2, 3
(MCLK
MCLK
PLL
)
ICLK
BITCLKI pin
CKM Mode 4, 5
REFCLK
(MCLK
REFCLK
MCLK
PLL
)
MCLK 122.88MHz or 112.896MHz
Figure 12. MCLK(ICLK)
1-1.
MCLK
CKM Mode0, 1
fs:
CKM
CKM
XTI
Mode
0
1
[2:0]
000
001
fs:48kHz
12.288MHz
18.432MHz
fs:44.1kHz
11.2896MHz
16.9344MHz
XTI
XTI
(1fs) , BITCLKO (64fs) LRCLKO, BITCLKO
LRCLKI, BITCLKI
XTI
(MHz)
11.0~12.4
16.7~18.6
LRCLKO
(INITRSTN
pin= “L”)
“L”(VSS3)
AK7782
XTI pin
CKM mode 0~3XTI
XTOXTI
XTI
XTI
External Clock
XTO
XTO
AK7782
CKM Mode 0-3
AK7782
CKM Mode 0-3
(CONT00)
MS1337-J-00
2011/11
- 27-
[AK7782]
1-2.
XTI
(CKM Mode2, 3)
fs:
CKM
CKM
XTI
Mode
2
3
[2:0]
010
011
fs:48kHz
12.288MHz
18.432MHz
(MHz)
11.0~12.4
16.7~18.6
fs:44.1kHz
11.2896MHz
16.9344MHz
XTI, LRCLKI, BITCLKI
XTI
LRCLKI
LRCLKO, BITCLKO LRCLKI, BITCLKI
DVD
(Master)
XTI
LRCLKI
BITCLKI
Clk Gen.
CKM2, 3
LRCLKO
BITCLKO
DAC
(Slave)
CLKO
AK7782
MS1337-J-00
2011/11
- 28-
[AK7782]
1-3.
BITCLKI
CKM Mode4, 5
CKM Mode 4, 5
BITCLKIXTI BITCLKI
PLL
(MCLK)
64BITCLKI
BITCLKILRCLKI
LRCLKI
fs:
CKM
CKM
BITCLKI
Mode
4
5
[2:0]
100
101
BITCLKI
64fs(fs=48,44.1kHz)
64fs(fs=96,88.2kHz)
fs:48kHz
3.072MHz
6.144MHz
fs:44.1kHz
2.8224MHz
5.6448MHz
2.75~3.1MHz
5.5~6.2MHz
XTI
0
1
XTO
BITCLKI
External
Clock
MCLK
CKM[2:0]
CKM[2:0]=4h,5h
“1”
BITCLK
AK7782
Figure 13.
(CONT00)
DFS Mode
CKM[2:0] pin
AK7782XTI pin = “L”(VSS3)
1-4. CKM[2:0]
CKM[2:0] pin
MS1337-J-00
2011/11
- 29-
[AK7782]
1-5. CKM[2:0] Pin
Slave/
CKM
CKM
Master
M
M
M
M
M
M
M
M
S
S
S
S
S
S
S
S
S
S
Mode
0, 1
0, 1
0, 1
0, 1
0, 1
0, 1
0, 1
0, 1
2, 3
2, 3
2, 3
2, 3
2, 3
2, 3
2, 3
2,3
4
5
[2:0]
00X
00X
00X
00X
00X
00X
00X
00X
01X
01X
01X
01X
01X
01X
01X
01X
100
101
Note 44. DFS mode
DFS
Mode
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
-
DFS
[2:0]
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
-
fs(kHz)
48, 44.1
96, 88.2
N/A
32, 29.4
12, 11.025
24, 22.05
16, 14.7
8, 7.35
48,44.1
96,88.2
N/A
32, 29.4
12, 11.025
24, 22.05
16, 14.7
8, 7.35
48,44.1
96,88.2
BITCLK
64fs
64fs
64fs
64fs
64fs
64fs
64fs
64fs
64fs
64fs
64fs
64fs
64fs
64fs
64fs
64fs
I2S
64fs
64fs
64fs
64fs
64fs
64fs
64fs
64fs
64fs
64fs
64fs
64fs
64fs
64fs
64fs
64fs
(X: Don’t care)
CONT00 DFS[2:0] (D7, D6, D5)
MS1337-J-00
2011/11
- 30-
[AK7782]
■
AK7782
W
R
Name
C0h
40h
CONT00
C1h
41h
CONT01
C2h
42h
CONT02
C3h
43h
CONT03
C4h
44h
CONT04
C5h
45h
CONT05
C6h
46h
CONT06
C7h
47h
CONT07
C8h
48h
CONT08
C9h
CAh
49h
4Ah
CONT09
CONT0A
CBh
4Bh
CONT0B
CCh
4Ch
CONT0C
CDh
4Dh
CONT0D
CEh
4Eh
CONT0E
CFh
4Fh
CONT0F
D0h
D1h
50h
51h
CONT10
CONT11
D2h
52h
CONT12
D3h
53h
CONT13
D4h
54h
CONT14
D5h
55h
CONT15
D6h
56h
CONT16
Note 45.
Note 46.
Note 47. TESTTEST
D7
D6
D5
D4
D3
D2
D1
Default
D0
CLK1S[0]
RCK
RSTN
00h
Reserved
Reserved
00h
Reserved
Reserved
00h
P1
WAVP[0]
P1
IN1SEL[1]
P2
IN1SEL[1]
OUT4
SEL[1]
P1
EFEN
P1
IN1SEL[0]
P2
IN1SEL[0]
OUT4
SEL[0]
MSEL[1]
MSEL[0]
00h
CLKO1EN
00h
OUT1EN
BICKOEN
00h
00h
TEST
00h
TEST
00h
TEST
00h
TEST
00h
DFS[2]
DFS[1]
DFS[0]
DIFI2S
CLK1S[2]
CLK1S[1]
P1
DATARAM
P2
DATARAM
P2
WAVM
P1
IN7SEL[1]
P2
IN7SEL[1]
OUT7
SEL[1]
OUT3
SEL[1]
OUTA
SEL2[1]
OUTAEN
P2JX2E
P2
WDTEN
P1
DIF7
P2
DIF7
P1
DOF7
P2
DOF7
VOL[5]
ASEL2[2]
SRC2
ISEL[1]
SRC1
BIEDGE
SRC2
BIEDGE
PSDSP2
RSRC2
SMUTE
P1
BANK[1]
P2
BANK[1]
P2
WAVP[1]
P1
IN7SEL[0]
P2
IN7SEL[0]
OUT7
SEL[0]
OUT3
SEL[0]
OUTA
SEL2[0]
OUT7EN
P2JX1E
P1
WDTEN
P1
DIF6
P2
DIF6
P1
DOF6
P2
DOF6
VOL[4]
ASEL2[1]
SRC2
ISEL[0]
SRC1
IDIF[2]
SRC2
IDIF[2]
PSDSP1
RSRC1
SMUTE
P1
BANK[0]
P2
BANK[0]
P2
WAVP[0]
P1
IN6SEL[1]
P2
IN6SEL[1]
OUT6
SEL[1]
OUT2
SEL[1]
OUTA
SEL1[1]
OUT6EN
P2JX0E
P1
POMODE
P2
POMODE
P2
EFEN
P1
IN6SEL[0]
P2
IN6SEL[0]
OUT6
SEL[0]
OUT2
SEL[0]
OUTA
SEL1[0]
OUT5EN
P1JX2E
SRC2
LOCKE
P1
DIFD[2]
P2
DIFD[2]
P1
DOFD[2]
P2
DOFD[2]
VOL[2]
ASEL1[2]
SRC2
CKI[0]
SRC1
IDIF[0]
SRC2
IDIF[0]
PSSRC1
RDSP
RSTN
P1
SS[1]
P2
SS[1]
P1
WAVM
P1
IN5SEL[1]
P2
IN5SEL[1]
OUT5
SEL[1]
OUT1
SEL[1]
P2
IN4SEL
OUT4EN
P1JX1E
SRC1
LOCKE
P1
DIFD[1]
P2
DIFD[1]
P1
DOFD[1]
P2
DOFD[1]
VOL[1]
ASEL1[1]
SRC2
CKO[1]
SRC1
BIFS[1]
SRC2
BIFS[1]
PSADC2
RAD
RSTN
P1
SS[0]
P2
SS[0]
P1
WAVP[1]
P1
IN5SEL[0]
P2
IN5SEL[0]
OUT5
SEL[0]
OUT1
SEL[0]
P2
IN3SEL
OUT3EN
P1JX0E
P2
IN2SEL
OUT2EN
LRCKOEN
TEST
TEST
P1
DIFD[0]
P2
DIFD[0]
P1
DOFD[0]
P2
DOFD[0]
VOL[0]
ASEL1[0]
SRC2
CKO[0]
SRC1
BIFS[0]
SRC2
BIFS[0]
PSADC1
P1
DIF1
P2
DIF1
P1
DOF1
P2
DOF1
TEST
MUX[1]
TEST
00h
TEST
MUX[0]
00h
00h
Reserved
Reserved
00h
SRC1
SEMIAUTO
SRC2
SEMIAUTO
PSADCM
SRC1
AUTOSEL
SRC2
AUTOSEL
Reserved
Reserved
Reserved
Reserved
CRCE
P1
DIF5
P2
DIF5
P1
DOF5
P2
DOF5
VOL[3]
ASEL2[0]
SRC2
CKI[1]
SRC1
IDIF[1]
SRC2
IDIF[1]
PSSRC2
RSRC
RSTN
CONT00
“0”
MS1337-J-00
2011/11
- 31-
00h
00h
00h
00h
00h
00h
00h
00h
[AK7782]
1) CONT00:
W
C0h
R
40h
Name
CONT00
D7
DFS[2]
D6
DFS[1]
D5
DFS[0]
D4
DIFI2S
D3
CLK1S
[2]
D2
CLK1S
[1]
D1
CLK1S
[0]
D0
RCK
RSTN
Default
00h
D7, D6, D5: DFS[2:0]
DFS
DFS
CKM
fs(kHz)
Mode
[2:0]
Mode
48kHz
0
000
0-3
48
1
001
0-3
96
2
010
0-3
N/A
3
011
0-3
32
4
100
0-3
12
5
101
0-3
24
6
110
0-3
16
7
111
0-3
8
4
48
5
96
Note 48. DFS mode CKM mode 0~3
Note 49. DFS mode 0~7(fs)
Note 50. DFS mode2
fs(kHz)
44.1kHz
44.1
88.2
N/A
29.4
11.025
22.05
14.7
7.35
44.1
88.2
D4: DIFI2S
0: (default)
1: I2S
I2S
AK7782
fs:
DSP
STEP
2560
1280
3840
10240
5120
7680
15360
2560
1280
ADC
(default)
-
I2S
D3, D2, D1: CLK1S[2:0] CLKO1
CLKO1
CLK1S Mode
0
1
2
3
4
5
6
7
CLK1S mode 7XTI
CLK1S[2:0]
000
001
010
011
100
101
110
111
D0: RCKRSTN
0:
1:
fs=48kHz
12.288MHz
6.144MHz
3.072MHz
8.192MHz
4.092MHz
2.048MHz
24.576MHz
XTI
fs=44.1kHz
11.2896MHz
5.6448MHz
2.8224MHz
7.5264MHz
3.7632MHz
1.8816MHz
22.5792MHz
XTI
(Default)
N
(default)
N
PCKRSTN pin
“L”(VSS3)
MS1337-J-00
2011/11
- 32-
[AK7782]
2) CONT01: DSP1 RAM
DSP
W
C1h
R
Name
41h
CONT01
D7
D6
P1
P1
DATARAM BANK[1]
D5
P1
BANK[0]
D4
P1
POMODE
D3
D2
P1
P1
SS[1] SS[0]
D1
D0
Default
0
0
00h
D7: P1DATARAM DSP1 DATARAM
DSP1 DATARAM
mode
0
1
A(000h-3FFh)
1024word
B(400h-7FFh)
1024word
(default)
DP0
DP1
D6, D5: P1BANK[1:0] DSP1 DLRAM Mode
DSP1 DLRAM
P1BANK[1:0] Ring 28bit
0
1
2
3
00
01
10
11
D4: P1POMODE DSP1 DLRAM
0: OFRAM
(default)
1: DBUS
Ring 14bit
6144word
4096word
3072word
3072word
Linear
28bit
(default)
4096word
6144word
3072word
0
D3, D2: P1SS[1:0] DSP1 DLRAM
DSP1 SS Mode
P1SS[1:0]
0
00
1
01
2
2
10
4
3
11
8
Note 51. Mode 1, 2, 3
Note 52. DSP1 DLRAM mode 1, 2Ring14 bit
D1: Reserved
0:
0
(default)
D0: Reserved
0:
0
(default)
(default)
DSP1 DLRAM mode 0, 3
MS1337-J-00
Ring 28 bit
2011/11
- 33-
[AK7782]
3) CONT02: DSP2 RAM
DSP
W
C2h
R
Name
42h
CONT02
D7
D6
D5
D4
D3
P2
P2
P2
P2
P2
DATARAM BANK[1] BANK[0] POMODE SS[1]
D2
P2
SS[0]
D1
D0
Default
0
0
00h
D7: P2DATARAM DSP2 DATARAM
DSP2 DATARAM Mode
A(000h-3FFh)
1024word
B(400h-7FFh)
1024word
0
1
(default)
DP0
DP1
D6, D5: P2BANK[1:0] DSP2 DLRAM Mode
DSP2 DLRAM
0
1
2
3
P2BANK[1:0] Ring 28bit
00
6144word
01
4096word
10
3072word
11
3072word
D4: P2POMODE DSP2 DLRAM
0: OFRAM
(default)
1: DBUS
Ring 14bit
Linear 28bit
(default)
4096word
6144word
3072word
0
D3, D2: P2SS[1:0] DSP2 DLRAM
DSP2 SS Mode
P2SS[1:0]
0
00
1
01
2
2
10
4
3
11
8
Note 53. 1, 2, 3
Note 54. DSP2 DLRAM mode 1, 2Ring14 bit
D1: Reserved
0:
0
(default)
D0: Reserved
0:
0
(default)
(default)
DSP2 DLRAM Mode2, 3
MS1337-J-00
Ring 28 bit
2011/11
- 34-
[AK7782]
4) CONT03 DSP2 & DSP1 RAM
DSP
W
C3h
R
Name
43h
CONT03
D7
P2
WAVM
D6
P2
WAVP[1]
D5
P2
WAVP[0]
D4
P2
EFEN
D3
P1
WAVM
D2
P1
WAVP[1]
D1
P1
WAVP[0]
D0
P1
EFEN
Default
00h
D7: P2WAVM DSP2 CRAM WAV Mode
0: 1/4 Mode (default)
1: 1/2 Mode
1/4 modeCRAM
D6, D5: P2WAVP[1:0] DSP2 CRAM
DSP2 WAVP Mode
0
1
2
3
P2WAVP[1:0]
00
01
10
11
P2WAVM=0
33word
65word
129word
257word
D4: P2EFEN DSP2
0: EF, SJ, IN
(default)
1: EF, SJ, IN
P2WAVM=1
65word
129word
257word
513word
FFT
128
256
512
1024
P1WAVM=1
65word
129word
257word
513word
FFT
128
256
512
1024
(default)
EF, SJ, IN
D3: P1WAVM DSP1 CRAM WAV Mode
0: 1/4 Mode (default)
1: 1/2 Mode
1/4 modre CRAM
D2, D1: P1WAVP[1:0] DSP1 CRAM
DSP1 WAVP Mode
0
1
2
3
D0: P1EFEN DSP1
0: EF, SJ, IN
1: EF, SJ, IN
P1WAVP[1:0]
00
01
10
11
P1WAVM=0
33word
65word
129word
257word
(default)
EF, SJ, IN
(default)
MS1337-J-00
2011/11
- 35-
[AK7782]
5) CONT04 DSP1
W
C4h
R
44h
DSP
D7
P1IN7
CONT04
SEL[1]
Name
D6
P1IN7
SEL[0]
D5
P1IN6
SEL[1]
D4
P1IN6
SEL[0]
D3
P1IN5
SEL[1]
D2
P1IN5
SEL[0]
D1
P1IN1
SEL[1]
D0
P1IN1
SEL[0]
Default
00h
D7, D6: P1IN7SEL[1:0] DSP1 SDIN7
DSP1 IN7SEL Mode
0
1
2
3
P1IN7SEL[1:0]
00
01
10
11
DSP1 SDIN7
ADC2
SDIN7/JX2 pin
SRC1O
ADCM
(default)
D5, D4: P1IN6SEL[1:0] DSP1 SDIN6
DSP1 IN6SEL Mode
0
1
2
3
P1IN6SEL[1:0]
00
01
10
11
DSP1 SDIN6
ADC1
SDIN6/JX1 pin
ADCM
SRC1O
(default)
D3, D2: P1IN5SEL[1:0] DSP1 SDIN5
DSP1 IN5SEL Mode
0
1
2
3
P1IN5SEL[1:0]
00
01
10
11
DSP1 SDIN5
SDIN5 pin
SRC2O
ADC1
ADCM
(default)
D1, D0: P1IN1SEL[1:0] DSP1 SDIN1
DSP1 IN1SEL Mode
0
1
2
3
P1IN1SEL[1:0]
00
01
10
11
DSP1 SDIN1
SDIN1 pin
SRC1O
SRC2O
ADC2
MS1337-J-00
(default)
2011/11
- 36-
[AK7782]
6) CONT05 DSP2
W
C5h
R
45h
DSP
D7
P2IN7
CONT05
SEL[1]
Name
D6
P2IN7
SEL[0]
D5
P2IN6
SEL[1]
D4
P2IN6
SEL[0]
D3
P2IN5
SEL[1]
D2
P2IN5
SEL[0]
D1
P2IN1
SEL[1]
D0
P2IN1
SEL[0]
Default
00h
D7, D6: P2IN7SEL[1:0] DSP2 SDIN7
DSP2 IN7SEL Mode
0
1
2
3
P2IN7SEL[1:0]
00
01
10
11
DSP2 SDIN7
ADC2
SDIN7/JX2 pin
SRC1O
DSP1 SDOUT7
(default)
D5, D4: P2IN6SEL[1:0] DSP2 SDIN6
DSP2 IN6SEL Mode
0
1
2
3
P2IN6SEL[1:0]
00
01
10
11
DSP2 SDIN6
ADC1
SDIN6/JX1 pin
ADCM
DSP1 SDOUT6
(default)
D3, D2: P2IN5SEL[1:0] DSP2 SDIN5
DSP2 IN5SEL Mode
0
1
2
3
P2IN5SEL[1:0]
00
01
10
11
DSP2 SDIN5
SDIN5 pin
SRC2O
ADC1
DSP1 SDOUT5
(default)
D1, D0: P2IN1SEL[1:0] DSP2 SDIN1
DSP2 IN1SEL Mode
0
1
2
3
P2IN1SEL[1:0]
00
01
10
11
DSP2 SDIN1
SDIN1 pin
SRC1O
SRC2O
DSP1 SDOUT1
MS1337-J-00
(default)
2011/11
- 37-
[AK7782]
7) CONT06
W
R
Name
C6h
46h
CONT06
DSP
D7
OUT7
SEL[1]
D6
OUT7
SEL[0]
D5
OUT6
SEL[1]
D4
OUT6
SEL[0]
D3
OUT5
SEL[1]
D2
OUT5
SEL[0]
D1
OUT4
SEL [1]
D0
OUT4
SEL[0]
Default
00h
D7, D6: OUT7SEL[1:0] SDOUT7 pin
OUT7SEL Mode
0
1
2
3
OUT7SEL[1:0]
00
01
10
11
SDOUT7 pin
DSP1 SDOUT7
DSP2 SDOUT7
ADCM
SRC2O
(default)
D5, D4: OUT6SEL[1:0] SDOUT6 pin
OUT6SEL Mode
0
1
2
3
OUT6SEL[1:0]
00
01
10
11
SDOUT6 pin
DSP1 SDOUT6
DSP2 SDOUT6
ADC1
ADC2
(default)
D3, D2: OUT5SEL[1:0] SDOUT5 pin
OUT5SEL Mode
0
1
2
3
OUT5SEL[1:0]
00
01
10
11
OUT5SEL
DSP1 SDOUT5
DSP2 SDOUT5
DSP1 IRPT
DSP2 IRPT
(default)
D1, D0: OUT4SEL[1:0] SDOUT4 pin
OUT4SEL Mode
0
1
2
3
OUT4SEL[1:0]
00
01
10
11
OUT4SEL
DSP1 SDOUT4
DSP2 SDOUT4
DSP1 GPO1
DSP2 GPO1
MS1337-J-00
(default)
2011/11
- 38-
[AK7782]
8) CONT07
W
R
Name
C7h
47h
CONT07
DSP
D7
OUT3
SEL[1]
D6
OUT3
SEL[0]
D5
OUT2
SEL[1]
D4
OUT2
SEL[0]
D3
OUT1
SEL[1]
D2
OUT1
SEL[0]
D1
MSEL
[1]
D0
Default
MSEL[0]
00h
D7, D6: OUT3SEL[1:0] SDOUT3 pin
OUT3SEL Mode
0
1
2
3
OUT3SEL[1:0]
00
01
10
11
SDOUT3 pin
DSP1 SDOUT3
DSP2 SDOUT3
DSP1 GPO0
DSP2 GPO0
(default)
D5, D4: OUT2SEL[1:0] SDOUT2 pin
OUT2SEL Mode
0
1
2
3
OUT2SEL[1:0]
00
01
10
11
SDOUT2 pin
DSP1 SDOUT2
DSP2 SDOUT2
MUXOUT
SRC2O
(default)
D3, D2: OUT1SEL[1:0] SDOUT1 pin
OUT1SEL Mode
0
1
2
3
OUT1SEL[1:0]
00
01
10
11
OUT1SEL
DSP1 SDOUT1
DSP2 SDOUT1
MUXOUT
SRC1O
MSEL[1:0]
00
01
10
11
MSELOUT
DSP1 SDOUT1
DSP1 SDOUT5
DSP2 SDOUT1
DSP2 SDOUT5
(default)
D1, D0: MSEL[1:0] MUX
MSEL Mode
0
1
2
3
MS1337-J-00
(default)
2011/11
- 39-
[AK7782]
9) CONT08 SDOUTA
W
R
Name
C8h
48h
CONT08
, DSP2
DSP
D7
OUTA
SEL2[1]
D6
OUTA
SEL2[0]
D7, D6: OUTASEL2[1:0] SDOUTA pin
OUTASEL2 Mode
0
1
2
3
OUTASEL2[1:0]
00
01
10
11
D5, D4: OUTASEL1[1:0] SDOUTA pin
OUTASEL1 Mode
0
1
2
3
OUTASEL1[1:0]
00
01
10
11
D5
OUTA
SEL1[1]
D4
D3
D2
D1
OUTA
P2
P2
P2
SEL1[0] IN4SEL IN3SEL IN2SEL
D0
CLKO1
EN
Default
00h
2
SDOUTA pin
OUTASEL1
SRC2O
DSP1 SDOUT7
DSP1 SDOUT7
(default)
1
OUTASEL1
MUXOUT
ADC1
ADC2
SRC1O
(default)
D3: P2IN4SEL DSP2 SDIN4
0: SDIN4 pin
(default)
1: DSP1 SDOUT4
D2: P2IN3SEL DSP2 SDIN3
0: SDIN3 pin
(default)
1: DSP1 SDOUT3
D1: P2IN2SEL DSP2 SDIN2
0: SDIN2 pin
(default)
1: DSP1 SDOUT2
D0: CLKO1EN
0: CLKO1
1: CLKO1 pin= “L”
(default)
MS1337-J-00
2011/11
- 40-
[AK7782]
10) CONT09:
W
R
C9h 49h
Name
CONT09
DSP
D7
D6
D5
OUTAEN
OUT7EN
OUT6EN
D7: OUTAEN
0: SDOUTA
1: SDOUTA pin= “L”
(default)
D6: OUT7EN
0: SDOUT7
1: SDOUT7 pin= “L”
(default)
D5: OUT6EN
0: SDOUT6
1: SDOUT6 pin= “L”
(default)
D4: OUT5EN
0: SDOUT5
1: SDOUT5 pin= “L”
(default)
D3: OUT4EN
0: SDOUT4
1: SDOUT4 pin= “L”
(default)
D2: OUT3EN
0: SDOUT3
1: SDOUT3 pin= “L”
(default)
D1: OUT2EN
0: SDOUT2
1: SDOUT2 pin= “L”
(default)
D0: OUT1EN
0: SDOUT1
1: SDOUT1 pin= “L”
(default)
MS1337-J-00
D4
D3
OUT5EN OUT4EN
D2
D1
D0
OUT3EN
OUT2EN
OUT1EN
Default
00h
2011/11
- 41-
[AK7782]
11) CONT0A: JX
W
R
CAh 4Ah
Name
CONT0A
, LRCLKO, BITCLKO
DSP
D7
P2
JX2E
D6
P2
JX1E
D7: P2JX2E DSP2 JX2
0: DSP2 JX2
1: DSP2 JX2
(default)
D6: P2JX1E DSP2 JX1
0: DSP2 JX1
1: DSP2 JX1
(default)
D5: P2JX0E DSP2 JX0
0: DSP2 JX0
1: DSP2 JX0
(default)
D4: P1JX2E DSP1 JX2
0: DSP1 JX2
1: DSP1 JX2
(default)
D3: P1JX1E DSP1 JX1
0: DSP1 JX1
1: DSP1 JX1
(default)
D2: P1JX0E DSP1 JX0
0: SP1 JX0
1: DSP1 JX0
(default)
D1: LRCKOEN
0: LRCLKO
1: LRCLKO pin= “L”
D5
P2
JX0E
D4
P1
JX2E
D3
P1
JX1E
D2
D1
D0
Default
P1
LRCKOEN BICKOEN
00h
JX0E
(default)
D0: BICKOEN
0: BITCLKO (default)
1: BITCLKO pin= “L”
MS1337-J-00
2011/11
- 42-
[AK7782]
12) CONT0B: DSP
DSP
W
R
Name
CBh
4Bh
CONT0B
D7
P2
WDTEN
D6
P1
WDTEN
D5
CRCE
D4
SRC2
LOCKE
D3
SRC1
LOCKE
D2
D1
D0
TEST
TEST
TEST
Default
00h
D7: P2WDTEN
0: DSP2 WDT
(default)
1: DSP2 WDT
WDT: Watch dog timer
D6: P1WDTEN
0: DSP1 WDT
1: DSP1 WDT
(default)
D5: CRCE
0: CRC
1: CRC
(default)
D4: SRC2LOCKE
0: SRC2LOCK
1: SRC2LOCK
(default)
D3: SRC1LOCKE
0: SRC1LOCK
1: SRC1LOCK
(default)
D3, D2, D1: TEST
000:
001-111:
(default)
MS1337-J-00
2011/11
- 43-
[AK7782]
13) CONT0C: DSP1
W
CCh
R
4Ch
DSP
D7
P1
CONT0C
DIF7
Name
D6
P1
DIF6
D5
P1
DIF5
D4
P1
DIFD[2]
D3
P1
DIFD[1]
D2
P1
DIFD[0]
D1
P1
DIF1
D0
Default
TEST
00h
D7: P1DIF7 DSP1 SDIN7
P1DIF7 Mode
P1DIF7
0
0
(24bit)
1
1
F24.4
Note 55. DSP1 SDIN7ADC2, ADCM SRC1O
(default)
P1DIF7 mode0
D6: P1DIF6 DSP1 SDIN6
P1DIF6 Mode
P1DIF6
0
0
(24bit)
1
1
F24.4
Note 56. DSP1 SDIN6ADC1, ADCM
(default)
SRC1O
P1DIF6 mode0
D5: P1DIF5 DSP1 SDIN5
P1DIF5 Mode
P1DIF5
0
0
(24bit)
1
1
F24.4
Note 57. DSP1 SDIN5ADC1, ADCM SRC2O
(default)
P1DIF5 mode0
D4, D3, D2: P1DIFD[2:0] DSP1 SDIN4, DSP1 SDIN3, DSP1 SDIN2
P1DIFD Mode
P1DIFD
0
000
1
001
2
010
3
011
4
100
5
101
6
110
7
111
Note 58. I2S (DIFI2S bit = “1”)
(24bit)
24bit
20bit
16bit
F24.4
32bit
N/A
N/A
P1DIFD mode 0
(default)
D1: P1DIF1 DSP1 SDIN1
P1DIF1 Mode
P1DIF1
0
0
(24bit)
1
1
F24.4
Note 59. DSP1 SDIN1ADC2, SRC1O SRC2O
(default)
P1DIF1 mode0
D0: TEST
0:
1:
MS1337-J-00
2011/11
- 44-
[AK7782]
14) CONT0D: DSP2
W
R
CDh
4Dh
DSP
D7
P2
CONT0D
DIF7
Name
D6
P2
DIF6
D5
P2
DIF5
D4
D3
D2
P2
P2
P2
DIFD[2] DIFD[1] DIFD[0]
D1
P2
DIF1
D0
TEST
Default
00h
D7: P2DIF7 DSP2 SDIN7
P2DIF7 Mode
P2DIF7
0
0
(24bit)
1
1
F24.4
Note 60. DSP2 SDIN7ADC2 SRC1O
(default)
P2DIF7 mode 0
D6: P2DIF6 DSP2 SDIN6
P2DIF6 Mode
P2DIF6
0
0
(24bit)
1
1
F24.4
Note 61. DSP2 SDIN6ADC1 ADCM
(default)
P2DIF6 mode 0
D5: P2DIF5 DSP2 SDIN5
P2DIF5 Mode
P2DIF5
0
0
(24bit)
1
1
F24.4
Note 62. DSP2 SDIN5ADC1 SRC2O
(default)
P2DIF5 mode 0
D4, D3, D2: P2DIFD[2:0] DSP2 SDIN4, DSP2 SDIN3, DSP2 SDIN2
P2DIFD Mode
P2DIFD
0
000
1
001
2
010
3
011
4
100
5
101
6
110
7
111
2
Note 63. I SDIFI2S bit= “1”
(default)
(24bit)
24bit
20bit
16bit
F24.4
32bit
N/A
N/A
P2DIFD mode
0
D1: P2DIF1 DSP2 SDIN1
P2DIF1 Mode
P2DIF1
0
0
(24bit)
1
1
F24.4
Note 64. DSP2 SDIN1SRC1O SRC2O
D0: TEST
0:
1:
(default)
P2DIF1 mode 0
(default)
MS1337-J-00
2011/11
- 45-
[AK7782]
15) CONT0E: DSP1
W
R
CEh
4Eh
DSP
D7
D6
P1
P1
CONT0E
DOF7 DOF6
Name
D5
P1
DOF5
D4
P1
DOFD[2]
D3
P1
DOFD[1]
D2
P1
DOFD[0]
D1
P1
DOF1
D0
Default
TEST
00h
D7: P1DOF7 DSP1 SDOUT7
P1DOF7 Mode
0
1
P1DOF7
0
1
(24bit)
F24.4
(default)
(24bit)
F24.4
(default)
(24bit)
F24.4
(default)
D6: P1DOF6 DSP1 SDOUT6
P1DOF6 Mode
0
1
P1DOF6
0
1
D5: P1DOF5 DSP1 SDOUT5
P1DOF5 Mode
0
1
P1DOF5
0
1
D4, D3, D2: P1DOFD[2:0] DSP1 SDOUT4,DSP1 SDOUT3,DSP1 SDOUT2
P1DOFD Mode
P1DOFD
0
000
(24bit)
1
001
24bit
2
010
20bit
3
011
16bit
4
100
F24.4
5
101
32bit
6
110
N/A
7
111
N/A
Note 65. I2SDIFI2S bit= “1”
P1DOFD mode
(default)
0
D1: P1DOF1 DSP1 SDOUT1
P1DOF1 Mode
0
1
P1DOF1
0
1
(default)
(24bit)
F24.4
D0: TEST
0:
1:
MS1337-J-00
2011/11
- 46-
[AK7782]
16) CONT0F: DSP2
W
R
Name
CFh
4Fh
CONT0F
DSP
D7
P2
DOF7
D6
P2
DOF6
D5
P2
DOF5
D4
P2
DOFD[2]
D3
P2
DOFD[1]
D2
P2
DOFD[0]
D1
P2
DOF1
D0
Default
TEST
00h
D7: P2DOF7 DSP2 SDOUT7
P2DOF7 Mode
0
1
P2DOF7
0
1
(24bit)
F24.4
(default)
(24bit)
F24.4
(default)
(24bit)
F24.4
(default)
D6: P2DOF6 DSP2 SDOUT6
P2DOF6 Mode
0
1
P2DOF6
0
1
D5: P2DOF5 DSP2 SDOUT5
P2DOF5 Mode
0
1
P2DOF5
0
1
D4, D3, D2: P2DOFD[2:0] DSP2 SDOUT4, DSP2 SDOUT3, DSP2 SDOUT2
P2DOFD Mode
P2DOFD
0
000
1
001
2
010
3
011
4
100
5
101
6
110
7
111
Note 66. I2SDIFI2S bit= “1”
(default)
(24bit)
24bit
20bit
16bit
F24.4
32bit
N/A
N/A
P2DOFD mode
0
D1: P2DOF1 DSP2 SDOUT1
P2DOF1 Mode
0
1
D0: TEST
0:
1:
P2DOF1
0
1
(default)
(24bit)
F24.4
(default)
MS1337-J-00
2011/11
- 47-
[AK7782]
17) CONT10: ADCM
W
D0h
R
50h
Name
D7
CONT10 VOL[5]
D6
VOL[4]
D5
VOL[3]
D4
D3
D2
D1
VOL[2] VOL[1] VOL[0] TEST
D0
TEST
Default
00h
D7, D6, D5, D4, D3, D2: VOL[5:0] ADCM
VOL[5]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
VOL[4]
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
VOL[3]
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
D1: TEST
0:
1:
(default)
D0: TEST
0:
1:
(default)
VOL[2]
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
1
VOL[1]
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
-
VOL[0]
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
-
Volume (dB)
0
-2
-4
-6
-8
-10
-12
-14
-16
-18
-20
-22
-24
-26
-28
-30
-32
-34
-36
-38
-40
-42
-44
-46
-48
-50
-52
-54
-56
-58
-60
-∞
MS1337-J-00
(default)
2011/11
- 48-
[AK7782]
18) CONT11: ADC2, ADC1
W
D1h
R
51h
Name
CONT11
D7
ASEL2[2]
D6
ASEL2[1]
D5
ASEL2[0]
D4
ASEL1[2]
D3
D2
D1
ASEL1[1] ASEL1[0] MUX[1]
D0
MUX[0]
Default
00h
D7, D6, D5: ASEL2[2:0] ADC2
ASEL2[2:0]
000
001
010
011
100
101
110
111
Pin
AINL-, AINL+, AINR-, AINR+
AINL2, AINR2
AINL3, AINR3
AINL4, AINR4
AINL5, AINR5
AINL6, AINR6
AINL7, AINR7
AINL8, AINR8
(default)
D4, D3, D2: ASEL1[2:0] ADC1
ASEL1[2:0]
000
001
010
011
100
101
110
111
Pin
AINL-, AINL+, AINR-, AINR+
AINL2, AINR2
AINL3, AINR3
AINL4, AINR4
AINL5, AINR5
AINL6, AINR6
AINL7, AINR7
AINL8, AINR8
(default)
D1, D0: MUX[1:0] MUX
MUX Mode
MUX[1:0]
0
00
1
01
2
10
3
11
Note 67. MUX Mode3L ch, R ch
MUXOUT L ch
MSELOUT Lch
MSELOUT Lch
ADCM
ADCM
MUXOUT Rch
MSELOUT Rch
ADCM
MSELOUT Rch
ADCM
MS1337-J-00
(default)
2011/11
- 49-
[AK7782]
19) CONT12: SRC2
W
D2h
R
52h
SRC
D7
SRC2
CONT12
ISEL[1]
Name
D6
SRC2
ISEL[0]
D5
SRC2
CKI[1]
D4
SRC2
CKI[0]
D3
SRC2
CKO[1]
D2
SRC2
CKO[0]
D1
D0
Default
0
0
00h
D7, D6: SRC2ISEL[1:0] SRC2I
SRC2ISEL Mode
0
1
2
3
SRC2ISEL[1:0]
00
01
10
11
SRC2I
SDIN5 pin
SDIN1 pin
DSP1 SDOUT1
DSP2 SDOUT1
(default)
D5, D4: SRC2CKI[1:0] SRC2
SRC2CKI Mode
0
1
2
3
SRC2CKI[1:0]
00
01
10
11
SRC2LRCKI
SRC2LRCK pin
SRCLRCK pin
LRCLKO
N/A
SRC2BICKI
SRC2BICK pin
SRCBICK pin
BITCLKO
N/A
SRC2LRCKO
LRCLKO
SRCLRCK pin
SRC2LRCK pin
N/A
SRC2BICKO
BITCLKO
SRCBICK pin
SRC2BICK pin
N/A
(default)
D3, D2: SRC2CKO[1:0] SRC2
SRC2CKO Mode
0
1
2
3
SRC2CKO[1:0]
00
01
10
11
D1: Reserved
0:
0
(default)
D0: Reserved
0:
0
(default)
MS1337-J-00
(default)
2011/11
- 50-
[AK7782]
20) CONT13: SRC1
SRC
D7
D6
D5
D4
D3
D2
D1
D0
Default
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
D3h 53h CONT13
00h
BIEDGE IDIF[2] IDIF[1] IDIF[0] BIFS[1] BIFS[0] SEMIAUTO AUTOSEL
W
R
Name
D7: SRC1BIEDGE SRC1BICKI
0: SRC1LRCKI
1: SRC1LRCKI
SRC1PCM mode
SRC1IDIF mode 6, 7
D6, D5, D4: SRC1IDIF[2:0] SRC1I
fsi : SRC1
SRC1IDIF Mode
0
1
2
3
4
5
6
7
SRC1IDIF[2:0]
000
001
010
011
100
101
110
111
SRC1BICKI
32fsi
40fsi
48fsi
48fsi or 32fsi
48fsi
16bit
20bit
24/20bit
I2S24/16bit
24bit
N/A
PCM SHORT
PCM LONG
(default)
SRC1BIFS[1:0]
SRC1BIFS[1:0]
D3, D2: SRC1BIFS[1:0] SRC1BICKI fs
SRC1BIFS Mode
0
1
2
3
SRC1BIFS[1:0]
00
01
10
11
D1: SRC1SEMIAUTO SRC1
0: SRC1 SEMIAUTO OFF
1: SRC1 SEMIAUTO ON
D0: SRC1AUTOSEL SRC1
0: 2205/fso (default)
1: 8820/fso
SRC1BICKI
32fsi
64fsi
128fsi
48fs
(default)
SEMIAUTO
SEMIAUTO mode
Note 68. SRC124-bit
MS1337-J-00
2011/11
- 51-
[AK7782]
21) CONT14: SRC2
SRC
D7
D6
D5
D4
D3
D2
D1
D0
Default
SRC2
SRC2
SRC2
SRC2
SRC2
SRC2
SRC2
SRC2
D4h 54h CONT14
00h
BIEDGE IDIF[2] IDIF[1] IDIF[0] BIFS[1] BIFS[0] SEMIAUTO AUTOSEL
W
R
Name
D7: SRC2BIEDGE SRC2BICKI
0: SRC2LRCKI (default)
1: SRC2LRCKI
SRC2PCM mode (SRC2IDIF mode 6, 7)
D6, D5, D4: SRC2IDIF[2:0] SRC2I
fsi : SRC2
SRC2IDIF Mode
0
1
2
3
4
5
6
7
SRC2IDIF[2:0]
000
001
010
011
100
101
110
111
16bit
20bit
24/20bit
I2S24/16bit
24bit
N/A
PCM SHORT
PCM LONG
SRC2BICKI
32fsi
40fsi
48fsi
48fsi or 32fsi
48fsi
(default)
SRC2BIFS[1:0]
SRC2BIFS[1:0]
D3, D2: SRC2BIFS[1:0] SRC2BICKI fs
SRC2BIFS Mode
0
1
2
3
SRC2BIFS[1:0]
00
01
10
11
D1: SRC2SEMIAUTO SRC2
0: SRC2 SEMIAUTO OFF (default)
1: SRC2 SEMIAUTO ON
D0: SRC2AUTOSEL SRC2
0: 2205/fso (default)
1: 8820/fso
SRC2BICKI
32fsi
64fsi
128fsi
48fs
(default)
SEMIAUTO
SEMIAUTO Mode
Note 69. SRC224-bit
MS1337-J-00
2011/11
- 52-
[AK7782]
22) CONT15:
W
D5h
R
55h
Name
CONT15
D7: PSDSP2 DSP2
0:
(default)
1: DSP2
DSP2
“0”
D6: PSDSP1 DSP1
0:
(default)
1: DSP1
DSP1
“0”
D5: PSSRC2 SRC2
0:
(default)
1: SRC2
SRC2
“0”
D4: PSSRC1 SRC1
0:
(default)
1: SRC1
SRC1
“0”
D3: PSADC2 ADC2
0:
(default)
1: ADC2
ADC2
“0”
D2: PSADC1 ADC1
0:
(default)
1: ADC1
ADC1
“0”
D1: PSADCM ADCM
0:
(default)
1: ADCM
ADCM
“0”
D0: Reserved
0:
0
D7
PSDSP2
D6
PSDSP1
D5
PSSRC2
D4
PSSRC1
“1”
DSP2
“1”
DSP1
“1”
SRC2
“1”
SRC1
“1”
ADC2
“1”
ADC1
“1”
D3
PSADC2
D2
PSADC1
D1
PSADCM
D0
0
Default
00h
ADCM
(default)
MS1337-J-00
2011/11
- 53-
[AK7782]
23) CONT16:
W
R
Name
D6h
56h
CONT16
D7
RSRC2
SMUTE
D6
RSRC1
SMUTE
D5
RSRC
RSTN
D4
RDSP
RSTN
D3
RADC
RSTN
D2
D1
D0
Default
0
0
0
00h
D7: RSRC2SMUTE
0: SRC2 SOFT MUTE OFF (default)
1: SRC2 SOFT MUTE ON
SRC2SOFT MUTE
PSRCSMUTE pin
“L”(VSS3)“1”
D6: RSRC1SMUTE
0: SRC1 SOFT MUTE OFF (default)
1: SRC1 SOFT MUTE ON
SRC1SOFT MUTE
PSRCSMUTE pin
“L”(VSS3)“1”
D5: RSRCRSTN SRC
0: SRC1, SRC2
1: SRC1, SRC2
PSRCRSTNpin
N
(default)
D4: RDSPRSTN DSP
0: DSP1, DSP2
1: DSP1, DSP2
PDSPRSTNpin
N
(default)
D3: RADCRSTN ADC
0: ADC1, ADC2, ADCM
1: ADC1, ADC2, ADCM
PADRSTNpin
D2: Reserved
0:
0
(default)
D1: Reserved
0:
0
(default)
D0: Reserved
0:
0
(default)
“L”(VSS3)
“L”(VSS3)
N
(default)
“L”(VSS3)
MS1337-J-00
2011/11
- 54-
[AK7782]
■
1)
ADC
DSP
SRCINITRSTN pin
0
VSS3
P RSTN (
R RSTN(
)
RSTN
)
=CK, AD, DSP, SRC
Figure 14. (
)
*: CK, AD, DSP, SRC
P*RSTN()
R*RSTN()
L (0)
0
L (0)
1
H (1)
0
H (1)
1
*RSTN
0
1
1
1
8bit
()
()
()
8bit
(■
D0
SCLK
)
“0” (
)
“L”
P*RSTN
RQN
1
8 9
SCLK
16
D7
Command
SI()
D0
Data
*RSTN
Figure 15.
P, R
*RSTN
Figure 15
2)
INITRSTNAK7782
, ADC, DSP, SRC, PLL
INITRSTN pin= “L”
INITRSTN pin “L”
“H”
INITRSTN pin “L”
“H”
REF
CKM[2:0] pinXTI pin
(CKM mode 4, 5)
(CKM mode 0, 1, 2, 3)
BITCLKI pin
CKM[2:0] pinPLL
MS1337-J-00
2011/11
- 55-
[AK7782]
(
)
Pin
No.
1
12
21
22
23
24
25
Pin
Name
LFLT
XTO
LRCLKO
BITCLKO
SDOUT1
SDOUT2
SDOUT3
I/O
O
O
O
O
O
O
O
H
Hi-Z
L
L
L
L
L
26
27
28
SDOUT4
SDOUT5
CLKO1
O
O
O
L
L
L
Pin
No.
50
51
52
53
54
55
65
Pin
Name
SO
RDY
STO
SDOUTA1
SDOUT6
SDOUT7
SDA
I/O
O
O
O
O
O
O
IO
76
86
TESTO
VCOM
O
O
Hi-Z
H
H
L
L
L
L (I2CSEL=L)
Hi-Z (I2CSEL=H)
Hi-Z
L
3)
(INITRSTN pin= “H”) PCKRSTN pin= “L”
RCKRSTN= “0”
CKM mode 0, 1XTI
CKM mode 2, 3XTI, LRCLKI, BITCLKI
CKM mode 4, 5LRCLKI, BITCLKI
PLL
PLL
(18ms) DSPDSP
ADRSTN= “1” or DSPRSTN= “1”
AK7782
ADC DSP
PCKRSTN pin= “L”
PCKRSTN pin
RCKRSTN
“1” → “0”
RCKRSTN= “0”,
INITRSTN= “H”
CKM[2:0] pin
“H” →”L”
INITRSTN
PCKRSTN
SRESETN()
ICLK
(XTI or BITCLKI)
PLL
DSP
(18ms)
Figure 16. PCKRSTN ()
PCKRSTN=”L”
600ns(min)
RQN
SCLK
SI
D6h
00h
SRESETN()
CKRSTN(
C0h
00h
C0h
RCKRSTN=0
02h
D6h
18h
CKRSTN=1
)
PLL
18ms
&
DSP
Figure 17. RCKRSTN()
MS1337-J-00
2011/11
- 56-
[AK7782]
4)
(PCKRSTN pin= “H” or
DSP
(DSPRSTN bit = “0”)
PADRSTN (
RADRSTN(
RCKRSTN bit = “1”)ADC (ADRSTN bit = “0”)
)
)
ADRSTN
SRESETN
PDSPRSTN (
RDSPRSTN(
)
)
DSPRSTN
Figure 18. (
ADRSTN
0
0
1
1
DSPRSTN
0
1
0
1
)
SRESETN
0
1
1
1
)
DSPADC
DSP
DSP, ADC
ADC
(RUNADC
DSPSRC
ADC
LRCLKO, BITCLKO
ADRSTN bit, DSPRSTN bit
“1”
ADCDSP
SRC
ADC
130LRCLK(max) (2.75ms@fs=48kHz, 16.5ms@fs=8kHz)
(ADRSTN bit = “1” or DSPRSTN bit = “1”)
2
I
SLRCLKI,
BITCLKI
LRCLKI BITCLKILRCLKI
1/16fs
1/16fs
LRCLKI
LRCLKI, BITCLKI
LRCLKI, BITCLKI
DSP
LRCLKI
I2S
4LRCLK(max)
MS1337-J-00
2011/11
- 57-
[AK7782]
5)
(1)pin:
INITRSTN (pin)
PCKRSTN (pin)
PDSPRSTN (pin)
PADRSTN (pin)
RCKRSTN (ctreg)
RDSPRSTN (ctreg)
RADRSTN (ctreg)
SRESETN ()
REF
PLL
CLKO1 XTI
CLKO1 XTI
LRCLKO ()
()
BITCLKO ()
()
DSP
ADC
(2)pin:
INITRSTN (pin)
PCKRSTN (pin)
PDSPRSTN (pin)
PADRSTN (pin)
RCKRSTN (ctreg)
RDSPRSTN (ctreg)
RADRSTN (ctreg)
SRESETN ()
REF
PLL
CLKO1 XTI
CLKO1 XTI
LRCLKO ()
(
)
BITCLKO ()
()
DSP
ADC
(1)(2)
ctreg:
L
L
L
L
0
0
0
0
DSP
ADC
DSP+ADC
H
L
L
L
0
0
0
0
H
H
L
L
0
0
0
0
H
H
H
L
0
0
0
1
H
H
L
H
0
0
0
1
H
H
H
H
0
0
0
1
LRCLKI
LRCLKI
LRCLKI
LRCLKI
LRCLKI
BITCLKI
BITCLKI
BITCLKI
BITCLKI
BITCLKI
DSP
ADC
DSP+ADC
ctreg:
L
L
L
L
0
0
0
0
H
L
L
L
0
0
0
0
H
L
L
L
1
0
0
0
H
L
L
L
1
1
0
1
H
L
L
L
1
0
1
1
H
L
L
L
1
1
1
1
LRCLKI
LRCLKI
LRCLKI
LRCLKI
LRCLKI
BITCLKI
BITCLKI
BITCLKI
BITCLKI
BITCLKI
MS1337-J-00
2011/11
- 58-
[AK7782]
■
INITRSTN pin= “L”, PCKRSTN pin= “L”, PDSPRSTN pin= “L”, PADRSTN pin= “L”
INITRSTN pin= “L”(
Note 70)
INITRSTN pin= “H”
REF
PCKRSTN pin= “H”
PLL
(Note 71) PLL
(MCLK)
AK7782
PLL
Note 70.
Note 71.
PCKRSTN pin
“L” CONT00 D0 (RCKRSTN)
“1”
(CKM mode0, 1
XTI, CKM mode2, 3
LRCLKI, BITCLKI
(INITRSTN pin= “L”)
pin= “H” & RCKRSTN bit= “0”)
XTI, LRCLKI, BITCLKI, CKM mode 4, 5
(INITRSTN
AVDD
DVDD
DVDD18
INITRSTN
CKRSTN
SRESETN
XTI(CKM
BITCLKI(CKM
(
0-3)
4,5)
PLLCLK)
CLKO1
OFF
PLL
INITR STN
DSP
CKRST
(18ms)
C LKO1 (1 8ms m ax)
Figure 19.
MS1337-J-00
2011/11
- 59-
[AK7782]
■ RAM
DSPDRAM
DLRAM 0
(RAM
DSP7*LRCLK(max) +4096*MCLK (
3*LRCLK(max)+4096*MCLK
fs=48kHz
(7/48kHz)+(4096/122.88MHz)=179μsfs=8kHz (7/8kHz)+(4096/122.88MHz)=908
RAMRUN
DSP
RAMDSP
RAMRAM
)
RAM
)
μs
INITRSTN
PDSPRSTN
RAM
DSP (
()
)
RAM
DSP
Figure 20. RAM
■
SDIN1, SDIN2, SDIN3, SDIN4, SDIN5, SDIN6, SDIN7, SDOUT1, SDOUT2, SDOUT3,
SDOUT4, SDOUT5, SDOUT6, SDOUT7, SDOUTA1 pinLRCLKI, BITCLKI, LRCLKO, BITCLKO
2's
MSB
2
2
I
S(I
S
2
I
S
) BITCLKI64fs
SDIN2, SDIN3, SDIN4
(24bit),
24bit,
20bit,
16bit,
, 32bitSDIN1, SDIN5, SDIN6, SDIN7
(24bit),
SDIN2, SDIN3, SDIN4
SDIN1, SDIN5, SDIN6, SDIN7
SDIN1, SDIN5, SDIN6, SDIN7
ADC1, ADC2, ADCM, SRC1O, SRC2O
2
I
S
F24.4
SDOUT2, SDOUT3, SDOUT4
(24bit), 24bit,
20bit,
16bit,
,
32bit
SDOUT1, SDOUT5, SDOUT6, SDOUT7(24bit),
F24.4
SDOUT2, SDOUT3, SDOUT4
SDOUT1, SDOUT5,
SDOUT6, SDOUT7
ADCM
Lch, Rch
MS1337-J-00
F24.4
F24.4
2011/11
- 60-
[AK7782]
1)
DIFI2S bit= “0” (CONT00 D4)
Left ch
LRCLKO
Right ch
BITCLKO
31 30 29 28 27
SDIN1~7
DIF Mode 0
SDOUT1~7
DOF Mode 0
SDOUTA1
10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0
M 22 2120 19
2 1 L
M 22 21 20 19
2 1 L
M:MSB,L:LSB
M 22 2120 19
2 1 L
M 22 21 20 19
2 1 L
M:MSB,L:LSB
Figure 21. (CKM Mode 0, 1)
(24bit), BITCLK64fs
Left ch
LRCLKO
Right ch
BITCLKO
31 30
SDIN2~4
DIFD Mode 1
SDIN2~4
DIFD Mode 2
SDIN2~4
DIFD Mode 3
SDOUT2~4
DOFD Mode 1
SDOUT2~4
DOFD Mode 2
SDOUT2~4
DOFD Mode 3
23 22 21 20 19 18 17 16 15 14
1 0 31 30
23 22 21 20 19 18 17 16 15 14
1 0
Don’t care M 22 21 20 19 18 17 16 15 14
1 L Don’t care M 22 21 20 19 18 17 16 15 14
1 L
Don’t care
M 18 17 16 15 14
1 L Don’t care
1 L
Don’t care
M 14
M 18 17 16 15 14
1 L Don’t care
M:MSB,L:LSB
M 14
1 L
MSB
22 21 20 19 18 17 16 15 14
1 L
MSB
22 21 20 19 18 17 16 15 14
1 L
MSB
18 17 16 15 14
1 L
MSB
18 17 16 15 14
1 L
MSB
14
1 L
MSB
14
1 L
Figure 22. (CKM Mode 0, 1)
, BITCLK64fs
MS1337-J-00
2011/11
- 61-
[AK7782]
Left ch
LRCLKI
Right ch
BITCLKI
31 30 29 28 27
SDIN1~7
DIF Mode 0
SDOUT1~7
DOF Mode 0
SDOUTA1
LRCLKO
10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0
M 22 2120 19
2 1 L
M 22 21 20 19
2 1 L
M:MSB,L:LSB
M 22 2120 19
2 1 L
M 22 21 20 19
2 1 L
M:MSB,L:LSB
Left ch
Right ch
BITCLKO
Figure 23.
(CKM Mode 2~5) (24bit), BITCLK64fs
Left ch
LRCLKI
Right ch
BITCLKI
31 30
SDIN2~4
DIFD Mode 1
SDIN2~4
DIFD Mode 2
SDIN2~4
DIFD Mode 3
SDOUT2~4
DOFD Mode 1
SDOUT2~4
DOFD Mode 2
SDOUT2~4
DOFD Mode 3
23 22 21 20 19 18 17 16 15 14
1 0 31 30
23 22 21 20 19 18 17 16 15 14
1 0
Don’t care M 22 21 20 19 18 17 16 15 14
1 L Don’t care M 22 21 20 19 18 17 16 15 14
1 L
Don’t care
M 18 17 16 15 14
1 L Don’t care
M 18 17 16 15 14
1 L
Don’t care
M 14
1 L Don’t care
M 14
1 L
M:MSB,L:LSB
MSB
22 21 20 19 18 17 16 15 14
1 L
MSB
22 21 20 19 18 17 16 15 14
1 L
MSB
18 17 16 15 14
1 L
MSB
18 17 16 15 14
1 L
MSB
14
1 L
MSB
14
1 L
Left ch
LRCLKO
Right ch
BITCLKO
Figure 24.
(CKM Mode 2~5) , BITCLK64fs
MS1337-J-00
2011/11
- 62-
[AK7782]
Left ch
LRCLKO
Right ch
BITCLKO
31 30 29 28 27
SDIN1, 5~7
DIF Mode 1
SDIN2, 3, 4
DIF Mode 4
SDOUT1, 5~7
DOF Mode 1
SDOUT2, 3, 4
DOF Mode 4
10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0
M 22 2120 19
2 1 L S3S2S1S0
M 22 21 20 19
2 1 L S3 S2 S1 S0
M 22 2120 19
2 1 L S3S2S1S0
M 22 21 20 19
2 1 L S3 S2 S1 S0
M 22 2120 19
2 1 L S3S2S1S0
M 22 21 20 19
2 1 L S3 S2 S1 S0
M 22 2120 19
2 1 L S3S2S1S0
M 22 21 20 19
2 1 L S3 S2 S1 S0
Figure 25. (CKM Mode 0, 1)
(24bit), BITCLK64fs,
DIF7/6/5/1 Mode 1, DIFD Mode 4, DOF7/6/5/1 Mode 1, DOFD Mode 4
Left ch
LRCLKO
Right ch
BITCLKO
31 30 29 28 27
SDIN1, 5~7
DIF Mode 0
SDIN2, 3, 4
DIF Mode 5
SDOUT1, 5~7
DOF Mode 0
SDOUT2, 3, 4
DOF Mode 5
10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27
M 22 21 20 19
10 9 8 7 6 5 4 3 2 1 0
M 22 2120 19
2 1 L
M 30 2928 27
10 9 8 7 6 5 4 3 2 1 L M 30 2928 27
10 9 8 7 6 5 4 3 2 1 L
M 22 2120 19
2 1 L
2 1 L
M 30 2928 27
10 9 8 7 6 5 4 3 2 1 L M 30 2928 27
M 22 21 20 19
2 1 L
10 9 8 7 6 5 4 3 2 1 L
Figure 26. (CKM Mode 0, 1)
(24bit), BITCLK64fs,
DIF7/6/5/1 Mode 0, DIFD Mode 5, DOF7/6/5/1 Mode 0, DOFD Mode 5
MS1337-J-00
2011/11
- 63-
[AK7782]
Left ch
LRCLKI
Right ch
BITCLKI
31 30 29 28 27
SDIN1, 5~7
DIF Mode 1
SDIN2, 3, 4
DIF Mode 4
SDOUT1, 5~7
DOF Mode 1
SDOUT2, 3, 4
DOF Mode 4
10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0
M 22 2120 19
2 1 L S3S2S1S0
M 22 21 20 19
2 1 L S3 S2 S1 S0
M 22 2120 19
2 1 L S3S2S1S0
M 22 21 20 19
2 1 L S3 S2 S1 S0
M 22 2120 19
2 1 L S3S2S1S0
M 22 21 20 19
2 1 L S3 S2 S1 S0
M 22 2120 19
2 1 L S3S2S1S0
M 22 21 20 19
2 1 L S3 S2 S1 S0
Left ch
LRCLKO
Right ch
BITCLKO
Figure 27.
(CKM Mode 0, 1) (24bit), BITCLK64fs,
DIF7/6/5/1 Mode 1, DIFD Mode 4, DOF7/6/5/1 Mode 1, DOFD Mode 4
Left ch
LRCLKI
Right ch
BITCLKI
31 30 29 28 27
SDIN1, 5~7
DIF Mode 0
SDIN2, 3, 4
DIF Mode 5
SDOUT1, 5~7
DOF Mode 0
SDOUT2, 3, 4
DOF Mode 5
10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27
M 22 21 20 19
10 9 8 7 6 5 4 3 2 1 0
M 22 2120 19
2 1 L
M 30 2928 27
10 9 8 7 6 5 4 3 2 1 L M 30 2928 27
10 9 8 7 6 5 4 3 2 1 L
M 22 2120 19
2 1 L
2 1 L
M 30 2928 27
10 9 8 7 6 5 4 3 2 1 L M 30 2928 27
M 22 21 20 19
Left ch
LRCLKO
2 1 L
10 9 8 7 6 5 4 3 2 1 L
Right ch
BITCLKO
Figure 28.
(CKM Mode 0, 1) (24bit), BITCLK64fs,
DIF7/6/5/1 Mode 0, DIFD Mode 5, DOF7/6/5/1 Mode 0, DOFD Mode 5
MS1337-J-00
2011/11
- 64-
[AK7782]
2)I2S
DIFI2S bit= “1” (CONT00 D4)
Left ch
LRCLKO
Right ch
BITCLKO
31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0
SDIN1~7
M 22 21 20
3 2 1 L
M 22 21 20
3 2 1 L
SDOUT1~7
SDOUTA1
M 22 21 20
3 2 1 L
M 22 21 20
3 2 1 L
M:MSB,L:LSB
M:MSB,L:LSB
(24bit)
Figure 29. (CKM Mode 0~1)
Left ch
LRCLKI
Right ch
BITCLKI
31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0
SDIN1~7
M 22 21 20
3 2 1 L
M 22 21 20
3 2 1 L
SDOUT1~7
SDOUTA1
M 22 21 20
3 2 1 L
M 22 21 20
3 2 1 L
LRCLKO
Left ch
M:MSB,L:LSB
M:MSB,L:LSB
Right ch
BITCLKO
(24bit)
Figure 30.
(CKM Mode 2~5)
MS1337-J-00
2011/11
- 65-
[AK7782]
■
(I2CSEL pin= “L”)
1.
(8bit) +
MSB first
Bit
8
bit
R/W7bit
PRAM/CRAM/Register
Command
16 / 0
Address
PRAM/CRAM/OFREG16bit
0bit (
)
Data
Note 72. PRAM0
RQN
SCLK
SI
don’tcare
(L/H )
Command (8bit)
SO
Hi-Z
Address (16bit or 0bit )
d on’tcare
(L/H)
Data ( write )
Data ( read )
Low or Echo back
Hi-Z
RQN=HighSO
Hi-Z
2.
BIT7
BIT7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT6
BIT6
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
BIT5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
BIT5
BIT4
BIT4
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
BIT3~0
0100
0110
0100
0010
1000
0110
1100
1010
0000
0001
0110
1000
0111
1001
BIT3
BIT2
CRAM/OFRAM (RUN
CRAM2/OFRAM2 (RUN
CRAM
(DSP )
OFRAM
(DSP)
PRAM
(DSP)
CRAM2
(DSP )
OFRAM2
(DSP)
PRAM2
(DSP)
DSP1
DSP2
DSP1 @MICR
DSP1 @MIR2
DSP2 @MICR
DSP2 @MIR2
00~0F
10~16
CRC
0010
0000
MS1337-J-00
BIT1
BIT0
)
)
2011/11
- 66-
[AK7782]
3.
LSB
BIT[6:4]= “000” → “011”
BIT[6:4]= “100” → “111”
16bit
4.
RAM
80h~8Fh
16bit
A2h
A4h
B2h
B4h
B8h
F4h
16bit
16bit
16bit
16bit
16bit
90h~9Fh
16bit
ACh
A6h
BCh
B6h
BAh
F5h
16bit
16bit
16bit
16bit
16bit
10h~1Fh
16bit
AEh
ADh
BEh
BDh
BFh
F6h
C0h~CFh
D0h~D6h
F2h
16bit
16bit
16bit
16bit
16bit
16bit × n
16bit × n
16bit × n
40bit × n
8bit
16bit × n
16bit × n
16bit × n
40bit × n
8bit
16bit × n
16bit × n
16bit × n
40bit × n
8bit
8bit
8bit
16bit
CRAM/OFRAM
BIT0
RUNBIT3
(80h1
81h2
OFRAM RUN
CRAM RUN
OFRAM (DSP
)
CRAM(DSP)
PRAM(DSP)
DSP1 JX
CRAM2/OFRAM2 RUNBIT3
BIT0 (90h1
91h2
16)
OFRAM2 RUN
CRAM2 RUN
OFRAM2 (DSP
)
CRAM2(DSP
)
PRAM2(DSP
)
DSP2 JX
CRAM&CRAM2, OFRAM&OFRAM2 RUN
BIT3 BIT0 (10h
2
1Fh16)
OFRAM & OFRAM2 RUN
CRAM & CRAM2 RUN
OFRAM & OFRAM2 (DSP
CRAM & CRAM2
(DSP)
PRAM & PRAM2(DSP
)
DSP1 & DSP2 JX
00h~0Fh
10h~17h
CRC
MS1337-J-00
8Fh16)
9Fh
1
11h
)
2011/11
- 67-
[AK7782]
RAM
24h
32h
34h
38h
16bit
16bit
16bit
ALL0
16bit × n
16bit × n
16bit × n
40bit × n
70h
8bit
76h
32bit
78h
32bit
26h
3Ch
36h
3Ah
16bit
16bit
16bit
ALL0
16bit × n
16bit × n
16bit × n
40bit × n
71h
8bit
77h
32bit
79h
32bit
40h~4Fh
50h~56h
72h
60h
8bit
8bit
16bit
8bit
CRAM, OFRAMRUN
OFRAM(DSP
CRAM(DSP)
PRAM(DSP)
)
DSP1
DSP1 @MIR1
28bit
DSP1 @MIR2
28bit
4bitValidity0000
4bitValidity0000
CRAM2, OFRAM2RUN
OFRAM2(DSP
)
CRAM2(DSP
)
PRAM2(DSP
)
DSP2
DSP2 @MIR1
28bit
DSP2 @MIR2
28bit
00h~0Fh
10h~17h
CRC
MS1337-J-00
4bitValidity0000
4bitValidity0000
2011/11
- 68-
[AK7782]
5.
AK7782
SO
(1)
RQN
SI
COMMAND
SO
IN VALID
ADDRESS1
ADDRESS2
COMMAND
ADDRESS1
DATA1
don’ tcare
(L/H)
DATA2
ADDRESS2
DATA1
BIT15 8
BIT7
COMMAND
Hi-Z
IN VALID
ADDRESS1
COMMAND
SI8bitSO
Figure 31. 1
RQN
SI
0xB4
SO
IN VALID
0x00
COMMAND
0x00
ADDRESS1
Dummy 8bit
PRAM, PRAM240bitDummy
(CRAM, CRAM2, OFRAM, OFRAM216bit
ADDRESS2
0
DATA1
Dummy 8bit
DATA2
H i-Z
Dummy
)
Figure 32. 2
(2)
RQN
SI
COMMAND
SO
IN VALID
ADDRESS1
ADDRESS2
COMMAND
ADDRESS1
d on’tcare
(L/ H)
COMMAND
READ DATA
READ DATA
Hi-Z
IN VALID
ADDRESS1
COMMAND
READPRAM,
PRAM2
Figure 33.
MS1337-J-00
2011/11
- 69-
[AK7782]
6.
6-1. DSP
RAM(PRAM, PRAM2)
(1) COMMAND
(2) ADDRESS1
(3) ADDRESS2
(4) DATA1
(5) DATA2
(6) DATA3
(7) DATA4
(8) DATA5
(DSP)
B8h, BAh, BFh
0 0 0 0 0 A10 A9 A8
A7 ~ A0
0 0 0 0 D35 D34 D33 D32
D31~D24
D23~D16
D15~D8
D7~D0
(5byte)
RAM(CRAM, CRAM2)
(1) COMMAND
(2) ADDRESS1
(3) ADDRESS2
(4) DATA2
(5) DATA3
(DSP)
B4h, B6h, BDh
0 0 0 0 0 A10 A9 A8
A7~A0
D15~D8
D7~D0
(2byte)
RAM(OFRAM, OFRAM2)
(DSP
)
(1) COMMAND
B2h, BCh, BEh
(2) ADDRESS1
00000000
(3) ADDRESS2
0 0 A5 A4 A3 A2 A1 A0
(4) DATA1
0 0 0 D12 D11 D10 D9 D8
(5) DATA2
D7~D0
(2byte)
6-2. DSP RUN
(DSP
(1) COMMAND
(2) DATA
Note 73.
RUN
SI
C0h~CFh, D0h~D6h
D7~D0
RUN
)
(DSP
(1) COMMAND
(2) DATA
RUN)
SI
F4h, F5h, F6h
D7~D0
CRC (DSP
(1) COMMAND
(2) DATA
(3) DATA
RUN)
SI
F2h
D15~D8
D7~D0
MS1337-J-00
2011/11
- 70-
[AK7782]
6-3. RUN
RAM(CRAM, CRAM2, CRAM&CRAM2
)
OFRAM2
)
(RUN):
SI
(1) COMMAND
80h~8Fh (80h1
90h~9Fh (90h1
10h~1Fh (10h1
(2) ADDRESS1
0 0 0 0 0 A10 A9 A8
(3) ADDRESS2
A7~A0
(4) DATA1
D15~D8
(5) DATA2
D7~D0
(2byte)
Note 74. COMMAND
RAM(CRAM, CRAM2, CRAM & CRAM2
SI
(1) COMMAND
A4h, A6h, ADh
(2) ADDRESS1
00000000
(3) ADDRESS2
00000000
RAM(OFRAM, OFRAM2, OFRAM &
8Fh16)
9Fh16)
1Fh16)
)
RAM(OFRAM, OFRAM2, OFRAM & OFRAM2
SI
(1) COMMAND
A2h, ACh, AEh
(2) ADDRESS1
00000000
(3) ADDRESS2
00000000
Note 75. COMMAND
)
MS1337-J-00
2011/11
- 71-
[AK7782]
6-4. DSP
RAM(PRAM, PRAM2)
(1) COMMAND
(2) ADDRESS1
(3) ADDRESS2
(4) DATA1
(5) DATA2
(6) DATA3
(7) DATA4
(8) DATA5
(DSP)
SI
38h, 3Ah
0 0 0 0 0 A10 A9 A8
A7 ~ A0
SO
0 0 0 0 D35 D34 D33 D32
D31~D24
D23~D16
D15~D8
D7~D0
(5byte)
RAM(CRAM, CRAM2)
(1) COMMAND
(2) ADDRESS1
(3) ADDRESS2
(4) DATA1
(5) DATA2
(DSP)
SI
34h, 36h
0 0 0 0 0 A10 A9 A8
A7~A0
SO
D15~D8
D7~D0
(2byte)
RAM(OFRAM, OFRAM2)
(DSP
SI
(1) COMMAND
32h, 3Ch
(2) ADDRESS1
00000000
(3) ADDRESS2
0 0 A5 A4 A3 A2 A1 A0
(4) DATA1
(5) DATA2
(2byte)
)
SO
0 0 0 D12 D11 D10 D9 D8
D7~D0
MS1337-J-00
2011/11
- 72-
[AK7782]
6-5. DSP RUN
(DSP
RUN
SI
40h~4Fh, 50h~56h
(1) COMMAND
(2) DATA
CRC (DSP
(1) COMMAND
(2) DATA
(3) DATA
(1) COMMAND
(2) DATA
SO
D7~D0
(DSPRUN
(1) COMMAND
(2) DATA
)
)
SI
60h
SO
D7
1
RUN
SI
72h
D6
0
D5
0
8
D4
0
D3
0
D2
0
2
D1
1
D0
0
)
SO
D15~D8
D7~D0
(DSPRUN
SI
SO
70h, 71h
)
D7
D6
D5
D4
CRCERRN
WDTERRN
GPO0
GPO1
D3
0
D2
0
D1
0
D0
0
6-6. RUN
CRAM, CRAM2 / OFRAM, OFRAM2 (RUN
SI
(1) COMMAND
24h, 26h
(2) ADDRESS1
(3) ADDRESS2
(4) DATA1
(5) DATA2
MIR1/2 (RUN
(1) COMMAND
(2) DATA1
(3) DATA2
(4) DATA3
(5) DATA4
Note 76. flag“0”
)
SO
A15~A8
A8~A0
D15~D8
D7~D0
)
SI
76h (DSP1 MICR)
78h (DSP1 MIR2)
77h (DSP2 MICR)
79h (DSP2 MIR2)
SO
D27~D20
D19~D12
D11~D4
D3 D2 D1 D0 (flag) (flag) (flag) (flag)
flag bit “1”
MS1337-J-00
2011/11
- 73-
[AK7782]
7.
7-1. DSP
RAM
RAM(PRAM, PRAM2)
DSP
RAM(CRAM, CRAM2)RAM(OFRAM, OFRAM2)
RQN pin “H”
“L”PRAM
PDSPRSTN
RQN
SCLK
do n’tcare
(L/H)
SI
Command
Address
DATA
DATA
DATA
DATA
d on’tcare
(L /H)
Address DATA
d on’tcare
(L /H)
DATA
RDY = “H”
Figure 34.
RAM
PDSPRSTN
RQN
SCLK
do n’tcare
(L/H)
SI
Command
Address DATA
don’tcare
(L /H)
Command
RDY = “H”
Figure 35.
7-2. RUN
RAM
RAM
RAM(CRAM, CRAM2)RAM(OFRAM, OFRAM2)
1)
1~16(8bit)
(16bit),
2)
24h
26h(
0001h
)
3)
RUN(16bit all “0”)
RUN
Note 77.
RDY
“H”
MS1337-J-00
2011/11
- 74-
[AK7782]
RAM
RAM
RAM5
“10”
7
RAM
8
9
10
↓
11
↓
13
16
11
12
↓
13
↓
14
↓
15
↑
“13”
“12”
PDSPRSTN= “H”
RQN
DATA
SCLK
SI
4
CRAM,OFRAM Command 83h
CRAM2,OFRAM2 Command 93h
don’tcare
(L/H)
Command
RDY = “H”
Address
DATA
DATA
DATA
CRAM,OFRAM 80h(DATA
CRAM2,OFRAM2
1
90h(DATA
don’tcare
(L/H)
DATA
) ~ 8Fh(DATA
1
16
) ~ 9Fh(DATA
)
16
)
Figure 36. CRAM, OFAM
PDSPRSTN=H
RQN
SCLK
SI
don’tcare
(L/H)
24h, 26h
Address DATA
INVALID
SO
don’tcare
(L/H)
DATA
DATA
DATA
Hi-Z
RDY=H
Figure 37. CRAM, OFRAM
PDSPRSTN= “H”
RQN
SCLK
SI
don’tcare
(L/H)
RDY
00000000
Command
00000000
don’tcare
(L/H)
max 400ns
CRAM A4h, OFRAM A2h
CRAM2 A6h, OFRAM2 ACh
RDYLG (Note 78)
Note 78. RDYLG1
2LRCK
“L”
RDY
RDY
“L”
CHIP
RQN pin
Figure 38. CRAM, OFRAM
MS1337-J-00
2011/11
- 75-
[AK7782]
7-3.
(DSP
(1) COMMAND
(2) DATA
RUN)
F4h, F5h, F6h
D7~D0
DSP
LRCLK (LRCLKI, LRCLKO)
RDY pin
“L”
8 bit
JX0, JX1, JX2
“1”1
INITRSTN pin = “L”
RUN
RQN pin
RDY pin “H”
11bitIFCON
IFCON
00hDSP
(F4h: DSP1, F5h: DSP2, F6h: DSP1/2)
7
■
IFCON
6
■
5
■
4
■
↑
3
■
2
■
1
■
0
■
“1”
16
↓
9
IFCON
PDSPRSTN
SCLK
SI
don’tcare
(L/H)
F4h
D7D0
don’tcare
(L/H)
Lch
RQN
Rch
LRCLK
RDY
Figure 39. (DSP, DSP1
JX
)
PDSPRSTN = “H”
SCLK
SI
don’tcare
(L/H)
F4h
D7 …. D0
don’tcare
(L/H)
RQN
L ch
R ch
LRCLK
RDY
Figure 40. (RUN
, DSP1
MS1337-J-00
JX)
2011/11
- 76-
[AK7782]
7-4. DSP
RAM
RAM(PRAM, PRAM2)
DSP
SCLK
SO
SCLK
RAM(CRAM, CRAM2)RAM(OFREM, OFRAM2)
PRAM0h
(SI
Don’t care
)
PDSPRSTN
RQN
SCLK
don’tcare
(L/H)
SI
SO
Command
don ’tcare
(L/H )
Address
DATA
HI-Z
DATA
DATA
DATA
DATA
HI-Z
RDY
Figure 41.
7-5. DSP RUN
CRC
RUN
SO(SI
DSP
SCLK
Don’t care
)
PDSPRSTN
RQN
SCLK
SI
don’tcare
(L/H)
SO
Command
Address
don ’tcare
(L/H )
DATA
HI-Z
HI-Z
RDY
Figure 42. DSP
PDSPRSTN=H
RQN
SCLK
SI
SO
don’tcare
(L/H)
Command
Address
don ’tcare
(L/H )
DATA
HI-Z
HI-Z
RDY
Figure 43. DSP RUN
MS1337-J-00
2011/11
- 77-
[AK7782]
■ I2C
(I2CSEL pin= “H”)
I2C
AK7782
I2CSEL pin= “H”
(max: 400kHz)
I2C
Hs
(max: 3.4MHz)
1.
IC·
1
·
IC
IC
IC
READ
WRITE
·
1-1.
SDA
“H”
“L”
SCL
“L”“H”SDA
SCL“H”
SDA
“L”SCL
·
·
SCL
SDA
DATA LINE
STABLE:
DATA VALID
CHANGE
OF DATA
ALLOWED
Figure 44.
MS1337-J-00
2011/11
- 78-
[AK7782]
1-2.
(Start Condition)
SCL
·
“H”SDA
“H”
“L”
(Stop Condition)
·
SCL
“H”SDA
“L”
“H”
··
SCL
SDA
START CONDITION
STOP CONDITION
Figure 45.
1-3.
(Repeated Start Condition)
SCL
SDA
START CONDITION
Repeated Start CONDITION
Figure 46.
1-4.
IC
IC
AK7782
·
(Acknowledge)
1
SDA
SDA
(HIGH
)
“L”
·
WRITE
SDA
· AK7782
READ
SDA
AK7782
AK7782 (Not Acknowledge)
MS1337-J-00
2011/11
- 79-
[AK7782]
Clock pulse
for acknowledge
SCL FROM
MASTER
1
8
9
DATA
OUTPUT BY
TRANSMITTER
DATA
OUTPUT BY
RECEIVER
not acknowledge
acknowledge
START
CONDITION
Figure 47. (acknowledge)
1-5.
IC
IC
“00110”
·
IC
8
READ
R/W bit=“0”
7
5
2IC
CAD1, CAD0 pin
(
)
R/W bitR/W bit= “1”
WRITE
Note 79. R/W bit= “0”
R/W
bit= “1”
0
0
1
1
0
CAD1
CAD0
R/W
(CAD1, CAD0)
Figure 48.
1-6.
I
8
I
2
CAK7782
2
C
MS1337-J-00
MSB8
2011/11
- 80-
[AK7782]
A1B2C3(hex)
24bit
2
IC
(1)I2C
(1)
A1
B2
C3
A1
B2
A
24BIT
8BIT
C3
A
8BIT
8BIT
A …Acknowledge
Figure 49.
Note 80.
Write
Write
Read
Read
2. Write
AK7782Write
(
Figure 50*1)
Write
Table 1. WriteWrite
S
SLAD
W
A
Cmd
A
Data
A
Stp
repeat N times (*1)
Figure 50. Write
MS1337-J-00
2011/11
- 81-
[AK7782]
80h~8Fh
2byte
2byte × n
A2h
A4h
B2h
B4h
B8h
2byte
2byte
2byte
2byte
2byte
2byte × n
2byte × n
5byte × n
F4h
90h~9Fh
2byte
1byte
2byte × n
ACh
A6h
BCh
B6h
BAh
F5h
10h~1Fh
AEh
ADh
BEh
BDh
BFh
2byte
2byte
2byte
2byte
2byte
2byte × n
2byte × n
5byte × n
2byte
1byte
2byte × n
2byte
2byte
2byte
2byte
2byte
F6h
C0h~CFh
D0h~D6h
F2h
Note 81. RAM
2byte × n
2byte × n
5byte × n
1byte
1byte
1byte
1byte
CRAM / OFRAM RUN
BIT3~BIT0 (80h
16)
OFRAM RUN
CRAM RUN
OFRAM (DSP
)
CRAM(DSP)
PRAM(DSP)
DSP1 JX
CRAM2 / OFRAM2
BIT3~BIT0 (90h
16)
OFRAM2 RUN
CRAM2 RUN
OFRAM2 (DSP
CRAM2(DSP
PRAM2(DSP
1
81h
2
8Fh
1
91h
2
9Fh
RUN
)
)
)
DSP2 JX
CRAM&CRAM2 / OFRAM&OFRAM2 RUN
BIT3~BIT0
(10h
11h2
1Fh16)
OFRAM & OFRAM2 RUN
CRAM & CRAM2 RUN
OFRAM & OFRAM2 (DSP
CRAM & CRAM2
(DSP)
PRAM & PRAM2(DSP
)
DSP1 & DSP2 JX
00h~0Fh
(RUN
10h~16h
CRC
1
)
)
Table 1. WriteWrite
MS1337-J-00
2011/11
- 82-
[AK7782]
3. Read
AK7782Read
Read
Figure 51(*2)
)
(
Figure 51
(*3)
Read
AK7782
Read
Table 2. Read
S
SLAD
W A
Cmd
A
Data
A
rS
SLAD
Repeat N times (*2)
Read
R A
Data
A
Data
Na Stp
Repeat N-1 times (*3)
Figure 51. Read
24h
32h
34h
38h
70h
76h
2byte
2byte
2byte
78h
26h
3Ch
36h
3Ah
71h
77h
79h
40h~4Fh
50h~56h
60h
72h
Note 82.
2byte
2byte
2byte
5byte
1byte
4byte
n
n
n
n
4byte
2byte
2byte
2byte
2byte
2byte
2byte
5byte
1byte
4byte
n
n
n
n
4byte
1byte
1byte
1byte
2byte
CRAM/OFRAM
OFRAM(DSP
)
CRAM(DSP)
PRAM(DSP)
DSP1
DSP1 @MIR1
28bit
4bitValidity
DSP1 @MIR2
28bit
4bitValidity
CRAM2/OFRAM2 (RUN
OFRAM2(DSP
)
CRAM2(DSP
)
PRAM2(DSP
)
DSP2
DSP2 @MIR1
28bit
4bitValidity
DSP2 @MIR2
28bit
4bitValidity
00h~0Fh
10h~16h
(RUN)
0000
0000
)
0000
0000
CRC
RAM
Note 83.
Table 2. ReadRead
MS1337-J-00
2011/11
- 83-
[AK7782]
4.
4-1. RDY pin
Low
AK7782RDY pin
RDY pinHigh
LowRDY pin
Low
RDY pin
Low
Figure 52. RDY pin
RDY= “L”
RDY
…
Data
RDY= “L”
A
Stp
S
SLAD
W Na …
S
SLAD
W Na …
RDY= “H”
S
SLAD
W
A
…
RDY
Figure 52. RDY pin
MS1337-J-00
2011/11
- 84-
[AK7782]
4-2. Read
Read
AK7782Read
AK7782
Read
Read
Read
RDY pin
“L” “H”(
Note 84)
Note 84.
I2C
S
SLAD
W Na
Cmd
Na
xxx
Na
rS
SLAD
R Na
Read
N
RDY
Read RDY
“H”
Figure 53. Read
MS1337-J-00
2011/11
- 85-
[AK7782]
I2C
I2C
(1) Hs
(max: 3.4MHz)
(max: 400kHz)
(2)
(3)
Note 85. I2C BUS(I2CSEL pin= “H”)
SDA pin , SCL pin
SDA, SCL pin DVDD
ONAK7782
DVDD
OFF
Note 86. I2C
SLAD
…SlaveAddress (7 bits)
Cmd
…Command Code (8 bits)
S
…StartCondition
rS
…Repeated StartCondition
Stp
…StopCondition
W
…
R/W
Write(=0)
Write (1 bit)
R
…
R/W
Read(=1)
Read (1 bit)
A
…Acknowledge (1 bit)
Na
…NotAcknowledge (1 bit)
(Gray)
(White)
…
AK7782
MS1337-J-00
2011/11
- 86-
[AK7782]
■ ADC
1) ADC
ADCDC
(HPF)
1Hz(fs=48kHz)
(fs)
2) ADCM
ADCM
RQN
RQN
HPF
(fs)
96kHz
1.86Hz
48kHz
0.93Hz
44.1kHz
0.86Hz
32kHz
0.62Hz
8kHz
0.16Hz
(VOL)
2LRCLK
2LRCLK
VOL mode VOL[5] VOL[4] VOL[3] VOL[2] VOL[1] VOL[0] Volume (dB)
00
0
0
0
0
0
0
0
(default)
01
0
0
0
0
0
1
-2
03
0
0
0
0
1
1
-4
04
0
0
0
1
0
0
-6
05
0
0
0
1
0
1
-8
07
0
0
0
1
1
1
-10
08
0
0
1
0
0
0
-12
09
0
0
1
0
0
1
-14
0B
0
0
1
0
1
1
-16
0C
0
0
1
1
0
0
-18
0D
0
0
1
1
0
1
-20
0F
0
0
1
1
1
1
-22
10
0
1
0
0
0
0
-24
11
0
1
0
0
0
1
-26
13
0
1
0
0
1
1
-28
14
0
1
0
1
0
0
-30
15
0
1
0
1
0
1
-32
17
0
1
0
1
1
1
-34
18
0
1
1
0
0
0
-36
19
0
1
1
0
0
1
-38
1B
0
1
1
0
1
1
-40
1C
0
1
1
1
0
0
-42
1D
0
1
1
1
0
1
-44
1F
0
1
1
1
1
1
-46
20
1
0
0
0
0
0
-48
21
1
0
0
0
0
1
-50
23
1
0
0
0
1
1
-52
24
1
0
0
1
0
0
-54
25
1
0
0
1
0
1
-56
27
1
0
0
1
1
1
-58
28
1
0
1
0
0
0
-60
3C-3F
1
1
1
1
-∞
MS1337-J-00
2011/11
- 87-
[AK7782]
3) ADCM MUX
ADCM
DSP
MSEL[1:0]
RQN
4LRCLK
MUX Mode
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
DSP
MUX
DSP1 SDOUT1, DSP1 SDOUT5, DSP2 SDOUT1, DSP2 SDOUT5
MUX[1:0] Lch/Rch
2LRCLK
DATA 00000h
MUX
MSEL[1:0]
00
00
00
00
01
01
01
01
10
10
10
10
11
11
11
11
MUX[1:0]
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
L ch
DSP1 SDOUT1 Lch
DSP1 SDOUT1 Lch
ADCM
ADCM
DSP1 SDOUT5 Lch
DSP1 SDOUT5 Lch
ADCM
ADCM
DSP2 SDOUT1 Lch
DSP2 SDOUT1 Lch
ADCM
ADCM
DSP2 SDOUT5 Lch
DSP2 SDOUT5 Lch
ADCM
ADCM
Rch
DSP1 SDOUT1 Rch
ADCM
DSP1 SDOUT1 Rch
ADCM
DSP1 SDOUT5 Rch
ADCM
DSP1 SDOUT5 Rch
ADCM
DSP2 SDOUT1 Rch
ADCM
DSP2 SDOUT1 Rch
ADCM
DSP2 SDOUT5 Rch
ADCM
DSP2 SDOUT5 Rch
ADCM
4) ADCM VOL + MUX
ADCM
VOL+MUXSDOUT1pin, SDOUT2pin, SDOUTA1pin
1Ts(1/fs)DSP1 SDOUT1, DSP1 SDOUT5, DSP2 SDOUT1, DSP2 SDOUT5
SDOUT1pin, SDOUT2pin, SDOUTA1pin
1Ts(1/fs)MUX
SDOUT1pin, SDOUT2pin, SDOUTA1 pin
SDOUT pin
DSP SDOUT
1Ts(1/fs)
MS1337-J-00
MUX
2011/11
- 88-
[AK7782]
■ SRC
1)
(SRC)7.35kHz~96kHz
(FSI)
(FSO/FSI)
(I) (0.98
FSO
96kHz
96kHz
96kHz
96kHz
88.2kHz
88.2kHz
88.2kHz
48kHz
48kHz
48kHz
48kHz
48kHz
48kHz
48kHz
44.1kHz
44.1kHz
44.1kHz
44.1kHz
44.1kHz
44.1kHz
7.35kHz~96kHz(FSO)
FSO/FSI = 0.167~6
FSO/FSI 6.00)
FSI
96kHz
88.2kHz
48kHz
44.1kHz
88.2kHz
48kHz
44.1kHz
48kHz
44.1kHz
32kHz
24kHz
16kHz
12kHz
8kHz
44.1kHz
32kHz
24kHz
16kHz
12kHz
8kHz
FSO/FSI
1.00
1.09
2.00
2.18
1.00
1.84
2.00
1.00
1.09
1.50
2.00
3.00
4.00
6.00
1.00
1.38
1.84
2.76
3.68
5.51
(II) (0.167FSO/FSI
(FSO/FSI)
FSO
FSI
FSO/FSI
44.1kHz 48kHz
0.92
48kHz 88.2kHz
0.54
48kHz
96kHz
0.50
44.1kHz 88.2kHz
0.50
16kHz
32kHz
0.50
8kHz
16kHz
0.50
44.1kHz 96kHz
0.46
8kHz
32kHz
0.25
8kHz
48kHz
0.167
8kHz
44.1KHz
0.181
Pass Band
44.00kHz
40.42kHz
22.00kHz
20.21kHz
40.42kHz
22.00kHz
20.21kHz
22.00kHz
20.21kHz
14.67kHz
11.00kHz
7.33kHz
5.50kHz
3.67kHz
20.21kHz
14.67kHz
11.00kHz
7.33kHz
5.50kHz
3.67kHz
Stop Band
52.00kHz
47.78kHz
26.00kHz
23.89kHz
47.78kHz
26.00kHz
23.89kHz
26.00kHz
23.89kHz
17.33kHz
13.00kHz
8.67kHz
6.50kHz
4.33kHz
23.89kHz
17.33kHz
13.00kHz
8.67kHz
6.50kHz
4.33kHz
0.99)
Pass Band
20.00kHz
19.25kHz
20.90kHz
19.20kHz
6.97kHz
2.48kHz
18.70kHz
2.93kHz
4.40kHz
4.04kHz
0.92, 0.54, 0.50, 0.46, 0.25, 0.181, 0.1677
Stop Band
24.10kHz
26.23kHz
27.00kHz
24.81kHz
9.00kHz
4.50kHz
25.00kHz
3.98kHz
6.50kHz
5.97kHz
MS1337-J-00
2011/11
- 89-
[AK7782]
SRC
(I)
SRC1(SRC1I)
SDIN1pinSRC2
P2SDOUT1 (Figure 1)
SRC(CONT13, CONT14)
(SRC2I)
SDIN5 pin, SDIN1 pin, P1SDOUT1,
2'sMSB
CONT13, CONT14
1. D7: BIEDGE SRC BICK
0: SRCLRCKI
tBCLK
SF
SRCLRCKI
SRCBICKI
63 62 61 60 59
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0
1: SRCLRCKI
tBCLK
SF
SRCLRCKI
SRCBICKI
63 62 61 60 59
2.
3.
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
D6, D5, D4: IDIF[2:0] SRC
fsi: SRC
IDIF Mode
IDIF[2]
IDIF[1]
0
0
0
1
0
0
2
0
1
3
0
1
4
1
0
5
1
0
6
1
1
IDIF[0]
0
1
0
1
0
1
0
7
1
1
1
D3, D2: BIFS[1:0] SRCBICKI
BIFS Mode
BIFS[1]
BIFS[0]
0
0
0
1
0
1
2
1
0
3
1
1
Note 87. IDIF mode 6, 7
16bit
20bit
24/20bit
I2S24/16bit
24bit
N/A
PCM
SHORT(24bit)
PCM LONG(24bit)
10 9 8 7 6 5 4 3 2 1 0
SRC BICK
32fsi
40fsi
48fsi
48fsi or 32fsi
48fsi
BIFS[1:0]
BIFS[1:0]
SRCBICKI
32fsi
64fsi
128fsi
48fsi
MS1337-J-00
2011/11
- 90-
[AK7782]
Left ch
SRCLRCKI
Right
ch
SRCBICKI
31 30
SRC1I,SRC2I
IDIF
4
SRC1I,SRC2I
IDIF
1
SRC1I,SRC2I
IDIF
0
23 22 21 20 19 18 17 16 15 14
1 0 31 30
23 22 21 20 19 18 17 16 15 14
1 0
Don’t care M 22 21 20 19 18 17 16 15 14
1 L Don’t care M 22 21 20 19 18 17 16 15 14
1 L
Don’t care
M 18 17 16 15 14
1 L Don’t care
M 18 17 16 15 14
1 L
Don’t care
M 14
1 L Don’t care
M 14
1 L
M:MSB,L:LSB
Figure 54. IDIF Mode 0, 1, 4 @BIEDGE=0, SRCBICKI 64fs
Left
SRCLRCKI
ch
Right
ch
SRCBICKI
SRC1I,SRC2I
IDIF
2
31 30 29 28 27
10 9 8 7 6 5 4 3 2 1
M 22 2120 19
2 1 L
0 31 30 29 28 27
M 22 21 20 19
10 9 8 7 6 5 4 3 2 1 0
2 1 L
M:MSB,L:LSB
Figure 55. IDIF Mode 2 @BIEDGE=0, SRCBICKI 64fs
Left
SRCLRCKI
ch
Right
ch
SRCBICKI
SRC1I,SRC2I
IDIF
2
23 22 21 20 19 18 17 16 23 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0
M 22 21 20 19 18 17 16 7 6 5 4 3 2 1 L M 22 21 20 19 18 17 16 7 6 5 4 3 2 1 L
M:MSB
L:LSB
Figure 56. IDIF Mode 2 @BIEDGE=0, SRCBICKI 48fs
Left ch
SRCLRCKI
Right
ch
SRCBICKI
SRC1I,SRC2I
IDIF
3
31 30 29 28 27
M 22 21 20
10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27
3 2 1 L
M 22 21 20
10 9 8 7 6 5 4 3 2 1 0
3 2 1 L
M:MSB,L:LSB
Figure 57. IDIF Mode 3 @BIEDGE=0, SRCBICI 64fs
SRCLRCKI
tBCLK
SF
SRCBICKI
SRC1I,SRC2I
IDIF
6
63 62 61 60 59
M 22 21 20 19
tBCLK
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
2 1 L L ch
M 22 21 20 19
10 9 8 7 6 5 4 3 2 1 0
2 1 L
R ch
32
Figure 58. IDIF Mode 6 @BIEDGE=1, BIFS[1:0]=1h
MS1337-J-00
2011/11
- 91-
[AK7782]
tBCLK
SF
SRCLRCKI
SRCBICKI
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRC1I,SRC2I
IDIF
6
M 14 13 12 11 10 9 8 7 6 5 4 3 2 1 L M 14 13 12 11 10 9 8 7 6 5 4 3 2 1 L
tBCLK
16
Lch
M:MSB
L:LSB
R ch
Figure 59. IDIF Mode 6 @BIEDGE=1, BIFS[1:0]=0h
1
tBCLK
60
LF
SRCLRCKI
SRCBICKI
SRC1I,SRC2I
IDIF
7
63 62 61 60 59
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
M 22 21 20 19
2 1 L
L ch
tBCLK
M 22 21 20 19
10 9 8 7 6 5 4 3 2 1 0
2 1 L
M:MSB,L:LSB
R ch
tBCLK
32
Figure 60. IDIF Mode 7 @BIEDGE=1, BIFS[1:0]=1h
LF
1
tBCLK
28
tBCLK
SRCLRCKI
SRCBICKI
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRIN1-3
IDIF
7
M:MSB
M 14 13 12 11 10 9 8 7 6 5 4 3 2 1 L M 14 13 12 11 10 9 8 7 6 5 4 3 2 1 L L:LSB
L ch
R ch
tBCLK
16
Figure 61. IDIF Mode 7 @BIEDGE=1, BIFS[1:0]=0h
MS1337-J-00
2011/11
- 92-
[AK7782]
(II)
SRC2's
MSB
BITCLKOCONT00 DIFI2S(D4) bit = “1”
I2S
SRC
DSPDSP
24bitLRCLKO,
Left ch
LRCKO
Right
ch
BICKO
31 30 29 28 27
SRC1O,SRC2O
M 22 2120 19
10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27
2 1 L
M 22 21 20 19
10 9 8 7 6 5 4 3 2 1 0
2 1 L
M:MSB,L:LSB
Figure 62. CONT00 DIFI2S (D4) bit= “0”
Left ch
LRCKO
Right
ch
BICKO
31 30 29 28 27
SRC1O,SRC2O
M 22 21 20
10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27
3 2 1 L
M 22 21 20
10 9 8 7 6 5 4 3 2 1 0
3 2 1 L
M:MSB,L:LSB
Figure 63. CONT00 DIFI2S (D4) bit= “1”
MS1337-J-00
2011/11
- 93-
[AK7782]
2
Manual Mode
PSRCSMUTE pin
“H”SRC1, SRC2
1024LRCLKO
PSRCSMUTE pin“L” ∞
1024LRCLKO
-∞
∞(“0”)
1024LRCLKO 0dB
0dB
RSRC1SMUTE bit, RSRC2SMUTE bit
SRCSMUTE
(PSRCSMUTE pin)
(RSRC*SMUTE bit)
0dB
Attenuation Level
at SRCOUT
-∞dB
(2)
(1)
(1)
Figure 64.
−∞
1024LRCLKO(1024/fso)
1024LRCLKO0dB
Manual Mode
(“0”)
Semi-Auto Mode
SRC1SEMIAUTO bit,
SRC2SEMIAUTO bit1
SRC
(SRCRSTN bit= “0”→ “1” PSRCRSTN pin = “L”
→ “H”)
50ms200ms
(@FSO=44.1kHz) SRC
PSRCSMUTE pin “H”
RSRC*SMUTE bit “1”
AUTOSEL(SRC1AUTOSEL bit, SRC2AUTOSEL bit),
FSO
Period
2205/fso×1
8820/fso×1
AUTOSEL
0
1
P S R C R S T N pin
R S R C R S T N b it
FSO=44.1kHz
50ms
200ms
FSO=48kHz
46ms
184ms
FSO=88.2kHz
25ms
100ms
FSO=96kHz
23ms
92ms
“L ” or “0 ”
P S R C S M U T E p in
R S R C 1S M U T E b it
R S R C 2S M U T E b it
D on ’t C ar e
“L ” o r “0 ”
(1 )
0d B
A tte n u ation
220 5/fso
-∞
(2 )
GD
SRCO
(S R C 1 O , S R C 2O )
1024LRCKO(1024/fso)
(GD)
Figure 65.
0dB
Semi-Auto
MS1337-J-00
2011/11
- 94-
[AK7782]
3
SRC
SRC1, SRC2PSRCRSTN pin= “L” SRC
PSRCRSTN pin= “L”
SRCOUT
“L”
PSRCRSTN pin= “L”
50ms
SRC
Case 1
External clocks
(Input port)
Don’t care
Input Clocks 1
Input Clocks 2
Don’t care
SRCnI (n=1, 2)
Don’t care
Input Data 1
Input Data 2
Don’t care
LRCKO
BICKO
(Output port)
Don’t care
Output Clocks 1
Output Clocks 2
Don’t care
SRCRST
< 50ms
(Internal state) Power-down
SRCnO (n=1, 2)
< 50ms
Normal
operation
PLL lock &
fs detection
“0” data
Normal data
PD
PLL lock &
fs detection
“0” data
Normal
operation
Power-down
Normal data
“0” data
SRCUNLOCK
Figure 66. 1
Case 2
External clocks
(Input port)
(No Clock)
SRCnI (n=1, 2)
External clocks
(Output port)
Input Clocks
Don’t care
(Don’t care)
Input Data
Don’t care
(Don’t care)
Output Clocks
Don’t care
SRCRST
(Internal state) Power-down
SRCnO (n=1, 2)
< 50ms
PLL Unlock
“0” data
PLL lock &
fs detection
Normal
operation
Power-down
Normal data
“0” data
SRCUNLOCK
Figure 67. 2
MS1337-J-00
2011/11
- 95-
[AK7782]
4
SRC
50 ms
SRC
Figure 68.
clocks
(input or output)
state 1
(unknown)
SRCRST
< 50ms(SETSRC=”L”)
(interlal state)
SRCnO (n=1, 2)
normal operation
Power
down
PLL locktime
& fs detection
normal operation
Note 88
normal data
SRCSMUTE
(Note89,recommended)
Att.Level
state 2
normal data
1024/fso
1024/fso
0dB
-∞dB
Figure 68.
Note 88.
SRC(
GD
SRCI “0” “0”
Note 89. Note 88SRCSMUTE (SRC)
p54 “CONT16: D7, D6” )
5
p55 “”
)
(SRC
UNLOCK
SRC1LOCKE, SRC2LOCKE
SRC RatioSTO pin
STO pin
“L”SRC
SRCLRCK96kHz STO pin
STO pin
“L” SRC
“L”
1 SRC
STO pin
“H”
(SRCRSTN bit= “0” )
Ratio
“L”
“L”
MS1337-J-00
2011/11
- 96-
[AK7782]
1)
Digital +3.3V
0.1μ
0.1μ
0.1μ
0.1μ
0.1μ
0.1μ
10μ
9
CLOCK
CONTROL
15,16,17
Rd
12
20
29
49
DVDD
56
69
I2CSEL
6
SDA
CKM[2:0]
STO
51
50
RQN
44
SI
45
SCLK
46
INITRSTN
40
PCKRSTN
41
PADRSTN
42
PDSPRSTN
43
AK7782
XTI
37
LRCLKI
36
BITCLKI
28
CLKO1
22
BITCLKO
21
LRCLKO
CLOCK
61
PSRCRSTN
TESTI1,2
NC
JX0
JUMP
NC
Analog Lch+
92
AINL+
Analog Lch-
91
AINL-
Analog Rch+
90
AINR+
89
AINR-
Analog RchAnalog Lch
83,81,79,94,96,98,100
Analog Rch
82,80,78,93,95,97,99
77
Analog Mono
C
10μ
R
PSRCSMUTE
SRCLRCK
AINR2
SRCBICK
LFLT
73
AVDD
I/F
RESET
CONTROL
66
4,72
76
75
6
7
SRC
71
64
63
AINR8
AINM
1
3
SDIN1
SDIN2 7
SDOUTA1
SDOUT1
7
62
32-35,59,60
53
23-27,54,55
Audio
I/F
VCOM
AVDD
86
0.1μ
10μ
0.1μ
84
10μ
SRC2BICK
Micom
0.1μ
Analog +3.3V
10μ
SRC2LRCK
AINL2 AINL8
65
52
SO
CL
11
“L”
RDY
XTO
CL
5
0.1μ
85
10,13,19,30,39,48,57,68
VSS1
AVDD
VREFL
VREFH
VSS2
VSS3
14
2,74,88
87
8,70
DVDD18 7
18
31
38
47
58
67
Digital +1.8V
0.1μ
0.1μ
0.1μ
0.1μ
0.1μ
0.1μ
0.1μ
10μ
Figure 69. I2CSEL pin= “L”,
MS1337-J-00
2011/11
- 97-
[AK7782]
Digital +3.3V
0.1μ
0.1μ
0.1μ
0.1μ
0.1μ
0.1μ
10μ
9
CLOCK
CONTROL
15,16,17
Rd
12
20
29
49
DVDD
56
6
69
I2CSEL
STO
CKM[2:0]
51
SO
SDA
50
65
CAD1
44
CAD0
45
SCL
46
INITRSTN
40
PCKRSTN
41
PADRSTN
42
CL
11
AK7782
XTI
37
LRCLKI
36
BITCLKI
28
CLKO1
22
BITCLKO
21
LRCLKO
CLOCK
61
PDSPRSTN
PSRCRSTN
TESTI1,2
JX0
JUMP
Analog Lch+
92
AINL+
Analog Lch-
91
AINL-
Analog Rch+
90
AINR+
89
AINR-
Analog RchAnalog Lch
83,81,79,94,96,98,100
Analog Rch
82,80,78,93,95,97,99
77
Analog Mono
C
10μ
R
73
AVDD
CONTROL
6
7
SRC
71
64
63
AINR8
AINM
LFLT
3
SDIN1
SDIN2
7
SDOUTA1
SDOUT1
7
62
32-35,59,60
53
23-27,54,55
Audio
I/F
VCOM
AVDD
86
0.1μ
10μ
0.1μ
84
10μ
SRCBICK
RESET
0.1μ
Analog +3.3V
10μ
AINR2
1
75
SRCLRCK
I/F
4,72
NC
PSRCSMUTE
Micom
43
76
SRC2BICK
I2C
66
NC
SRC2LRCK
AINL2 AINL8
“H”
RDY
XTO
CL
5
52
0.1μ
85
10,13,19,30,39,48,57,68
VSS1
AVDD
VREFL
VREFH
VSS2
VSS3
14
2,74,88
87
8,70
DVDD18 7
18
31
38
47
58
67
Digital +1.8V
0.1μ
0.1μ
0.1μ
0.1μ
0.1μ
0.1μ
0.1μ
10μ
Figure 70. I2CSEL pin= “H”,
MS1337-J-00
2011/11
- 98-
[AK7782]
2)
2-1)
AK7782
AVDD
AVDDDVDD, DVDD18
AK7782
2-2)
VREFH pinVREFL pin VREFH
AVDD
VREFL VSS1
0.1μFVSS1
VREFH pin
pinVREFL pin
VCOM pin
AK7782
VCOM pin10μ
0.1μFVSS1
VCOM pin
VREFH pin
10μF
VREFH
VCOM pin
F
2-3)
±FS=± (VREFH-VR
EFL)×2.0/3.3FS=(VREFH-VREFL)×2.0/3.3
VREFH=3.3V
VREFL=0.0V pin±2.00Vpp(typ)
2.00Vpp(typ)
2’s
AK7782fs=48kHz
3.072MHz
3.042MHz
AK7782
AAF
3.042MHz3.072MHz
3.072MHz
D/A
ADC
AK7782+3.3V(typ)
10mA
30kHz
ADC
AVDD+0.3V
VSS1-0.3V
IC
±15V
pin
10k
Signal
22μ
+
10k
10k
68p
+
+12V
10k
2.0Vpp
68p
+
+
LME49720MA
AIN+
2.2μ
+
2.2μ
AIN2.0Vpp
Figure 71.
(AINL+, AINL-, AINR+, AINR-, AINL2~L8, AINR2~R8, AINM)
AK7782
AVDD/2
MS1337-J-00
2011/11
- 99-
[AK7782]
2-4)
CMOS
CMOS74HC
74AC
74LV74LV-A 74ALVC 74AVC
2-5)
AK7782XTIpin XTOpin
XTI
XTO pin
CKM Mode
R1 max
C0 max
0,2
70Ω
5pF
1,3
50Ω
5pF
XTI,XTOpin
10pF or 15pF or 22pF
10pF or 15pF
2-6)LFLTpin
AK7782LFLTpin (1pin)
R [kΩ] C [nF]
1.5±5% 47± 30%
MS1337-J-00
2011/11
- 100-
[AK7782]
z
100-pin LQFP
(Unit: mm)
1.60 Max.
16.0
14.0
76
50
100
26
14.0
16.0
0.10±0.05
51
75
25
1
0.22±0.05
0.5
0.09~0.20
0.10
M
1.0
S
0°~10°
0.60±0.15
0.10 S
■
:
:
:
(
)
MS1337-J-00
2011/11
- 101-
[AK7782]
AK7782VQ
XXXXXXX
1) Pin #1 indication
2) Date Code: XXXXXXX(7 digits)
3) Marking Code: AK7782VQ
Date (YY/MM/DD)
11/11/02
Revision
00
Reason
Page
MS1337-J-00
Contents
2011/11
- 102-
[AK7782]
z
z
z
z
z
z
MS1337-J-00
2011/11
- 103-