データシート

ASAHI KASEI
[AK4342]
AK4342
24-Bit Stereo DAC with HP-AMP & 2V Line-Out
AK4342
DAC
2Vrms
Aux
3.3V, 16Ω
I2C
62.5mW
3
24-bit
ON/OFF
AK4342
32-pin QFN
† Multi-bit 24-bit ∆Σ DAC
† Sampling Rate: 8kHz to 96kHz
† 8 times Oversampling FIR interpolator
- Passband: 20kHz
- Passband Ripple: ±0.02dB
- Stopband Attenuation: 54dB
† Audio I/F Format: MSB First, 2’s Complement
- I2S, 24bit MSB justified, 24bit/20bit/16bit LSB justified
† Master Clock:
- Normal Speed Mode: 256fs/384fs/512fs/768fs
- Double Speed Mode: 128fs/192fs/256fs/384fs
- Half Speed Mode: 512fs/768fs
† Digital De-emphasis Filter: 32kHz, 44.1kHz and 48kHz
† Analog volume control:
- Headphone: +6dB to – 48dB, Variable Step Size
- Lineout: 0dB to – 31dB, 1dB step
† Digital Linear Attenuator
† Digital Soft Mute
† Analog Mixing Circuit
† µP Interface: 3-wire/I2C (400kHz mode)
† Pop Noise Free at Power-ON/OFF and Mute
† DAC Performance (Lineout)
- THD+N: -88dB
- Dynamic Range: 100dB
- Output Level: 2Vrms
† DAC Performance (Aux-Out)
- THD+N: -87dB
- Dynamic Range: 95dB
† Headphone Amplifier (Cap-less)
- Output Power: 62.5mW x 2ch @16Ω, 3.3V
- THD+N: -60dB @ 25mW
- Dynamic Range: 95dB
† Power Supply:
- DAC & Output Buffers: 2.7V ∼ 3.6V
- Digital Interface: 1.6V ∼ 3.6V
† Power Supply Current: 30.5mA (Headphone amp off)
† Ta: −30 ∼ 85°C
† Package: 32pin QFN
MS0506-J-02
2006/07
-1-
ASAHI KASEI
[AK4342]
LIN
MCLK
BICK
LRCK
SDATA
HVDD
HVSS
HVEE
VCOM
VCOM
Audio
Interface
Clock
Divider
DAC
(Lch)
ATT
&
Soft Mute
VOL
MUTE
HPL
VOL
MUTE
HPR
PMHP
DEM
&
Digital
Filter
DAC
VOL
MUTE
LOUT
VOL
MUTE
ROUT
(Rch)
PMLO
PVDD
PDN
PMDAC
I2C
PVSS
Charge
Pump
CAD0/CSN
SCL/CCLK
Serial I/F
PVEE
CP
SDA/CDTI
CN
PMCP
MUTE
LAUX
MUTE
RAUX
PMAUX
TVDD
DVDD
DVSS
AVDD
AVSS
RIN
MUTET
Figure 1. AK4342 Block Diagram
MS0506-J-02
2006/07
-2-
ASAHI KASEI
[AK4342]
„
AK4342EN
AKD4342
−30 ∼ +85°C
AK4342
32pin QFN (0.5mm pitch)
RIN
LIN
RAUX
LAUX
ROUT
LOUT
HVSS
HVDD
24
23
22
21
20
19
18
17
„
PVEE
DVSS
29
Top View
12
PVSS
DVDD
30
11
PVDD
TVDD
31
10
CN
I2C
32
9
CP
8
13
PDN
AK4342EN
7
28
SDATA
AVSS
6
HVEE
LRCK
14
5
27
BICK
AVDD
4
HPL
MCLK
15
3
26
CAD0/CSN
VCOM
2
HPR
SCL/CCLK
16
1
25
SDA/CDTI
MUTET
MS0506-J-02
2006/07
-3-
ASAHI KASEI
No.
1
Pin Name
SDA
CDTI
2
SCL
4
CCLK
CAD0
CSN
MCLK
5
BICK
6
LRCK
7
SDATA
8
PDN
9
10
11
12
13
CP
CN
PVDD
PVSS
PVEE
14
HVEE
15
16
17
18
19
20
21
22
23
24
HPL
HPR
HVDD
HVSS
LOUT
ROUT
LAUX
RAUX
LIN
RIN
25
MUTET
26
VCOM
27
28
29
30
31
AVDD
AVSS
DVSS
DVDD
TVDD
32
I2C
3
:
[AK4342]
I/O
Function
Control Data Input/Output Pin (I2C pin = “H”)
I/O
An external pull-up resistor is required.
I
Control Data Input Pin (I2C pin = “L”)
Control Data Clock Pin (I2C pin = “H”)
I
An external pull-up resistor is required.
I
Control Data Clock Pin (I2C pin = “L”)
I
Chip Address 0 Select Pin (I2C pin = “H”) (Internal Pull-up Pin to TVDD pin)
I
Control Data Chip Select Pin (I2C pin = “L”) (Internal Pull-up Pin to TVDD pin)
I
Master Clock Input Pin
Serial Bit Clock Pin
I
This clock is used to latch audio data.
L/R Clock Pin
I
This clock determines which audio channel is currently being input on SDATA pin.
I
Audio Serial Data Input Pin
Power-down & Reset Pin
I
When at “L”, the AK4342 is in power-down mode and is held in reset.
The AK4342 must be reset once upon power-up.
O
Positive Charge Pump Capacitor Terminal Pin
I
Negative Charge Pump Capacitor Terminal Pin
Charge Pump Circuit Positive Power Supply Pin
Charge Pump Circuit Ground Pin
O
Charge Pump Circuit Negative Voltage Output Pin
Headphone Amp Negative Power Supply Pin
Connected to PVEE pin
O
Lch Headphone Amp Output Pin
O
Rch Headphone Amp Output Pin
Headphone Amp Positive Power Supply Pin
Headphone Amp Ground Pin
O
Lch Lineout Output Pin
O
Rch Lineout Output Pin
O
Lch Auxiliary Output Pin
O
Rch Auxiliary Output Pin
I
Lch Analog Input Pin
I
Rch Analog Input Pin
Mute Time Constant Control Pin
O
Connected to AVSS pin through a 1µF capacitor for mute time constant.
Common Voltage Output Pin
O
Normally connected to AVSS pin with 0.1µF ceramic capacitor in parallel with a 2.2µF
electrolytic capacitor.
Analog Power Supply Pin
Analog Ground Pin
Digital Ground Pin
Digital Power Supply Pin
Digital Interface Power Supply Pin
Control Mode Select Pin (Internal Pull-up Pin to TVDD pin)
I
“H”: I2C Bus, “L”: 3-wire Serial
LIN, RIN
CAD0/CSN, I2C
MS0506-J-02
2006/07
-4-
ASAHI KASEI
[AK4342]
„
Analog
MUTET, HPL, HPR, LOUT, ROUT, LAUX, RAUX,
RIN, LIN
MS0506-J-02
2006/07
-5-
ASAHI KASEI
[AK4342]
(AVSS, DVSS, HVSS, PVSS = 0V; Note 1)
Parameter
Symbol
min
max
Power Supplies Analog
AVDD
4.0
−0.3
Digital
DVDD
4.0
−0.3
HP-Amp
HVDD
4.0
−0.3
Charge Pump
PVDD
4.0
−0.3
Digital I/F
TVDD
4.0
−0.3
|AVSS – DVSS | (Note 2)
0.3
∆GND1
|AVSS – HVSS | (Note 2)
0.3
∆GND2
|AVSS – PVSS | (Note 2)
0.3
∆GND3
Input Current (any pins except for supplies)
IIN
±10
Analog Input Voltage (Note 3)
AVIN
AVDD+0.3 or 4.0
−0.3
Digital Input Voltage (Note 4)
DVIN
TVDD+0.3 or 4.0
−0.3
Ambient Temperature
Ta
85
−30
Storage Temperature
Tstg
150
−65
Maximum Power Dissipation (Note 5)
Pd
700
Note 1.
Note 2. AVSS, DVSS, HVSS, PVSS pin
Note 3. LIN, RIN pin.
“AVDD+0.3V”
“4.0V”
Note 4. MCLK, BICK, LRCK, SDATA, CAD0/CSN, SCL/CCLK, SDA/CDTI, I2C, PDN pin.
“TVDD+0.3V”
“4.0V”
SCL, SDA pin
(TVDD + 0.3)V
Note 5.
100%
AK4342
Units
V
V
V
V
V
V
V
V
mA
V
V
°C
°C
mW
:
(AVSS, DVSS, HVSS, PVSS = 0V; Note 1)
Parameter
Symbol
Power Supplies Analog
AVDD
(Note 6)
Digital
DVDD
HP-Amp
HVDD
Charge Pump
PVDD
Digital I/F
TVDD
DVDD – AVDD
Difference
DVDD – HVDD
DVDD – PVDD
Note 1.
Note 6. AVDD, DVDD, HVDD, PVDD, TVDD
PDN pin = “L”
OFF
min
2.7
2.7
2.7
2.7
1.6
-0.3
-0.3
-0.3
Typ
3.3
3.3
3.3
3.3
1.8
0
0
0
max
3.6
3.6
3.6
3.6
DVDD
0.3
0.3
0.3
Units
V
V
V
V
V
V
V
V
PDN pin
“H”
:
MS0506-J-02
2006/07
-6-
ASAHI KASEI
[AK4342]
(Ta=25°C; AVDD=DVDD=HVDD=PVDD=3.3V, TVDD=1.8V, AVSS=DVSS=HVSS=PVSS=0V; fs=44.1kHz;
Signal Frequency =1kHz; Measurement band width=10Hz ∼ 20kHz; Headphone-Amp: RL =16Ω; Line output: RL =10kΩ,
Aux output: RL =10kΩ; Charge Pump Circuit External Capacitance: C1=C2= 2.2µF (see Figure 2); unless otherwise
specified)
Parameter
min
typ
max
Units
24
bit
DAC Resolution
LINEIN: (LIN/RIN pins)
Analog Input Characteristics:
Maximum Input Voltage (Note 7)
1.98
Vpp
Feedback Resistance
14
20
26
kΩ
Gain (LIN/RIN pins: External resistor = 20kΩ) (Note 8)
Vin = 1Vpp LIN/RIN → HPL/HPR (Note 9)
-1.5
1.5
4.5
dB
4.5
7.5
10.5
dB
LIN/RIN → LOUT/ROUT (Note 10)
-4.7
-1.7
1.3
dB
LIN/RIN → LAUX/RAUX
Headphone-Amp: (DAC Æ HPL/HPR pins) (Note 11)
Analog Output Characteristics
THD+N
fs=44.1kHz 0dBFS Output, Po=62.5mW
dB
−40
BW=20kHz −4dBFS Output, Po=25mW
-50
dB
−60
fs=96kHz
0dBFS Output, Po=62.5mW
dB
−40
BW=40kHz −4dBFS Output, Po=25mW
-50
dB
−60
87
95
dB
Dynamic Range (−60dBFS Output, A-weighted)
S/N (A-weighted)
87
95
dB
Interchannel Isolation
60
80
dB
DC Accuracy
Interchannel Gain Mismatch
0.2
1.0
dB
Gain Drift
200
ppm/°C
Load Resistance
16
Ω
Load Capacitance
300
pF
Output Voltage (0dBFS Output) (Note 12)
0.9
1.0
1.1
Vrms
Line Output: (DAC Æ LOUT/ROUT pins) (Note 13)
Analog Output Characteristics
THD+N
fs=44.1kHz 0dBFS Output
-78
dB
−88
BW=20kHz -60dBFS Output
dB
−37
fs=96kHz
0dBFS Output
-78
dB
−88
BW=40kHz -60dBFS Output
dB
−35
92
100
dB
Dynamic Range (−60dBFS Output, A-weighted)
S/N (A-weighted)
92
100
dB
Interchannel Isolation
80
100
dB
DC Accuracy
Interchannel Gain Mismatch
0.2
0.8
dB
Gain Drift
200
ppm/°C
Load Resistance
10
kΩ
Load Capacitance
(C3 in Figure 3)
25
pF
Output Voltage
(Note 14)
1.8
2.0
2.2
Vrms
MS0506-J-02
2006/07
-7-
ASAHI KASEI
Note 7. LIN/RIN pin
[AK4342]
AVDD
20kΩ±30%
Note 8.
Note 9. PGAL4-0=PGAR4-0= 0dB
Note 10. LPGA4-0= 0dB
Note 11. PMVCM=PMCP=PMDAC=PMHP bits = “1”, PMLO=PMAUX bits= “0”, LINL=LINR=RINL=RINR bits =
“0”, ATTL7-0=ATTR7-0= 0dB, PGAL4-0=PGAR4-0= 0dB.
Note 12.
AVDD
Vout (typ.) = 0.303 x AVDD [Vrms] @ 0dBFS
Note 13. PMVCM=PMCP=PMDAC=PMLO bits = “1”, PMHP=PMAUX bits= “0”, LINL=LINR=RINL=RINR bits =
“0”, ATTL7-0=ATTR7-0= 0dB, LPGA4-0= 0dB.
Note 14.
AVDD
Vout (typ.) = 0.606 x AVDD [Vrms] @ 0dBFS
HVEE pin
To headphone and lineout amps
PVEE pin
C1
CN pin
Charge Pump Circuit
CP pin
PVSS
C2
Figure 2. Charge Pump Circuit External Capacitor
LOUT/ROUT pin
Analog
Out
C3
Figure 3. Line out circuit example
MS0506-J-02
2006/07
-8-
ASAHI KASEI
[AK4342]
Parameter
min
typ
max
Units
Aux Output: (DAC Æ LAUX/RAUX pins) (Note 15)
Analog Output Characteristics
THD+N
fs=44.1kHz 0dBFS Output
-77
dB
−87
BW=20kHz −60dBFS Output
dB
−32
fs=96kHz
0dBFS Output
-77
dB
−87
BW=40kHz −60dBFS Output
dB
−30
87
95
dB
Dynamic Range (−60dBFS Output, A-weighted)
S/N (A-weighted)
87
95
dB
Interchannel Isolation
80
100
dB
DC Accuracy
Interchannel Gain Mismatch
0.2
0.8
dB
Gain Drift
200
ppm/°C
Load Resistance
(Note 16)
10
kΩ
Load Capacitance
(C4 in Figure 4)
25
pF
Output Voltage
(Note 17)
0.63
0.70
0.77
Vrms
Output Volume for Headphone-amp (PGAL, PGAR):
Step Size
+6dB to –10dB
0.1
1
1.9
dB
–10dB to –32dB
0.1
2
3.9
dB
–32dB to –48dB
0.1
4
7.9
dB
Output Volume for Lineout-amp (LPGA):
Step Size
0dB to –31dB
0.1
1
1.9
dB
Power Supplies
Power Supply Current
Normal Operation (PDN pin = “H”)
(Note 18)
AVDD+HVDD+PVDD
28
45
mA
DVDD+TVDD (fs = 44.1kHz)
2.5
4
mA
DVDD+TVDD (fs = 96kHz)
3.4
5.5
mA
Power-Down Mode (PDN pin = “L”)
(Note 19)
AVDD+HVDD+PVDD+DVDD+TVDD
10
100
µA
Note 15. PMVCM=PMDAC=PMAUX bits = “1”, PMHP=PMLO bits= “0”, LINL=LINR=RINL=RINR bits = “0”,
ATTL7-0=ATTR7-0=0dB
Note 16. AC
Note 17.
AVDD
Vout (typ) = 0.212 x AVDD [Vrms] @ 0dBFS
Note 18. PMVCM=PMDAC=PMHP=PMLO=PMAUX bits = “1” and HP-Amp output is off.
Note 19. I2C pin CAD0/CSN pin
MCLK, BICK, LRCK
DVSS
I2C pin CAD0/CSN pin TVDD
LAUX/RAUX pin
Analog
Out
C4
Figure 4. Aux-out circuit example
MS0506-J-02
2006/07
-9-
ASAHI KASEI
[AK4342]
(Ta=25°C; AVDD, DVDD, HVDD, PVDD=2.7 ∼ 3.6V, TVDD=1.6 ∼ 3.6V; fs=44.1kHz; De-emphasis = “OFF”)
Parameter
Symbol
min
typ
max
Units
DAC Digital Filter:
Passband
PB
0
20.0
kHz
±0.05dB (Note 20)
22.05
kHz
−6.0dB
Stopband
(Note 20)
SB
24.1
kHz
Passband Ripple
PR
dB
±0.02
Stopband Attenuation
SA
54
dB
Group Delay
(Note 21)
GD
21
1/fs
Group Delay Distortion
0
µs
∆GD
Digital Filter + Analog Filter: (Note 22)
Frequency Response 20.0kHz (fs=44.1kHz)
FR
dB
−0.5
40.0kHz (fs=96kHz)
FR
dB
−1.5
Analog Filter: (Note 23)
Frequency Response 20.0kHz
FR
dB
±1.0
40.0kHz
FR
dB
±1.0
Note 20.
fs
PB=0.4535*fs(@±0.05dB), SB=0.546*fs(@−54dB)
Note 21.
16/20/24 bit
Note 22. DAC Æ HPL/HPR/LOUT/ROUT/LAUX/RAUX
Note 23. LIN Æ HPL/LOUT/LAUX, RIN Æ HPR/ROUT/RAUX
DC
(Ta=25°C; AVDD, DVDD, HVDD, PVDD=2.7 ∼ 3.6V; TVDD=1.6 ∼ 3.6V)
Parameter
Symbol
min
High-Level Input Voltage (2.7V ≤ TVDD ≤ 3.6V)
VIH
70%TVDD
VIH
80%TVDD
(1.6V ≤ TVDD < 2.7V)
Low-Level Input Voltage (2.7V ≤ TVDD ≤ 3.6V)
VIL
VIL
(1.6V ≤ TVDD < 2.7V)
Low-Level Output Voltage
(Iout = 3mA)
VOL
Input Leakage Current
(Note 24)
Iin
Note 24. I2Cpin CAD0/CSN pin
MS0506-J-02
typ
-
max
30%TVDD
20%TVDD
0.4
±10
typ. 100kΩ
Units
V
V
V
V
V
µA
2006/07
- 10 -
ASAHI KASEI
[AK4342]
(Ta=25°C; AVDD, DVDD, HVDD, PVDD=2.7 ∼ 3.6V; TVDD=1.6 ∼ 3.6V)
Parameter
Symbol
min
Master Clock Timing (2.7V ≤ TVDD ≤ 3.6V)
Half Speed Mode
(512/768fs)
fCLK
4.096
Normal Speed Mode (256/384/512/768fs)
fCLK
2.048
Double Speed Mode (128/192/256/384fs)
fCLK
6.144
Pulse Width Low
tCLKL
0.4/fCLK
Pulse Width High
tCLKH
0.4/fCLK
Master Clock Timing (1.6V ≤ TVDD < 2.7V)
Half Speed Mode
(512/768fs)
fCLK
4.096
Normal Speed Mode (256/384fs)
fCLK
2.048
Double Speed Mode (128/192fs)
fCLK
6.144
Pulse Width Low
tCLKL
0.4/fCLK
Pulse Width High
tCLKH
0.4/fCLK
LRCK Timing
Frequency
Half Speed Mode
(DFS1-0 bits = “10”)
fsh
8
Normal Speed Mode (DFS1-0 bits = “00”)
fsn
8
Double Speed Mode (DFS1-0 bits = “01”)
fsd
60
Duty Cycle:
Duty
45
Serial Interface Timing (Note 25)
BICK Period
Half Speed Mode
tBCK
1/128fsh
Normal Speed Mode
tBCK
1/128fsn
Double Speed Mode
tBCK
1/64fsd
BICK Pulse Width Low
tBCKL
70
Pulse Width High
tBCKH
70
(Note 26)
tLRB
40
LRCK Edge to BICK “↑”
(Note 26)
tBLR
40
BICK “↑” to LRCK Edge
(Note 27)
tLRB
40
LRCK Edge to BICK “↓”
(Note 27)
tBLR
40
BICK “↓” to LRCK Edge
SDATA Hold Time
tSDH
40
SDATA Setup Time
tSDS
40
Control Interface Timing (3-wire Serial mode)
CCLK Period
tCCK
200
CCLK Pulse Width Low
tCCKL
80
Pulse Width High
tCCKH
80
CDTI Setup Time
tCDS
40
CDTI Hold Time
tCDH
40
CSN “H” Time
tCSW
150
tCSS
50
CSN “ ” to CCLK “↑”
tCSH
50
CCLK “↑” to CSN “↑”
Power-down & Reset Timing
PDN Pulse Width
(Note 28)
tPD
150
Note 25. “
”
Note 26. BCKP bit = “0”
LRCK
BICK
Note 27. BCKP bit = “0”
LRCK
BICK
Note 28.
PDN pin “L”
“H”
typ
max
Units
-
18.432
36.864
36.864
-
MHz
MHz
MHz
ns
ns
-
18.432
18.432
18.432
-
MHz
MHz
MHz
ns
ns
-
24
48
96
55
kHz
kHz
kHz
%
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
-
ns
ns
ns
ns
ns
ns
ns
ns
-
-
ns
“ ”
“ ”
MS0506-J-02
2006/07
- 11 -
ASAHI KASEI
[AK4342]
(
)
(Ta=25°C; AVDD, DVDD, HVDD, PVDD=2.7 ∼ 3.6V; TVDD=2.7 ∼ 3.6V)
Parameter
Symbol
min
2
Control Interface Timing (I C Bus mode): (Note 29)
SCL Clock Frequency
fSCL
Bus Free Time Between Transmissions
tBUF
1.3
Start Condition Hold Time (prior to first clock pulse) tHD:STA
0.6
Clock Low Time
tLOW
1.3
Clock High Time
tHIGH
0.6
Setup Time for Repeated Start Condition
tSU:STA
0.6
SDA Hold Time from SCL Falling
(Note 30)
tHD:DAT
0
SDA Setup Time from SCL Rising
tSU:DAT
0.1
Rise Time of Both SDA and SCL Lines
tR
Fall Time of Both SDA and SCL Lines
tF
Setup Time for Stop Condition
tSU:STO
0.6
Capacitive load on bus
Cb
Pulse Width of Spike Noise Suppressed by Input Filter
tSP
0
Note 29. I2C
I2C
Note 30.
Philips Semiconductors
TVDD
300ns (SCL
typ
max
Units
-
400
0.3
0.3
400
50
kHz
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
pF
ns
-
2.7V ∼ 3.6V
)
MS0506-J-02
2006/07
- 12 -
ASAHI KASEI
[AK4342]
„
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK
VIL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Figure 5. Clock Timing
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tSDS
tSDH
VIH
SDATA
VIL
Figure 6. Serial Interface Timing (BCKP bit = “0”)
MS0506-J-02
2006/07
- 13 -
ASAHI KASEI
[AK4342]
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tSDS
tSDH
VIH
SDATA
VIL
Figure 7. Serial Interface Timing (BCKP bit = “1”)
VIH
CSN
VIL
tCSS
tCCKL tCCKH
VIH
CCLK
VIL
tCDS
CDTI
C1
tCDH
C0
R/W
VIH
A4
VIL
Figure 8. WRITE Command Input Timing
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
CDTI
VIL
D3
D2
D1
D0
VIH
VIL
Figure 9. WRITE Data Input Timing
MS0506-J-02
2006/07
- 14 -
ASAHI KASEI
[AK4342]
VIH
SDA
VIL
tLOW
tBUF
tR
tHIGH
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
Start
tHD:DAT
tSU:DAT
tSU:STA
tSU:STO
Start
Stop
Figure 10. I2C Bus Mode Timing
tPD
PDN
VIL
Figure 11. Power-down & Reset Timing
MS0506-J-02
2006/07
- 15 -
ASAHI KASEI
[AK4342]
„
AK4342
1)
MCLK, BICK, LRCK
MCLK LRCK
MCLK
∆Σ
MCLK
MCLK LRCK
DFS1-0 bit Half speed mode Normal speed mode
Double speed mode
(Table 2)
FS3-0 bit
DFS1-0 bits
DFS1 bit
0
0
1
1
FS3 bit
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
(Table
PDN pin or PMDAC bit
DFS0 bit
0
1
0
1
FS2 bit
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Mode
Normal Speed
Double Speed
Half Speed
fs
MCLK Frequency
256/384/512/768fs
8 ∼ 48kHz
128/192/256/384fs
60 ∼ 96kHz
512/768fs
8 ∼ 24kHz
Reserve
Table 1. System Clock Example
FS1 bit
FS0 bit
Sampling Frequency
0
0
44.1kHz
0
1
32kHz
1
0
48kHz
1
1
(Reserve)
0
0
88.2kHz
0
1
64kHz
1
0
96kHz
1
1
(Reserve)
0
0
22.05kHz
0
1
16kHz
1
0
24kHz
1
1
(Reserve)
0
0
11.025kHz
0
1
8kHz
1
0
12kHz
1
1
(Reserve)
Table 2. Set up of Sampling Frequency
DAC S/N
Default
Default
Half speed mode (DFS1-0 bits = “10”)
S/N
S/N (fs=8kHz, 20kLPF + A-weighted)
Lineout
Headphone
Aux-out
Normal Speed
89dB
87dB
87dB
Half Speed
99dB
95dB
95dB
Table 3. Relationship between Clock Mode and S/N of Lineout, Headphone and Aux-out
Mode
DAC
bit = “1”, PMLO bit = “1” or PMCP bit = “1”)
(PMDAC bit = “1”, PMHP
(MCLK, BICK, LRCK)
DAC
DAC,
(PMDAC bit =
PMHP bit = PMLO bit = PMCP bit = “0”)
MS0506-J-02
2006/07
- 16 -
ASAHI KASEI
[AK4342]
„
SDATA, BICK, LRCK 3
5
(Table 4) DIF2-0 bit
Mode 0
16
DAC
Mode 1 Mode 0 20
Mode 4 Mode 0 24
Mode 2
ADC
DSP
Mode 3 I2S
BICK≥48fs
Mode 2 Mode 3 16
LSB
17∼24bit
8
“0”
20
LSB
21∼24bit
4
“0”
MSB
2’s complement
BCKP bit
BICK
LRP bit
LRCK
(Table 5) BCKP bit LRP bit
PMDAC
bit = “0”
DIF2
bit
DIF1
bit
DIF0
bit
MODE
0
0
0
0: 16bit, LSB justified
0
0
1
1: 20bit, LSB justified
0
1
0
2: 24bit, MSB justified
0
1
1
3: I2S Compatible
1
0
0
4: 24bit, LSB justified
BICK
Figure
32fs ≤ BICK ≤ 128fs (Half/Normal Speed Mode)
32fs ≤ BICK ≤ 64fs
(Double Speed Mode)
40fs ≤ BICK ≤ 128fs (Half/Normal Speed Mode)
40fs ≤ BICK ≤ 64fs
(Double Speed Mode)
48fs ≤ BICK ≤ 128fs (Half/Normal Speed Mode)
48fs ≤ BICK ≤ 64fs
(Double Speed Mode)
BICK=32fs
(Half/Normal/Double Speed Mode)
or
48fs ≤ BICK ≤ 128fs (Half/Normal Speed Mode)
48fs ≤ BICK ≤ 64fs
(Double Speed Mode)
48fs ≤ BICK ≤ 128fs (Half/Normal Speed Mode)
48fs ≤ BICK ≤ 64fs
(Double Speed Mode)
Figure 12
Figure 13
Figure 14
Default
Figure 15
Figure 13
Table 4. Audio Data Format
BCPKP bit
LRP bit
0
0
0
1
1
0
1
1
BICK Polarity
LRCK Polarity
(SDATA Latch Timing)
Lch Data
Rch Data
H: Mode 0,1,2,4
L: Mode 0,1,2,4
↑
L: Mode 3
H: Mode 3
L: Mode 0,1,2,4
H: Mode 0,1,2,4
↑
H: Mode 3
L: Mode 3
H: Mode 0,1,2,4
L: Mode 0,1,2,4
↓
L: Mode 3
H: Mode 3
L: Mode 0,1,2,4
H: Mode 0,1,2,4
↓
H: Mode 3
L: Mode 3
Table 5. LRCK and BICK Polarities
Default
LRCK
BICK
(32fs)
SDATA
Mode 0
15
14
6
5
4
3
2
15
14
1
0
15
14
0
Don’t care
6
5
4
3
2
15
14
1
0
15
14
BICK
SDATA
Mode 0
Don’t care
0
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 12. Mode 0 Timing (BCKP bit = “0”, LRP bit = “0”)
MS0506-J-02
2006/07
- 17 -
ASAHI KASEI
[AK4342]
LRCK
BICK
SDATA
Mode 1
Don’t care
19
0
Don’t care
19
0
Don’t care
19
0
19
0
19:MSB, 0:LSB
SDATA
Mode 4
Don’t care
23
22
21
20
23
22
21
20
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 13. Mode 1, 4 Timing (BCKP bit = “0”, LRP bit = “0”)
Rch
Lch
LRCK
BICK
SDATA
15
14
0
19
18
4
1
0
23
22
8
3
4
Don’t
care
15
14
0
Don’t
care
19
18
4
1
0
Don’t
care
23
22
8
3
4
Don’t
care
15
14
Don’t
care
19
18
Don’t
care
23
22
16bit
SDATA
20bit
SDATA
1
0
1
0
24bit
Figure 14. Mode 2 Timing (BCKP bit = “0”, LRP bit = “0”)
MS0506-J-02
2006/07
- 18 -
ASAHI KASEI
[AK4342]
Lch
LRCK
Rch
BICK
SDATA
16bit
SDATA
20bit
SDATA
15
14
0
19
18
4
1
0
23
22
8
3
4
1
0
15
14
6
5
4
3
2
Don’t
care
15
14
0
Don’t
care
19
18
4
1
0
Don’t
care
23
22
8
3
4
1
15
14
6
5
4
3
Don’t
care
15
Don’t
care
19
0
Don’t
care
23
2
1
24bit
BICK
(32fs)
SDATA
16bit
0
1
0
0
15
Figure 15. Mode 3 Timing (BCKP bit = “0”, LRP bit = “0”)
MS0506-J-02
2006/07
- 19 -
ASAHI KASEI
[AK4342]
„
AK4342
MUTE
256
DAC
ATT
0dB
-48dB
1
256
Table 7
DATTC bit
“0”
“1”
Lch, Rch
ATTL7-0 bit
Lch, Rch
DATTC bit
ATTL7-0 bits
ATT (dB)
ATTR7-0 bits
FFH
20 log10 (ATT_DATA / 255)
•
01H
00H
Mute
Table 6. Digital Volume Gain Table
STS1 bit
STS0 bit
0
0
0
1
1
0
1
1
Default
Transition Time
1 Level
255 to 0
Half Speed Mode
1LRCK
255LRCK
Normal Speed Mode
2LRCK
510LRCK
Double Speed Mode
4LRCK
1020LRCK
Half Speed Mode
2LRCK
510LRCK
Normal Speed Mode
4LRCK
1020LRCK
Double Speed Mode
8LRCK
2040LRCK
Half Speed Mode
4LRCK
1020LRCK
Normal Speed Mode
8LRCK
2040LRCK
Double Speed Mode
16LRCK
4080LRCK
Half Speed Mode
8LRCK
2040LRCK
Normal Speed Mode
16LRCK
4080LRCK
Double Speed Mode
32LRCK
8160LRCK
Table 7. Transition Time for Digital Volume
Sampling Speed
MS0506-J-02
Default
2006/07
- 20 -
ASAHI KASEI
[AK4342]
„
×ATT
−∞
ATT
SMUTE bit
−∞ (“0”)
(Figure 16)
×ATT
“1”
ATT
ATT
SMUTE bit “0”
−∞
ATT
ATT
SMUTE bit
STS1-0 bits
STS1-0 bits
(1)
ATT Level
(1)
(3)
Attenuation
-∞
GD
GD
(2)
Analog Output
Figure 16.
:
(1) ATT
×ATT
510LRCK
Normal Speed Mode, STS1-0 bit = “01”
(2)
(3)
ATT
“128”
(GD)
−∞
ATT
„
IIR
3
(32kHz, 44.1kHz, 48kHz)
DEM1-0 bit
Half Speed Mode, Double Speed Mode
DEM1-0 bit
(50/15µs
)
OFF
DEM1 bit
DEM0 bit
De-emphasis
0
0
44.1kHz
0
1
OFF
1
0
48kHz
1
1
32kHz
Table 8. De-emphasis Filter Frequency control
MS0506-J-02
Default
2006/07
- 21 -
ASAHI KASEI
[AK4342]
„
PVDD pin
(PVEE)
PMCP bit = “1”
(MCLK, BICK, LRCK)
FS3-0 bit
FS3 bit
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FS2 bit
FS1 bit
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Table 9.
FS0 bit
Sampling
Frequency
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
44.1kHz
32kHz
48kHz
(Reserve)
88.2kHz
64kHz
96kHz
(Reserve)
22.05kHz
16kHz
24kHz
(Reserve)
11.025kHz
8kHz
12kHz
(Reserve)
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Power up time of
Charge Pump
Circuit
11.6ms
8.0ms
10.7ms
(Reserve)
11.6ms
8.0ms
10.7ms
(Reserve)
11.6ms
8.0ms
10.7ms
(Reserve)
11.6ms
8.0ms
10.7ms
(Reserve)
Default
„
LIN/RIN pin
Ri
30% Ω
PMDAC, PMHP, PMLO or PMAUX
LINL, LINR, RINL, RINR
PTS1-0 bit FS3-0 bit
LINL, LINR, RINL, RINR
(Rf)
20k ±
“1”
Rf = 20kΩ
Ri
-
LIN/RIN
+
Figure 17. Block diagram of LIN/RIN inputs
MS0506-J-02
2006/07
- 22 -
ASAHI KASEI
[AK4342]
„
HVDD pin
PVEE pin
HVEE pin
HVEE pin PVEE pin
HVSS(0V)
min. 16Ω
1.
+6dB
PTS1-0 bit (Table 15)
PGAC bit “1”
PGAL4-0 bit
-48dB
L/R
(Table 10)
(Table 2)
PGAL4-0 bit Lch, Rch
PGAR4-0 bit
PGAC bit
PGAC bit “0”
Lch, Rch
PGAL4-0 bit PGAR4-0 bit
PGAC bit = “0” Æ “1” (“PGAL4-0 bit ≠ PGAR4-0 bit”
)
PGAC bit = “1” Æ “0” (“PGAL4-0 bit ≠ PGAR4-0 bit”
PGAR4-0 bit
PGAL4-0 bits
GAIN/ATT (dB)
PGAR4-0 bits
1FH
+6
1EH
+5
•
•
1AH
+1
19H
0
18H
-1
•
•
10H
-9
0FH
-10
0EH
-12
•
•
06H
-28
05H
-30
04H
-32
03H
-36
02H
-40
01H
-44
00H
-48
Table 10.
Lch, Rch
PGAC bit
Rch
)
Step
Level
1dB
16
2dB
11
4dB
5
PGAL4-0 bit
Rch
Default
2.
HMUTEL/HMUTER bit = “1”
L/R
(FS3-0 bit) PTS1-0 bit
HPL/HPR pin
HMUTEL/HMUTER bit
MS0506-J-02
HVSS(0V)
“0”
2006/07
- 23 -
ASAHI KASEI
[AK4342]
3. Power-up/down
PMHP bit
pin
HVSS(0V)
PMHP bit = “0”
PUT1-0 bit
HPL/HPR
FS3-0 bit
HMUTEL
bit = HMUTER bit = “1”
„
HVDD pin HVEE pin
HVEE pin PVEE pin
PVEE pin
HVSS (0V)
typ. 2Vrms (@AVDD = 3.3V
min. 10kΩ
1.
0dB
-31dB, 1dB Step
L/R
(Table 11)
PTS1-0 bit (Table 15)
Table 2
LPGA4-0 bits
ATT (dB)
1FH
0
1EH
-1
1DH
-2
1CH
-3
•
•
18H
-29
01H
-30
00H
-31
Table 11.
Step
Level
Default
1dB
32
2.
LMUTE bit = “1”
PTS1-0 bit
LMUTE bit = “0”
L/R
LOUT pin ROUT pin
FS3-0 bits
HVSS(0V)
3. Power-up/down
PMLO bit
HVSS(0V)
PMLO bit = “0”
PUT1-0 bit
MS0506-J-02
LOUT/ROUT pin
FS3-0 bits
LMUTE bit = “1”
2006/07
- 24 -
ASAHI KASEI
[AK4342]
4.
LOUT/ROUT
470Ω
1nF
470
Analog
Out
LOUT/ROUT
1n
Figure 18. External 1st order LPF Circuit Example
(fc = 339kHz, gain = -0.06dB @ 40kHz)
„ AUX
AUX
AVCMN bit
VCOM
0.45 x AVDD
typ. 700mVrms @AVDD=3.3V, 0dBFS
min. 10kΩ
“0”
AUX
“0.45x AVDD”
AVSS
AVDD
[
]: MUTET pin
AUX
PMAUX bit “0”
pin “L” (AVSS)
LAUX/RAUX pin
MUTET pin
= 1.0µF, AVDD=3.3V
AUX
AMUTE bit
VCOM
AVCMN bit “1”
MUTET pin AVSS pin
:
: τ = 100ms(typ), 300ms(max)
LAUX/RAUX
“1”
LAUX/RAUX
AMUTE bit “0”
PMAUX bit
AVCMN bit
LAUX pin
RAUX pin
(1) (2)
(3)
(4)
Figure 19. AUX
(1) AUX
(2) AUX
(3) AUX
(4) AUX
(PMAUX bit = “1”)
AVSS
(AVCMN bit = “1”)
(AVCMN bit = “0”)
(PMAUX bit = “0”)
AVSS
MS0506-J-02
2006/07
- 25 -
ASAHI KASEI
[AK4342]
„
Table 13
Table 15
PUT1-0 bit PTS1-0 bit
Table 12, Table 14
Address
Register Name
PUT1-0 bit
00H
PMHP, PMLO
Table 12. Registers with transition time (PUT1-0 bits)
PUT1 bit
PUT0 bit
Sampling Frequency (FS3-0 bits)
8k / 16k / 32k / 64kHz
11.025k / 22.05k / 44.1k/ 88.2kHz
12k / 24k / 48k / 96kHz
8k / 16k / 32k / 64kHz
11.025k / 22.05k / 44.1k/ 88.2kHz
12k / 24k / 48k / 96kHz
8k / 16k / 32k / 64kHz
11.025k / 22.05k / 44.1k/ 88.2kHz
12k / 24k / 48k / 96kHz
8k / 16k / 32k / 64kHz
11.025k / 22.05k / 44.1k/ 88.2kHz
12k / 24k / 48k / 96kHz
Table 13. Transition Time (PUT1-0 bits)
0
0
0
1
1
0
1
1
Transition Time
32ms
34.8ms
32ms
64ms
69.7ms
64ms
128ms
139ms
128ms
256ms
278ms
256ms
Default
Address
Register Name
01H
AMUTE
04H
HMUTEL, PGAL4-0
PTS1-0 bit
05H
HMUTER, PGAR4-0
06H
RINR, RINL, LINR, LINL, DACLR
07H
LMUTE, LPGA4-0
Table 14. Registers with transition time (PTS1-0 bits)
PTS1 bit
PTS0 bit
Sampling Frequency (FS3-0 bits)
8k / 16k / 32k / 64kHz
11.025k / 22.05k / 44.1k/ 88.2kHz
12k / 24k / 48k / 96kHz
8k / 16k / 32k / 64kHz
11.025k / 22.05k / 44.1k/ 88.2kHz
12k / 24k / 48k / 96kHz
8k / 16k / 32k / 64kHz
11.025k / 22.05k / 44.1k/ 88.2kHz
12k / 24k / 48k / 96kHz
8k / 16k / 32k / 64kHz
11.025k / 22.05k / 44.1k/ 88.2kHz
12k / 24k / 48k / 96kHz
Table 15. Transition Time (PTS1-0 bits)
0
0
0
1
1
0
1
1
MS0506-J-02
Transition Time
16ms
17.4ms
16ms
32ms
34.8ms
32ms
64ms
69.7ms
64ms
128ms
139ms
128ms
Default
2006/07
- 26 -
ASAHI KASEI
[AK4342]
„ System Reset
PDN pin = “L”
PDN pin
“H”
HPL, HPR, LAUX, RAUX, LOUT, ROUT,
DAC
LRCK
AVDD, DVDD, HVDD, PVDD, TVDD
PDN pin = “L” Æ “H”
VCOM, DAC,
PDN pin
PMDAC bit
“1”
MCLK
MCLK
LRCK
„ Power-Up/Down Sequence
Power Supply
(1)
PDN pin
(2)
(4)
PMVCM bit
(3)
Clock Input
PMCP bit
PVEE pin
Don’t care
Don’t care
0V
PVEE
0V
(10)
PMDAC bit
DAC Internal
State
PMHP bit
(or PMLO bit)
Power Down
Normal Operation
Power Down
(5)
HMUTEL/R bits
(or LMUTE bit)
HPL/HPR pins
(or LOUT/ROUT pins)
0V
Normal
MUTE
(6)
MUTE
(9)
(8)
(7)
0V
PMLO bit
(or PMHP bit)
LMUTE bit
(or HMUTEL/R bit)
LOUT/ROUT pins
(or HPL/HPR pins)
0V
Normal
MUTE
(6)
(7)
0V
MUTE
(8)
(9)
Figure 20.
(1)
PDN pin “L” Æ “H”
AK4342
PDN pin = “L”
PDN pin “H”
150ns
“L”
AVDD, DVDD, HVDD, PVDD, TVDD
(2) DFS1-0, DIF2-0, DEM1-0, FS3-0, PTS1-0, STS1-0, PUT1-0, LRP, BCKP, DACLR bit
MS0506-J-02
DAC
2006/07
- 27 -
ASAHI KASEI
[AK4342]
(3)
(MCLK, BICK, LRCK)
(4)
DAC, VCOM
PVEE pin FS3-0 bi
(5) PMCP bit
PMHP bit (PMLO bit)
PMHP bit (PMLO bit)
: PMCP bit = PMDAC bit = PMVCM bit = “0” Æ “1”
(Table 9)
PVEE
“1”
“1”
: PMHP bit (PMLO bit) = “0” Æ “1”
DC
PUT1-0 bit FS3-0 bit
(6)
PMHP bit
PMLO bit
: HMUTEL bit = HMUTER bit (LMUTE bit) = “1” Æ “0”
(7)
PTS1-0 bit
FS3-0 bit
LPGA4-0, PGAL4-0, PGAR4-0
PGAC bit
: HMUTEL = HMUTER (LMUTE bit) = “0” Æ “1”
(8)
PTS1-0 bit
FS3-0 bit
LPGA4-0, PGAL4-0, PGAR4-0
PGAC bit
: PMHP bit (PMLO bit) = “1” Æ “0”
(9)
PUT1-0 bit
(10)
PVEE pin
FS3-0 bit
DAC
VCOM
PVEE pin HVEE pin
typ.17.5kΩ
PMHP bit
PMLO bit
: PMCP bit = PMDAC bit = PMVCM bit = “1” Æ “0”
0V
MS0506-J-02
2006/07
- 28 -
ASAHI KASEI
[AK4342]
„
1. 3
(I2C pin = “L”)
3
address(2bits, “01”
data(MSB first, 8bits)
CSN
“L”
I/F
: CSN, CCLK, CDTI
I/F
Chip
), Read/Write(1bit, Fixed to “1”, Write only), Register address(MSB first, 5bits), Control
CCLK
CCLK
5MHz(max)
PDN pin =
CSN
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0:
R/W:
A4-A0:
D7-D0:
Chip Address (Fixed to “01”)
READ/WRITE (Fixed to “1”, Write only)
Register Address
Control Data
Figure 21. Serial Control I/F Timing
MS0506-J-02
2006/07
- 29 -
ASAHI KASEI
[AK4342]
2. I2C-
(I2C pin = “H”)
AK4342
I 2C
(max:400kHz)
1. WRITE
I2C
Figure 22
IC
(Start Condition)
SCL
“H”
SDA
“H”
“L”
(Figure 28)
8
(R/W)
6
“001000”
IC
CAD0 pin
(Figure 23)
AK4342
(Acknowledge)
SDA
(Figure 29) R/W
“0”
R/W
“1”
7
1
2
(
(Figure 24)
3
(Figure 25)
“0”
MSB first
SDA
“L”
)
8
MSB first
3
8
AK4342
(Stop Condition)
(Figure 28)
“H”
AK4342
SCL
“H”
1
“09H”
“00H”
“H”
SDA
SCL
“L”
(Figure 30)
“H”
SCL
“L”
“H”
SDA
S
T
A
R
T
SDA
S
T
O
P
R/W="0"
Slave
S Address
Sub
Address(n)
Data(n)
A
C
K
A
C
K
A
C
K
Data(n+1)
Data(n+x)
A
C
K
P
A
C
K
A
C
K
Figure 22. I2C
0
0
Figure 23.
0
0
1
0
1
D6
0
CAD0
R/W
A3
A2
A1
A0
D3
D2
D1
D0
CAD0
0
A4
Figure 24.
D7
0
D5
Figure 25.
2
D4
3
MS0506-J-02
2006/07
- 30 -
ASAHI KASEI
[AK4342]
2. READ
R/W bit
“1”
AK4342
READ
“09H”
“00H”
AK4342
2
READ
2-1.
AK4342
AK4342
(READ
WRITE
“n+1”
(R/W bit = “1”)
READ
)
“n”
1
READ
S
T
A
R
T
SDA
S
T
O
P
R/W="1"
Slave
S Address
Data(n)
A
C
K
Data(n+1)
Data(n+2)
A
C
K
A
C
K
Data(n+x)
A
C
K
P
A
C
K
A
C
K
Figure 26. CURRENT ADDRESS READ
2-2.
READ
(R/W bit = “1”)
WRITE
WRITE
= “0”)
AK4342
(R/W bit = “1”)
READ
(R/W bit
AK4342
1
READ
S
T
A
R
T
SDA
S
T
A
R
T
R/W="0"
Sub
Address(n)
Slave
S Address
A
C
K
Slave
S Address
A
C
K
S
T
O
P
R/W="1"
Data(n)
A
C
K
Data(n+1)
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 27. RANDOM ADDRESS READ
MS0506-J-02
2006/07
- 31 -
ASAHI KASEI
[AK4342]
SDA
SCL
S
P
start condition
stop condition
Figure 28.
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
acknowledge
SCL FROM
MASTER
2
1
8
9
S
clock pulse for
acknowledgement
START
CONDITION
Figure 29. I2C
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 30. I2C
MS0506-J-02
2006/07
- 32 -
ASAHI KASEI
[AK4342]
„ Register Map
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
Register Name
Power Management
Mode Control 0
Mode Control 1
Mode Control 2
HP Lch PGA Control
HP Rch PGA Control
Output Select
Lineout PGA control
DAC Lch ATT
DAC Rch ATT
D7
D6
D5
D4
D3
D2
D1
D0
0
0
PMAUX
AVCMN
0
0
PGAC
0
0
PUT1
0
ATTL7
ATTR7
PTS1
0
0
PUT0
0
ATTL6
ATTR6
FS3
PTS0
HMUTEL
HMUTER
RINR
LMUTE
ATTL5
ATTR5
PMHP
DIF0
FS0
DATTC
PGAL2
PGAR2
LINL
LPGA2
ATTL2
ATTR2
PMVCM
SMUTE
PMCP
DIF1
FS1
STS0
PGAL3
PGAR3
LINR
LPGA3
ATTL3
ATTR3
PMDAC
AMUTE
PMLO
DIF2
FS2
STS1
PGAL4
PGAR4
RINL
LPGA4
ATTL4
ATTR4
DFS1
DEM1
BCKP
PGAL1
PGAR1
DACLR
LPGA1
ATTL1
ATTR1
DFS0
DEM0
LRP
PGAL0
PGAR0
0
LPGA0
ATTL0
ATTR0
PDN pin = “L”
PDN pin “L”
Note 31: “0”
Note 32:
“1”
00H ∼ 09H
MS0506-J-02
2006/07
- 33 -
ASAHI KASEI
[AK4342]
„ Register Definitions
Addr
00H
Register Name
Power Management
R/W
Default
D7
0
RD
0
D6
D5
0
PMAUX
RD
0
R/W
0
D4
PMLO
R/W
0
D3
PMCP
R/W
0
D2
D1
D0
PMHP
PMDAC
PMVCM
R/W
0
R/W
0
R/W
0
PMVCM: VCOM
0: Power OFF (Default)
1: Power ON
PMDAC: DAC
0: Power OFF (Default)
1: Power ON
OFF
ON
ATT
PMHP:
0: Power OFF (Default)
HPL/HPR pin
HVSS (0V)
1: Power ON
PMCP:
0: Power OFF (Default)
1: Power ON
PMLO:
0: Power OFF (Default)
LOUT/ROUT pin
1: Power ON
PMAUX: Aux Out
0: Power OFF (Default)
LAUX/RAUX pin
1: Power ON
PDN pin
HVSS (0V)
AVSS (0V)
“L”
“0”
MS0506-J-02
2006/07
- 34 -
ASAHI KASEI
Addr
01H
[AK4342]
Register Name
Mode Control 0
R/W
Default
D7
D6
D5
AMUTE
SMUTE
AVCMN
R/W
1
R/W
0
R/W
0
D4
DIF2
R/W
0
D3
DIF1
R/W
1
D2
DIF0
R/W
0
D1
DFS1
R/W
0
D0
DFS0
R/W
0
D2
FS0
R/W
0
D1
DEM1
R/W
0
D0
DEM0
R/W
1
DFS1-0:
(Table 1)
Default: “00” (Normal Speed Mode)
DIF2-0:
(Table 4)
Default: “010” (Mode 2; 24bit, MSB justified)
AVCMN: LAUX/RAUX
0: LAUX/RAUX pin
1: LAUX/RAUX pin
SMUTE:
0:
1: DAC
AVSS (0V)
“0.45 x AVDD”
(Default)
(Default)
AMUTE: LAUX/RAUX
0:
1:
LAUX/RAUX pin
Addr
02H
Register Name
Mode Control 1
R/W
Default
D7
0
RD
0
(Default)
D6
0
RD
0
DEM1-0:
Default: “01” (OFF)
FS3-0:
D5
FS3
R/W
0
D4
FS2
R/W
0
D3
FS1
R/W
0
(Table 8)
(Table 2)
Default: “0000” (fs=44.1kHz)
MS0506-J-02
2006/07
- 35 -
ASAHI KASEI
Addr
03H
[AK4342]
Register Name
Mode Control 2
R/W
Default
D7
PGAC
R/W
0
LRP: LRCK
0:
1:
(Default)
BCKP: BICK
0:
1:
(Default)
D6
PTS1
R/W
0
D5
PTS0
R/W
0
DATTC:
0: Independent (Default)
1: Dependent
DATTC bit
“1”
ATTL7-0 bit L/Rch
“0”
ATTL7-0 bit Lch ATTR7-0 bit
STS1-0:
D4
STS1
R/W
0
D3
STS0
R/W
1
D2
DATTC
R/W
0
D1
BCKP
R/W
0
D0
LRP
R/W
0
DATTC bit
Rch
(Table 7)
Default: “01” (1020LRCK at Normal Speed Mode)
PTS1-0: AMUTE, LINL, LINR, RINL, RINR, DACLR, LPGA4-0, PGAL4-0, PGAR4-0, LMUTE, HMUTEL,
HMUTER
(Table 15)
Default: “00”
PGAC: PGA Control Mode Select
0: Independent (Default)
1: Dependent
PGAC bit
“1”
PGAL4-0 bit L/Rch
“0”
PGAL4-0 bit Lch PGAR4-0 bit
Addr
04H
05H
Register Name
Lch PGA Control
Rch PGA Control
R/W
Default
PGAL4-0:
HMUTEL:
0:
1:
PGAR4-0:
HMUTER:
0:
1:
D7
0
0
RD
0
Lch
Lch
D6
0
0
RD
0
PGAC bit
Rch
D5
HMUTEL
HMUTER
R/W
1
D4
PGAL4
PGAR4
R/W
1
D3
PGAL3
PGAR3
R/W
1
D2
PGAL2
PGAR2
R/W
0
D1
PGAL1
PGAR1
R/W
0
D0
PGAL0
PGAR0
R/W
1
(Table 10)
PGAL4-0 bit
(Default)
PGAL4-0 bit
Rch
Rch
(Table 10)
PGAR4-0 bit
(Default)
PGAR4-0 bit
MS0506-J-02
2006/07
- 36 -
ASAHI KASEI
Addr
06H
[AK4342]
Register Name
Output Select 0
R/W
Default
D7
PUT1
R/W
1
DACLR: DAC
0: OFF (Default)
1: ON
D6
PUT0
R/W
0
D5
RINR
R/W
0
D4
RINL
R/W
0
D3
LINR
R/W
0
D2
LINL
R/W
0
D1
DACLR
R/W
0
D0
0
RD
0
MIX
LINL: LIN pin
0: OFF (Default)
1: ON
MIX
Lch
LINR: LIN pin
0: OFF (Default)
1: ON
MIX
Rch
RINL: RIN pin
0: OFF (Default)
1: ON
MIX
Lch
RINR: RIN pin
0: OFF (Default)
1: ON
MIX
Rch
PUT1-0: PMHP, PMLO bit
Defaults: “10”
(Table 13)
20kΩ(typ)
Ri
-
LIN
+
R
R
LINL bit
R
RINL bit
-
To Lch output buffers
+
R
DAC(Lch)
Lch MIX-Amp
DACLR bit
R
R
DAC(Rch)
R
RIN
20kΩ(typ)
LINR bit
Ri
+
+
R
To Rch output buffers
Rch MIX-Amp
RINR bit
Figure 31.
MS0506-J-02
2006/07
- 37 -
ASAHI KASEI
Addr
07H
[AK4342]
Register Name
Lineout PGA Control
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
LMUTE
R/W
1
D4
LPGA4
R/W
1
D3
LPGA3
R/W
1
D2
LPGA2
R/W
1
D1
LPGA1
R/W
1
D0
LPGA0
R/W
1
D5
ATTL5
ATTR5
R/W
1
D4
ATTL4
ATTR4
R/W
1
D3
ATTL3
ATTR3
R/W
1
D2
ATTL2
ATTR2
R/W
1
D1
ATTL1
ATTR1
R/W
1
D0
ATTL0
ATTR0
R/W
1
LPGA4-0:
Default: “1FH” (0dB) (Table 11)
LMUTE: LOUT/ROUT
0:
LPGA4-0 bit
1:
(Default)
LPGA4-0 bit
Addr
08H
09H
Register Name
DAC Lch ATT
DAC Rch ATT
R/W
Default
D7
ATTL7
ATTR7
R/W
1
D6
ATTL6
ATTR6
R/W
1
ATTL7-0: DAC Lch
ATTR7-0: DAC Rch
ATT = 20 log10 (ATT_DATA / 255) [dB]
FFH: 0dB (Default)
00H: Mute
MS0506-J-02
2006/07
- 38 -
ASAHI KASEI
[AK4342]
Figure 32
[AKD4342]
Analog Input
Lineout
Aux-out
10u
+
2
Power Supply
2.7 ∼ 3.6V
23
22
21
20
19
18
17
LIN
LAUX
ROUT
LOUT
HVSS
HVDD
1u
RAUX
RIN
24
0.1u
25 MUTET
HPR
16
26 VCOM
HPL
15
27 AVDD
HVEE
14
Headphone
0.1u
0.1u
10
2.2u
+
28 AVSS
AK4342EN
PVEE
13
29 DVSS
Top View
PVSS
12
30 DVDD
PVDD
11
31 TVDD
CN
10
CP
9
0.1u
Power Supply
1.6 ∼ 3.6V
+
SCL/CCLK
CAD0/CSN
MCLK
BICK
LRCK
SDATA
PDN
3
4
5
6
7
8
Analog Ground
2
Digital Ground
SDA/CDTI
32 I2C
1
10u 0.1u
2.2u
(+):Note
0.1u
2.2u
(+):Note
µP
DSP
Figure 32.
Note:
-
HVDD pin
(3
PVDD pin
)
2Ω
ESR
CP pin
AVSS, DVSS, PVSS, HVSS
TVDD
DVDD
(10µF, 0.1µF)
TVDD pin
DVDD pin
MS0506-J-02
TVDD pin
2006/07
- 39 -
ASAHI KASEI
[AK4342]
32pin QFN (Unit: mm)
0.40 ± 0.10
5.00 ± 0.10
4.75 ± 0.10
24
3.5
25
16
4.75 ± 0.10
25
B
3.5
5.00 ± 0.10
24
17
9
32
1
0.23
Exposed
Pad
32
2
.4
C0
8
0.50
+0.07
-0.05
1
0.10
M
0.85 ± 0.05
A
AB
:
0.04
0.01+- 0.01
0.08 C
0.20
C
(Exposed Pad)
„
:
:
:
MS0506-J-02
2006/07
- 40 -
ASAHI KASEI
[AK4342]
4342
XXXX
1
XXXXX : Date code identifier (4
Date (YY/MM/DD)
06/04/26
06/05/09
Revision
00
01
Reason
Page
)
Contents
39
Figure 32: PVDD, HVDD pin
2Ω
Note: “HVDD pin PVDD pin
2Ω
”
06/07/07
02
24
3. Power-up/down;
PTS1-0 bit
Î
PUT1-0
bit
3. Power-up/down;
PTS1-0 bit
Î
PUT1-0
bit
Power-Up/Down Sequence
Figure 20:
(4)
27
MS0506-J-02
2006/07
- 41 -
ASAHI KASEI
[AK4342]
•
•
•
•
•
•
MS0506-J-02
2006/07
- 42 -