[AK4184A] AK4184A TSC with Keypad Scanner and GPIO Expander GENERAL DESCRIPTION The AK4184A is a 12-bit A/D converter witch operates 125kHz (max) sampling rate with a 4-wire resistive touch screen controller (TSC), including low-on resistance switches, touch pressure measurement capability, a maximum 6 x 5 keypad scanner, eight GPIO ports, and a PWM generator for LED contrast control. The AK4184A operates down to a 2.5V supply voltage, and it tolerates digital I/O interface voltage from 1.6V to AVDD in order to connect to low voltage controllers. The AK4184A supports SPI interface for communication to a host controller. The AK4184A is available in a 41-pin BGA package and it operates over a temperature range of -40°C to +85°C. The AK4184A is suitable for Cellular Phone, DSC, DVC, Smart Phone and MP3 player application systems. FEATURES SPI Serial Interface 12 bit SAR A/D Converter with S/H Circuit 4-wire Resistive Touch Screen Interface Sampling Frequency: 125 kHz (max) Pen Pressure Measurement 6 x 5 Keypad Scanner 8 GPIO Ports PWM Generator for LED Bias Control Power Supply: AVDD = 2.5V ∼ 3.6V IOVDD = 1.6V ∼ AVDD (Digital I/F) Low Power Consumption: 400μA Package: 41pin BGA (4mm x 4mm, pitch 0.5mm) MS0947-E-00 2008/04 -1- [AK4184A] C1 C2 C3 C4 C5 C6 R1 R2 R3 R4 GP0 GP1 GP2 GP3 R5 GP4 Keypad Scanner GPIO I/F GP5 GP6 XP GP7 YP IOVDD Control Logic XN SCLK CSN YN DOUT VREF+ Serial Data I/F and Level Shifter VREF- DIN BUSY KEYIRQN AIN+ AIN- 12bit ADC (SAR type) PENIRQN PW M G e n e r a to r BRCONT PEN and Keypad INTERRUPT OSCILLATOR AVDD VSS1 RESETN VSS2 Figure 1. Block Diagram MS0947-E-00 2008/04 -2- [AK4184A] ■ Ordering Guide AK4184AEG −40 ∼ +85°C AKD4184A AK4184A Evaluation board 41pin BGA (4mm x 4mm, 0.5mm pitch) ■ Pin Layout (BGA 41pin) 7 6 AK4184AEG 5 Top View 4 3 2 1 A 7 6 5 4 3 2 1 NC C1 R4 R3 VSS2 IOVDD NC A C3 C4 C2 R5 R2 R1 KEYIRQN B B C D E F G C5 C6 BRCONT GP0 GP1 GP2 VSS2 BUSY DOUT C DIN SCLK D CSN RESETN E GP3 GP5 GP7 XP XN PENIRQN VSS1 F NC GP4 GP6 AVDD YP YN NC G TOP View MS0947-E-00 2008/04 -3- [AK4184A] PIN/FUNCTION No. A1 Pin Name NC I/O - B1 KEYIRQN O C2 BUSY O C1 DOUT O D2 DIN I D1 E2 SCLK CSN I I E1 F2 RESETN PENIRQN I O G1 NC - F1 G2 VSS1 YN I/O F3 XN I/O G3 YP I/O F4 XP I/O G4 AVDD - Function No Connection No internal bonding. This pin should be open or connected to the ground. Keypad Interrupt (Active Low) This pin is “L” on a key press (when the AK4184A is allowed to detect a key press). This pin is “H” after a debounce scan is completed. This is always “H” when the device is in key interrupt disable state. BUSY output Keypad scanner: This pin stays “H” when the keypad scanner is on the debounce scan. Touch Screen controller: This pin stays “H” from the end of sampling time to the timing of the MSB data out. Serial Data Output Data is clocked at SCLK falling edge. DOUT pin is “L” when this part does not produce data at the CSN=“L”. This pin is Hi-Z when CSN keeps “H”. Serial Data Input Data is clocked on the rising edge of SCLK. Must keep “L” while not issuing command. External Clock Input Chip Select Input (Active Low) Enables writing data to registers when CSN pin = “L”. Device Reset (Active Low) Pen Interrupt Output (Active Low) PENIRQN pin is “L” when touch-screen pressed is detected and the CSN pin is “H”. This pin is “H” irrespective of touch screen press when pen interrupt is not enabled. The state is dependent upon power down mode. See Power-down control and Pen Interrupt for reference. No Connection No internal bonding. This pin should be open or connected to the ground. Analog Ground Touch Screen Y- plate Voltage Supply Y axis measurement: Supplies voltage to the Y- position input X axis measurement: OPEN state Pen Pressure Measurement: This pin is the input for the A/D converter for Z2 measurement. Pen Waiting State: connected to GND. Touch Screen X- plate Voltage Supply X axis measurement: Supplies voltage to the X- position input Y axis measurement: OPEN state Pen Pressure Measurement: Supplies the voltage to X- position input of the touch panel Pen Waiting State: OPEN state Touch Screen Y+ plate Voltage Supply X axis measurement: Supplies voltage to the X- position input Y axis measurement: OPEN state Pen Pressure measurement voltage supply Pen Waiting State: OPEN state Touch Screen X+ plate Voltage Supply X axis measurement: Supplies voltage to the X+ position input Y axis measurement: This pin is used for the input to the A/D converter Pen Pressure measurement: This pin is the input for the A/D converter for Z1 measurement. Pen Waiting State: Pulled up by an internal resistor (typ.50KΩ). Analog Power Supply: 2.5V ~ 3.6V MS0947-E-00 2008/04 -4- [AK4184A] F5 G5 F6 G6 G7 GP7 GP6 GP5 GP4 NC I/O I/O I/O I/O - F7 E6 E7 D6 D7 C6 C7 B6 A7 GP3 GP2 GP1 GP0 BRCONT C6 C5 C4 NC I/O I/O I/O I/O O O O O - B7 B5 A6 B4 A5 C3 A4 B3 A3 B2 A2 C3 C2 C1 R5 R4 VSS2 R3 R2 VSS2 R1 IOVDD O O O I I I I I - GPIO7 pin GPIO6 pin GPIO5 pin GPIO4 pin No Connection No internal bonding. This pin should be open or connected to the ground. GPIO3 pin GPIO2 pin GPIO1 pin GPIO0 pin Pulse width modulated output signal Keypad Column 6 Keypad Column 5 Keypad Column 4 No Connection No internal bonding. This pin should be open or connected to the ground. Keypad Column 3 Keypad Column 2 Keypad Column 1 Keypad Row 5 Keypad Row 4 Digital I/O Ground Keypad Row 3 Keypad Row 2 Digital I/O Ground Keypad Row 1 Digital I/O Power Supply: 1.6V ~ AVDD MS0947-E-00 2008/04 -5- [AK4184A] ■ Handling of Unused Pin The unused I/O pins must be processed appropriately as below. Classification Digital Pin Name GP0 ~ GP8, R1 ~ R5 C1 ~ C6, BRCONT Setting These pins should be open. These pins should be open. ABSOLUTE MAXIMUM RATINGS (VSS1, VSS2 = 0V: Note 1) Parameter Power Supply Analog (Note 2) Digital I/F Input Current (any pins except for supplies) Analog Input Voltage (Note 3) Digital Input Voltage (Note 4) Touch Panel Drive Current Ambient Temperature (power supplied) Storage Temperature Symbol AVDD IOVDD IIN VINA VIND IOUTDRV Ta Tstg min -0.3 -0.3 -0.3 -0.3 -40 -65 max 6.0 6.0 ±10 AVDD+0.3 or 6.0 IOVDD+0.3 or 6.0 50 85 150 Units V V mA V V mA °C °C Note 1. All voltages with respect to ground. Note 2. VSS1 and VSS2 must be connected to the same analog ground plane. Note 3. XP, YP, XN, YN pins. Max is smaller value between (AVDD+0.3)V or 6.0V. Note 4. DIN, CSN, SCLK, RESETN, R1 ~ R5, GP0 ~ GP7 pins. Max is smaller value between (IOVDD+0.3)V or 6.0V. Pull-up resistors on BRCONT pin and GP0 ~ GP7 pins should be connected to (IOVDD+0.3) V or less voltage. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMEND OPERATING CONDITIONS (VSS1, VSS2 = 0V: Note 1) Parameter Power Supplies Digital I/O Power Supply Symbol AVDD IOVDD min 2.5 1.6 typ 3.3 3.3 max 3.6 AVDD Units V V Note 1. All voltages are with respect to ground. WARNING: AKEMD assumes no responsibility for the usage beyond the conditions in this datasheet. MS0947-E-00 2008/04 -6- [AK4184A] ANALOG CHARACTERISTICS Ta = -40°C to 85°C, AVDD = IOVDD = 3.3V, fs = 125 KHz, fSCLK=5MHz Parameter min ADC for Touch Screen Resolution No Missing Codes 11 Integral Nonlinearity (INL) Error Differential Nonlinearity (DNL) Error Offset Error Gain Error Touch Panel Drivers Switch On-Resistance XP, YP, RL = 300Ω XN, YN, RL = 300Ω XP Pull Up Register (when pen interrupt enable) Power Supply Current Touch Screen only fs = 125KHz (PD bit = “0”) Touch Screen only fs = 125KHz (PD bit = “1”) Oscillator on, Touch Screen Driver off, A/D power down Full Power Down (all blocks power down when CSN = “H”, RESETN = “H”) DC CHARACTERISTICS (Logic I/O) Ta = -40°C to 85°C, IOVDD = 1.6V to 3.6V Parameter Symbol min Digital Input (CSN, SCLK, DIN, R1 ~ R5, GP0 ~ GP7 pins) “H” level input voltage VIH 0.8xIOVDD “L” level input voltage VIL Input Leakage Current IILK -10 Digital Output (DOUT, BUSY, BRCONT, PENIRQN, KEYIRQN pins) VOH IOVDD-0.4 “H” level output voltage (@ Iout = -250μA) VOL “L” level output voltage (@ Iout = 250μA) Digital Output (GP0 ~ GP7 pins) “H” level output voltage (@ Iout = -1.5mA) VOH IOVDD-0.4 “L” level output voltage (@ Iout = 1.5mA) VOL Digital Output(C1 ~ C6) “H” level output voltage (@ Iout = -1.5mA) VOH IOVDD-0.4 Resistance Rkey Pulldown Resistance (R1 ~ R5 pins) Rgp Pulldown Resistance (GP0 ~ GP7 pins @ input) Tri-state Leakage Current IOLK All pins except for XP, YP, XN, YN pins -10 XP, YP, XN, YN pins -50 MS0947-E-00 typ max Units 12 12 ±1 - ±2 ±6 ±4 Bits Bits LSB LSB LSB LSB 10 10 50 - Ω Ω KΩ 400 500 72 0 680 850 120 5 μA μA μA μA typ max Units - 0.2xIOVDD 10 V V μA - 0.4 V V - 0.4 V V - - V 16 1000 - KΩ KΩ - 10 50 μA μA 2008/04 -7- [AK4184A] SWITCHING CHARACTERISTICS Ta = -40°C to 85°C, AVDD = 2.5V to 3.6V, IOVDD = 1.6V to AVDD, CL = 20pF Parameter Symbol min Internal oscillator frequency fosc 0.9 Touch Panel (A/D Converter) SCLK period tCP 200 tSam 1.5 Sampling Time (Rin = 600Ω) Throughput Rate fs Conversion Time tCONV 24 Timing Characteristics SCLK Pulse Width Low tCKL 80 Pulse Width High tCKH 80 CSN “↓” to First SCLK “↓” tCSS 300 CSN “↓” to DOUT Tri-State Disabled tDV Data Setup Time tDS 40 Data Hold Time tDH 40 Data Output Delay after SCLK“↓” tDD CSN “↑” to DOUT Hi-Z state tCDZ CSN “H” Time tCSW 150 SCLK “↑” to CSN “↑” tCSH 50 Reset Timing RESETN Pulse Width (Note 5) tRST 20 Note 5. Device is reset by pull RESETN pin to “L”. typ 1.3 max 1.7 Units MHz - 1000 125 - ns μs KHz tCP - 50 50 70 - ns ns ns ns ns ns ns ns ns ns - - µs tCSW VIH VIL CSN tCP tCSH tDD tCKH tCSS VIH VIL SCLK tCKL tDS tDH VIH VIL DIN tCDZ tDV DOUT D11 D10 D0 Hi-Z Hi-Z Figure 2. Timing Diagram tRST RESETN VIL Figure 3. Power-down & Reset Timing MS0947-E-00 2008/04 -8- 50%IOVDD [AK4184A] OPERATION OVERVIEW The AK4184A consists of the following blocks: z 4-wire resistive touch screen controller interface z 6 columns by 5 rows keypad interface z 8 GPIO pins z PWM control circuit for LED bias control z Successive approximation resister (SAR) A/D converter z Pen interrupt and key interrupt circuit z Oscillation circuit AK4184A interfaces to the host processor through standard SPI™ serial interface. SPI™ is the trademark of Motorola. ■ Touch Screen A/D Converter The AK4184A incorporates a 12-bit successive approximation resistor (SAR) A/D converter for determining the touch position and pressure measurement. The architecture is based on a capacitive redistribution algorithm, and an internal capacitor array functions as the sample/hold (S/H) circuit. The SAR A/D converter output is in straight binary format as shown below: Input Voltage Output Code (ΔVREF - 1.5LSB) ~ ΔVREF FFFH (ΔVREF - 2.5LSB) ~ (ΔVREF - 1.5LSB) FFEH ----------------0.5LSB ~ 1.5LSB 001H 0 ~ 0.5LSB 000H ΔVREF: (VREF+) – (VREF-) Table 1. Output Code MS0947-E-00 2008/04 -9- [AK4184A] ■ Touch Screen Position Detection XY-coordinate detection (XY-position) from the touch panel is determined by the control command (A1, A0) bits of the touch screen control command. Coordinate detection is in differential mode. The full scale (ΔVREF) is the differential voltage between the non-inverting terminal and the inverting terminal of the measured axis (e.g. X-axis measurement: ΔVREF = VXP – VXN). The input (ΔAIN) of the A/D converter is the voltage between the non-inverting terminal (VXP) of the non-target axis and the inverting terminal (VXN) of the target axis. (E.g. ΔAIN = (AIN+) - (AIN) = VYP – VXN) The input voltage charges the internal capacitor during the sampling time period. No current flows into the internal capacitors after the capacitor has been fully charged. The required settling time to charge the internal capacitor array needs at least 1.5μs. The maximum throughput of the A/D converter is 125kHz. The position from the touch screen is detected by taking the voltage of one axis when the voltage is supplied between the two terminals of another axis. At least two A/D conversions are needed to get the two-dimensional (X/Y axis) position. AVDD AVDD X-Plate XP-Driver SW ON XP VREF+ XP Y-Plate AIN+ VREF+ YP ADC VREF- X-Plate YP-Driver SW ON AIN+ YP ADC AIN- Y-Plate VREF- AIN- XN XN XN-Driver SW ON YN YN-Driver SW ON a) X-Position Measurement Differential Mode YN Touch Screen b) Y-Position Measurement Differential Mode The X-Plate and Y-plate are connected on the dotted line when the panel is touched. XP X-Plate (Top side) XN YN Y-Plate (Bottom side) YP c) 4-wire Touch Screen Figure 4. Axis Measurement MS0947-E-00 2008/04 - 10 - [AK4184A] ■ Pen Pressure Measurement Touch screen pen pressure can be derived from the measurement of the contact resistor between two plates. The contact resistance depends on the size of the depressed area and the pressure. The area of the spot is proportional to the contact resistance. This resistance (Rtouch) can be calculated using two different methods. The first method is when the total resistance of the X-plate sheet is already known. The resistance, Rtouch, is calculated from the results of three A/D conversions: X-position, Z1-Position, and Z2-Position, using the following formula: Rtouch = (Rxplate) * (Xposition/4096) * [(Z2/Z1) – 1] The second method is when both the resistances of the X-plate and Y-plate are known. The resistance, Rtouch, is calculated from the results of three A/D conversions: X-position, Y-Position, and Z1-Position, using the following formula: Rtouch = (Rxplate * Xposition/4096) * [(4096/Z1) – 1] – Ryplate * [1 – (Yposition/4096)] AVDD AVDD YP-Driver SW ON YP-Driver SW ON YP XP VREF+ AIN+ VREF- AIN- YP Rtouch XP ADC VREF+ AIN+ VREF- AIN- Rtouch ADC XN XN-Driver SW ON XN XN-Driver SW ON YN a) YN b) Z1-Position Measurement Z2-Position Measurement Figure 5. Pen Pressure Measurements MS0947-E-00 2008/04 - 11 - [AK4184A] ■ Keypad Scanner The AK4184A keypad scanner is designed to interface to a matrix type keypad with 5 rows x 6 columns (30keys or fewer) to the host controller. The KPMASK1, 2 and KPColumnMask register enable the masking of certain keys or a whole column of the keypad when any keys less than 30 keys or any columns less than 6 columns are not utilized. ■ Keypad Interrupt Detection When the AK4184A is in key interrupt enabled mode, C1 ~ C6 pins are designed to output “H” and R1 ~ R5 pins are designed to pull to GND via Rkey (Rkey=16kΩ typ, Figure 5). When a key is pressed a related R1 ~ R5 pins go to “H” and the KEYIRQN pin goes “L”. The KEYIRQN pin returns “H” after key press scan is completed. The KEYIRQN pin does not go “L” again until the host reads the keypad read register (KPDATA1 or KPDATA2). ■ Keypad Scan Data Read The AK4184A starts scanning key condition in sequence and writes each keypad state to the registers after a keypress is detected. First the C1 pin goes to “H” (Scan Output1) and the C2 ~ C6 pins are in Hi-Z state. Certain R1 ~ R5 pins are connected to C1 and pulled “H”. The R1 ~ R5 pins return to “L” after the key-press is released. The AK4184A reads R1 ~ R5 pins level (Sense Input 1 through 5) and loads the keypad data into the register. When two keys are pressed simultaneously, the associated row pins go “H” at the same time. Then the AK4184A C2 pin goes to “H” (Scan Output2), and reads and loads the R1 ~ R5 pin levels into the register (Sense Input 1 through 5). The same sequence as Scan Output 1 repeats up to Scan Output 6. The AK4184A makes this Scan Output and Sense Input pattern and loads the keypad-data into the register for unmasked columns. Debounce key scan performs a series of the Scan Output/ Sense Input at the end of the debounce time interval, then the AK4184A loads the key pad data into the resister. μ-Processor starts to read the data register after confirming if the keypad scan completed. New keypad scan does not repeat again until the Host reads the keypad data. MS0947-E-00 2008/04 - 12 - [AK4184A] Scan Output 6 Scan Output 5 Scan Output 4 Scan Output 3 Sense Input 1 through 5 Scan Output 2 Scan Output 1 Drive High or Hi-Z STATE C1 R1 C2 C3 C4 C5 C6 1 6 11 16 21 26 2 7 12 17 22 27 3 8 13 18 23 28 4 9 14 19 24 29 5 10 15 20 25 30 Rkey R2 Rkey R3 Rkey R4 Rkey R5 Rkey Rkey=16KΩ(typ.) Figure 6. Key Press Detection Circuitry and KEY Number Key pressed Rx Signal from keypad Debounce Scan Store the Key value in the KPDATA1, the KPDATA2 Register Key debounce time interval Time Oscillator startup Figure 7. Debounce Time Interval MS0947-E-00 2008/04 - 13 - [AK4184A] ■ Digital Interface The AK4184A supports a SPI bus system. The Host processor starts to communicate with the serial clock. The digital interface can be operated from 1.6V, which enables connecting with a low voltage host controller. The full scale level of the digital I/O voltage is specified IOVDD. Touch Panel AVDD=2.5V ~ 3.6V X-Plate (Top side) IOVDD=1.6V~AVDD IOVDD AK4184A XP CSN TP Interface XN YN YP SCLK KP Interface DIN GPIO port DOUT BRCONT PENIRQN KEYIRQN μP Y-Plate (Bottom side) 8 GPIO 6x5 KEYPAD LED Driver Figure 8. Typical peripheral connection diagram The AK4184A is controlled by reading from and writing to registers through the 4-wire serial interface (CSN, SCLK, DIN, and DOUT pins). The data is composed of control command, control data, and readout data. The transmitter sends each bit on the falling edge of the SCLK pin and the receiver latches on the rising edge of SCLK. The first 16 bits after the falling edge of the CSN pin contains the control command followed by 16 bits of control data during the write operation, or 16 bits of readout data during the read operation before the rising edge of the CSN. This completes a write or read operation. The max clock speed of the SCLK pin is 5MHz. The register value is reset by pulling RESETN pin to “L”. The control command layout is shown in Table 2. The upper 8-bit word is the touch screen control command. The next lower 8-bits [D7:D0] are filled with “0” when accessing the touch screen block. The lower 8 bit word is composed of other block control commands, which specify control of the Keypad, GPIO, and PWM output. When accessing touch panel functions, the lower 8-bit word [D7:D0] is filled with “0” data. When accessing Keypad, GPIO, or PWM control, the upper 8-bit word [D15:D8] is filled with “0” data. This command begins with the S bit which specifies access to the touch screen block. The S bit must be set to “1”. The touch screen command begins with the A1:A0 bits, which select the measurement axis (X, Y, and Z). The PD bit specifies power down control of the touch screen driver and the A/D converter. When controlling other blocks, the first bit is a W/R bit, which specifies the direction of data flow on the bus. The next bit specifies the page bit of the register, which is the data register and the control register as shown in Table 3. The data of the next 6 bits are the address specified in the register. The page and address of the register is shown in Table 4. The next 16 bits are data that are read from or written to the register in Table 4. 32 SCLK cycles are necessary for both read and write operations. MS0947-E-00 2008/04 - 14 - [AK4184A] D15 D14 D13 D12 D11 D10 D9 Touch Screen Control Command Byte S A1 A0 PD x x x MSB D8 x D7 D6 D5 D4 D3 D2 D1 D0 Other(Keypad, GPIO, LCD bias) Control Command Byte W/R PAGE ADDR[5:0] LSB Table 2. Control Command (x: don’t care) PAGE Description 0 Data Register 1 Control Register Table 3. Page Address PAGE Addr Register Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 00H KPDATA1 DERR KD3[4] KD3[3] KD3[2] KD3[1] KD3[0] KD2[4] KD2[3] KD2[2] KD2[1] KD2[0] KD1[4] KD1[3] KD1[2] KD1[1] KD1[0] 0 01H KPDATA2 SERR KS2[4] KS2[3] KS3[2] KS3[1] KS3[0] KS2[4] KS2[3] KS2[2] KS2[1] KS2[0] KS1[4] KS1[3] KS1[2] KS1[1] KS1[0] 0 02H -FH Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10H GPLR 0 0 0 0 0 0 0 0 GPD7 GPD6 GPD5 GPD4 GPD3 GPD2 GPD1 GPD0 0 11H3FH Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 00H KEY KST1 KST0 DBN2 DBN1 DBN0 HLD2 HLD1 HLD0 0 0 0 0 0 0 0 0 1 01H KPMASK1 0 KM15 KM14 KM13 KM12 KM11 KM10 KM9 KM8 KM7 KM6 KM5 KM4 KM3 KM2 KM1 1 02H KPMASK2 0 KM30 KM29 KM28 KM27 KM26 KM25 KM24 KM23 KM22 KM21 KM20 KM19 KM18 KM17 KM16 1 03H KPColumnMask 0 0 0 0 0 0 0 0 0 0 CM6 CM5 CM4 CM3 CM2 CM1 1 04H KPScanInitiate 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 05H07H Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 08H PDCTRL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KPPD TPPD 1 09H0FH reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 10H GPSCR 0 0 0 0 0 0 0 0 SC7 SC6 SC5 SC4 SC3 SC2 SC1 SC0 1 11H GPDR IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 0 0 0 0 0 0 0 0 1 12H GPPU PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 0 0 0 0 0 0 0 0 1 13H GPSR PS7 PS6 PS5 PS4 PS3 PS2 PS1 PS0 0 0 0 0 0 0 0 0 1 14H17H Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 18H PWMCTL LPU 0 0 BRV[4] BRV[3] BRV[2] BRV[1] BRV[0] 0 PACT 0 0 0 DIV2 DIV1 DIV0 1 19H3FH Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 4. AK4184A Register Map MS0947-E-00 2008/04 - 15 - [AK4184A] ■ System Reset Upon power-up, all blocks of the AK4184A must be reset by the RESETN pin = “L”. This ensures that all internal registers are reset to their initial values (0000H). The touch screen control data is set to X-measurement and auto driver off (A1 bit=A0 bit = PD bit=“0”). Internal state is fixed and the pen interrupt function is enabled. If the AVDD and IOVDD are supplied separately, the power up sequence is not critical. ■ Touch Screen Control Command The control command (4 bits) provided to the AK4184A via DIN is shown in Table 5. This command includes a start bit, channel selection of ADC input, power-down mode of ADC and the next 12bits (written by “0” data). The AK4184A latches the serial command on the rising edge of SCLK. Detail information regarding the bit order, function, status of the driver switch, ADC input and reference voltage are shown in Table 6 and Table 7. D15 S D14 A1 D13 A0 D12 PD D11 0 D10 0 D9 0 D8 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 Table 5. Touch Screen Command Word Format Bits 15 14:13 Name S A1-A0 12 11:0 PD Input S 1 1 1 1 A1 0 0 1 1 A0 0 1 0 1 Function Start Bit. This bit must be “1” Channel Selection Bits. Analog inputs to the A/D converter and the activated driver switches are selected. (Table 7) Power-down Mode (Table 8) Reserved Table 6. The definition of touch screen control data Status of Driver Switch ADC input Reference Voltage (ΔAIN) (ΔVREF) XP XN YP YN AIN+ AIN- VREF+ VREFON ON OFF OFF YP XN XP XN OFF OFF ON ON XP YN YP YN OFF ON ON OFF XP(Z1) XN YP XN OFF ON ON OFF YN(Z2) XN YP XN Table 7. Status of Driver Switch MS0947-E-00 Note X-axis Y-axis Z1 (Pen Pressure) Z2 (Pen Pressure) 2008/04 - 16 - [AK4184A] ■ Power-down Control The power-down state of A/D converter and the touch screen driver switches is controlled by the PD bit. PD PENIRQN Function 0 Enabled Auto Driver Power Off Mode. When PD bit is “0”, the touch screen driver switches and the A/D converter are automatically powered up at the start of sampling, and moves to power- down state automatically at the rising edge of CSN. The AK4184A is always powered down when CSN is “H”. All touch screen driver switches except for the YN switch are turned off, and relative pins are in open state. Only the YN driver switch is turned ON, and the YN pin is forced to ground. The pen interrupt function is enabled except when CSN is “L”. See “ Pen Interrupt” for detail. 1 Disabled ADC ON Mode When PD bit is “1”, the touch screen driver switches and the A/D converter are always turned ON. The pen interrupt function is disabled and the PENIRQN pin is always “H”, regardless of the pen touch. The touch panel driver turns on before sampling time starts so that the touch panel voltage fed into A/D converter is stable in this mode. The sampling time starts at the falling edge of CSN this is effective if more settling time is required to suppress the electrical bouncing of touch plate. Table 8. Power-down Control A/D converter is power-down both when the CSN pin is “H” and controlling with keypad scanner, GPIO block, PWM controller. A/D converter is power-up when issues touch panel command at the CSN pin is “L”. MS0947-E-00 2008/04 - 17 - [AK4184A] ■ Touch Screen Control Sequence The timing of sampling and A/D conversion is shown in Figure 8. The AK4184A is controlled through a standard SPI serial interface (CSN, SCLK, DIN, and DOUT pins). BUSY and DOUT are in Hi-Z state when CSN = “H”. The AK4184A latches the 4-bit control word serially via DIN on the rising edge of SCLK. DIN must be low until CSN is “H”. The S bit must be “1”. The sampling (Sampling1 or Sampling2) time for the A/D converter depends on the PD bit. The SAR-A/D conversion is synchronized with SCLK. The A/D conversion occurs between the falling edge of the sixth SCLK and the 20th SCLK, followed by a 12-bit serial data output. Sampling time is determined by the PD bit. If a series of the measurements are the same and the previous PD bit is “0”, sampling occurs between the falling edge of the third SCLK and the sixth SCLK (Sampling2). When the previous PD bit is “1”, sampling occurs between the falling edge of CSN to the falling edge of the sixth SCLK (Sampling1+Sampling2). This is a longer sampling time. If the measurements switch to another axis, the measurement axis is determined by the current setting of the [A1, A0] bits, irrespective of the PD bit setting. Even through the previous PD bit is “1”, the valid sampling time is Sampling2 as shown in Figure 9. Sampling time depends on SCLK and the source impedance. When the A/D input voltage does not reach the final voltage during Sampling2, continue to measure the same axis with the PD bit = “1” or use a slower SCLK in order to increase the settling time. The BUSY pin stays “H” from beginning of the A/D conversion to the beginning of MSV data output (20th falling edge of SCLK). BUSY is “L” for the other period. The AK4184A outputs A/D data with MSB first via DOUT from the rising edge of the 21st SCLK. CSN 1 2 3 4 5 6 7 8 9 14 16 17 18 19 20 21 22 23 24 25 29 30 31 32 SCLK A/D conversion DIN A1 A0 PD S 0 Control Command Hi-Z D11 D10 D9 D8 D4 D3 D2 D1 D0 DOUT Hi-Z A/D Data Touch Screen Driver SW Current PD bit Previous PD bit Sampling2 PD = “1” PD = “0” PD = “0” Sampling1 + Sampling2 PD = “1” PD = “1” PD = “0” Figure 9. Touch Screen Operation MS0947-E-00 2008/04 - 18 - [AK4184A] ■ Pen Interrupt The AK4184A has a pen interrupt function to detect a pen touch. The pen interrupt function is enabled during powerdown state. The YN pin is connected to GND during the pen interrupt enabled state. The XP pin is pulled up via an internal resistor (Ri), typically 50kΩ. If the touch plate is pressed by a pen, the current flows via <AVDD> - <Ri> <XP> - <the plates> - <YN>- <GND>. The resistance of the plate is generally several hundreds, and PENIRQN pin is forced to a “L” level. If the pen is released, the PENIRQN pin returns to a “H” level because two plates are disconnected, and the current doesn’t flow between the two plates. The PENIRQN pin is a buffer type. The “H” level is specified by IOVDD. The operation of PENIRQN is related to PD bit. The pen interrupt function is disabled and stays “H” irrespective of the pen touch when the PD bit is “1”. When the PD bit is “0”, the PENIRQN pin is forced “H” from the falling edge of the sixth SCLK to the rising edge of CSN. The pen interrupt function is valid when the CSN pin is “H”. The PENIRQN pin stays low when the touch panel is pressed, and stays high when the touch panel is not pressed. The pen interrupt function is determined by the present PD bit setting when the host writes to or reads from the register other than the pen touch block. The touch panel block is able to power down when the TPPD bit is “1” (Table 25). All the touch panel drivers turn off in this state and the pen interrupt function is not valid. The current through the touch screen does not flow even through the panel is pressed. IOVDD AVDD PENIRQN AVDD Ri = 50kΩ EN Driver OFF XP YN Driver ON Figure 10. PENIRQ Functional Block Diagram MS0947-E-00 2008/04 - 19 - [AK4184A] ■ Keypad, GPIO, LED Contrast Control The control command format for accessing the keypad scanner, GPIO, and LED contrast control is described in Table 10. The sequence of writing to and reading from the registers is shown in Table 12, Table 13. The upper MSB byte (touch screen command) of the control command is set to zero when assessing these blocks. Refer to Table 4 for the control and read data formats. D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 0 D7 W/R D6 PAGE D5 D4 D3 D2 D1 ADDR[5:0] D0 Table 9. Keypad, GPIO, LED Contrast Control Command Format 1. Bits 7 Name W/R 6 PAGE 5:0 ADDR Description Write/Read bit 0: Write 1: Read Page bit (Table 3) Address bit (Table 4) Table 10. Control Command Write Operation CSN 1 2 3 8 9 10 11 12 13 14 15 16 17 18 19 25 26 27 28 29 30 7 6 5 4 3 2 31 32 1 0 SCLK DIN ADDR[5:0] W/R Page 15 14 13 8 Control Data Control Command DOUT Hi-Z Hi-Z “0” Figure 11. Write Operation 2. Read Operation CSN 1 2 3 8 9 10 11 12 13 14 15 16 17 18 19 25 26 27 28 29 30 7 6 5 4 3 2 31 32 1 0 SCLK DIN W/R Page ADDR[5:0] Control Command DOUT Hi-Z 15 14 13 “0” 8 Hi-Z Read Data Figure 12. Read Operation MS0947-E-00 2008/04 - 20 - [AK4184A] ■ Keypad Scanner The AK4184A has a keypad interface which supports maximum Keypad matrix of six columns by five rows. ■ Keypad Measurement Mode Setting the KST1 bit = “0” (default) enables the AK4184A to monitor key-press detection and move to key pad measurement mode after keypad detection. The AK4184A provides two different keypad measurement modes by setting the KST0 bit: host scan mode and key press scan mode. ■ Host Scan Mode When the KST0 bit is “1” the mode is host scan mode, pressing the keypad down makes the AK4184A outputs a keypad interrupt signal (KEYIRQN pin goes low), and then the AK4184A move to the state which waits for a KPScanInitiate (Page1, Address 04H) command from host. The internal oscillator turns off until receiving this command, and the AK4184A does not execute key scan. Keypad scan begin when receiving a KPScanInitiate command. Once receiving this command, the AK4184A turns on the internal oscillator and starts keypad debounce scan. ■ Key press Scan Mode When the KST0 bit is “0” key press scan mode is enabled. Pressing the keypad down causes the AK4184A to output a keypad interrupt signal (KEYIRQN pin goes low) and the AK4184A starts a keypad debounce scan automatically. The keypad data register (KPDATA1, KPDATA2) is revised after completing a debounce scan. The KEYIQRN pin goes to “H” and the AK4184A goes to hold state. Key press detect function is disabled during the hold time. When the host processor reads the keypad data register during hold time, the hold time counter is reset and restarted after being read by the host processor. Key press detection is not valid until the host processor reads the keypad data register after hold time is passed. Reading a keypad date is determined by accessing KPDATA1, KPDATA2 register. Reading the KPDATA1 or KPDATA2 registers is required when key press interrupts of the AK4184A become valid. The hold time and the debounce time are controlled through the keypad control register (KEY). Keypad Debounce Scan initiated by Host (Initial : KST1 bit="0", KST0 bit="1") Ry KEYIRQN BUSY CSN KPScanInitiate KPScanInitiate DIN KPDATA1,2 KPDATA1,2 DOUT State Key Detect Enable wait Debounce Scan HOLD Key Detect Disable Debounce Scan HOLD Key Detect when Host reads the keypad data during Enable then wait the hold time, the hold time counter will reset after keypad data is read completly. Figure 13. Timing Diagram for keypad debounce scan initiated by Host (Initial: key interrupt enable, wait for Host instruction) MS0947-E-00 2008/04 - 21 - [AK4184A] Keypad Debounce Scan initiated by keypad activity (Initial : KST1 bit="0", KST0 bit="0") Ry KEYIRQN BUSY CSN KPDATA1,2 DOUT Key Detect Enable State Debounce Scan HOLD Key Detect Disable Debounce Scan HOLD Key Detect Enable then wait Figure 14. Keypad Debounce Scan initiated by key activity (Key interrupt enable, key scan initiated by key touch) ■ Keypad Control Register (PAGE 1) The keypad scanner controller is controlled by the Keypad Control register (Table 12), Keypad Mask register (Table 17 ) and Keypad Column register (Table 19). This register controls the key press interrupt (host scan mode or key-press scan mode), key-press debounce time interval and hold time. The Keypad Mask register is valid for each key masked after debounce key scan. The Keypad Column Mask register stops a key scan of a selected key column and is disabled for the detection of key press. Addr NAME D15 MSB D14 00H KEY KST1 KST0 D13 D12 D11 D10 DBN[2:0] D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LSB 0 0 0 0 0 0 0 0 HLD[2:0] Table 11. Keypad Control Register Format Bits 15 Name KST1 14 KST0 13:11 10:8 7:0 DBN HLD Description Key Interrupt enable signal 0 : enable 1 : disable Key scan initiated by Host/Key 0 : scan starts by key-press 1 : scan starts by Host command Keypad debounce time interval Keypad hold time control Reserved Table 12. Keypad Control Register (Write) The KST1 and KST0 bits can be read to determine the state of keypad scanner. The KST1 and KST0 bits and their descriptions are described in Table 13. KST1 0 0 1 1 KST0 0 1 0 1 Description Keypad Debounce scan is busy. Wait for the command initiated by Host No detect Data available Table 13. KST bit (Read) MS0947-E-00 2008/04 - 22 - [AK4184A] The keypad debounce time interval is determined by [DBN2:DBN0]. The default setting is 1ms. DBN2 0 0 0 0 1 1 1 1 DBN1 DBN0 Function 0 0 Debounce time: 1ms (default) 0 1 Debounce time: 2ms 1 0 Debounce time: 5ms 1 1 Debounce time: 10ms 0 0 Debounce time: 20ms 0 1 Debounce time: 50ms 1 0 Debounce time: 80ms 1 1 Debounce time: 100ms Table 14. Keypad Debounce Time Interval The keypad hold time is determined by [HLD2:HLD0]. The default setting is 100μs. HLD2 0 0 0 0 1 1 1 1 HLD1 0 0 1 1 0 0 1 1 HLD0 0 1 0 1 0 1 0 1 Function Wait 100μs for next Debounce scan (default) Wait 1 debounce time interval to the next debounce scan Wait 2 debounce time interval to the next debounce scan Wait 3 debounce time interval to the next debounce scan Wait 4 debounce time interval to the next debounce scan Wait 5 debounce time interval to the next debounce scan Wait 6 debounce time interval to the next debounce scan Wait 7 debounce time interval to the next debounce scan Table 15. Keypad Hold Time Control ■ Keypad Mask Register (PAGE 1) This register controls the key to be masked after a debounce key scan. The keypad mask register format is described in the following table. This register setting is valid for the data in the KPDATA2 register. Addr NAME D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 01H KPMASK1 0 KM15 KM14 KM13 KM12 KM11 KM10 KM9 KM8 KM7 KM6 KM5 KM4 KM3 KM2 KM1 02H KPMASK2 0 KM30 KM29 KM28 KM27 KM26 KM25 KM24 KM23 KM22 KM21 KM20 KM19 KM18 KM17 KM16 Table 16. Keypad Mark Register Format KMx 0 1 Description Disable keypad data masked (default) Enable keypad data masked Table 17. Keypad Mask bit The number of the keypad corresponds to each bit of this register .This relationship is shown in Table 24. KPMASK1, KPMASK2 default setting is 0000H (disable keypad data masked on KPDATA2) MS0947-E-00 2008/04 - 23 - D0 [AK4184A] ■ Keypad Column Mask Register (PAGE 1) The Keypad Column Mask Register format is shown in Table 19. This register allows a certain column to be masked from keypad detection. Addr NAME D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 03H KPColumnMASK 0 0 0 0 0 0 0 0 0 0 CM6 CM5 CM4 CM3 CM2 CM1 Table 18. Keypad Column Mask Register Format CMx 0 1 Description Enable key press detection for a certain column pin (default) Disable key press detection for a certain column pin Table 19. Keypad Column Mask bit ■ Keypad Scan Initiate Command (PAGE 1) When a key is pressed with the KST0 bit = “1”, the AK4184A does not start debounce and key scan, the Host Controller sends a keypad scan initiate command to the AK4184A. After receiving the command, the AK4184A starts a debounce scan, and the Host Controller can then read the data [D15:D0] from the keypad data register (KPDATA1, KPDATA2). When receiving the command the Keypad Data Resister (KPDATA1, KPDATA2) is reset to 0000H. Addr 04H NAME KPScanInitiate D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X X X X X X X X Table 20. Keypad Scan Initiate Command Format MS0947-E-00 2008/04 - 24 - X [AK4184A] ■ Keypad Data Register (PAGE 0) The keypad data register format is shown below. KD1, KD2, KD3, KS1, KS2 and KS3 represent the number of keys pressed. Table 24 shows a configuration of a 30-key keypad. Data of KD1, KD2, KD3, KS1, KS2 and KS3 returned as zero represents no key pressed. The AK4184A keypad scanner can be read out up to three keys simultaneously. The AK4184A key pad scanner writes the number of keys pressed in the keypad data register. For example: When two keys are pressed at the same time, the contents of the keypad register are filled with KD1, KD2, KS1, and KS2. KD3 and KS3 are the zero data. When more than four keys are pressed at the same time, error bits (DERR bit and SERR bit) are set to “1” and KD1, KD2, KD3, KS1, KS2, and KS3 data are set to 31. The keypad data can be read out either from the KPDATA1 register or the KPDATA2 register. The KPDATA1 register represents the keypad data masked by the keypad column mask register. KPDATA2 register represents the keypad data masked by both the keypad column mask register and the keypad mask register. KPDATA1 and KPDATA2 register are cleared after these resisters are read. Addr 00H 01H NAME KPDATA1 KPDATA2 D15 DERR SERR D14 D13 D12 D11 KD3[4:0] KS3[4:0] D10 D9 D8 D7 D6 KD2[4:0] KS2[4:0] D5 D4 D3 D2 D1 KD1[4:0] KS1[4:0] D0 Table 21. Keypad Data Register Format Bits 15 14:10 9:5 4:0 Bits 15 14:10 9:5 4:0 Name DERR KD3 KD2 KD1 Name SERR KS3 KS2 KS1 Description Keypad scan data error Keypad scan result 3. can be masked by column mask Keypad scan result 2. can be masked by column mask Keypad scan result 1. can be masked by column mask Table 22. Keypad Data 1 Register (addr: 00H) Description Keypad status data error Keypad status result 3. can be masked by both keymask and column mask Keypad status result 2. can be masked by both keymask and column mask Keypad status result 1. can be masked by both keymask and column mask Table 23. Keypad Data 2 Register (addr: 01H) The corresponding number and its keypad layout are shown on Table 24. C1 C2 C3 C4 C5 C6 #11 #16 #21 #26 R1 #1 #6 #12 #17 #22 #27 R2 #2 #7 #13 #18 #23 #28 R3 #3 #8 #4 #9 #14 #19 #24 #29 R4 R5 #5 #10 #15 #20 #25 #30 Table 24. Keypad to Key number Mapping MS0947-E-00 2008/04 - 25 - [AK4184A] ■ GPIO controller The AK4184A has eight ports [GP0:GP7] which can be configured as inputs or outputs for general purpose. Figure 15 shows a block diagram of a single GPIO pin. The GPIO Pin Direction register (GPDR) is used to program the GPIO pins as input or output. For a pin configured as output, use the GPIO pin pull-up register (GPPU) to set the pin type to either Open-Drain or CMOS, and use the GPIO Set/ Clear register (GPSCR) to set a pin level high or low. To validate the state of GP0 ~ GP7 pins, write to the GPIO pin state register (GPSR) to program the pin state as pulldown or Hi-Z and read the GPIO Pin Level register (GPLR) at any time even if the pin is configured as an output. The GPIO pin state is determined by these registers before writing and reading the pin level. The pin state set by default input, pull-down. Pin Direction (GPDR) Pin Pull-up (GPPU) Pin State (GPSR) Pin Set (GPSCR) GPIO Pin Pin Level (GPLR) Figure 15. General-Purpose I/O Block Diagram ■ GPIO Pin Set/ Clear Register (PAGE 1) The GPIO pin set/clear register sets the pin level when the pin is configured as an output (Table 28: IO bit = “1”). GPSCR is a write-only register. The actual pin level is read from the GPLR register. Addr 10H Name GPSCR D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 0 D7 SC7 D6 SC6 D5 SC5 D4 SC4 D3 SC3 D2 SC2 D1 SC1 D0 SC0 Table 25. GPIO Pin Set/ Clear Register Format Bits 15:8 7:0 Name Description Reserved Set GPIO Pin level for GPIO pins 0: Set pin level low (default) 1: Set pin level high Table 26. GPIO Pin Set/Clear Register SC ■ GPIO Pin Direction Register (PAGE 1 ) Whether a pin is input or an output is determined by the GPDR register. The GPDR contains one direction-control bit for each of the eight GPIO pins. Addr 11H Name GPDR D15 IO7 D14 IO6 D13 IO5 D12 IO4 D11 IO3 D10 IO2 D9 IO1 D8 IO0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 Table 27. GPIO Pin Direction Register Format Bits 15:8 7:0 Name IO Description GPIO Direction select 0: GPIO pin configured as input. (default) 1: GPIO pin configured as output. Reserved Table 28. GPIO Direction Register MS0947-E-00 2008/04 - 26 - [AK4184A] ■ GPIO Pin Pull-up Register (PAGE 1 ) The GPPU register determines the output pin type - either CMOS or Open drain. This register is valid for pins configured as outputs (IO bit = “1” in Table 28). Pull-up resistors on GP0 to GP7 pins must be connected to (IOVDD+0.3) V or lower voltage when the PUx bit is set to “1”. Addr 12H Name GPPU D15 PU7 D14 PU6 D13 PU5 D12 PU4 D11 PU3 D10 PU2 D9 PU1 D8 PU0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 Table 29. GPIO Pin Pull-up Register Format Bits 15:8 Name PU 7:0 Description GPIO Pullup register select 0: GPIO CMOS outputs (default) 1: GPIO Open drain outputs Reserved Table 30. GPIO Pull-up Register ■ GPIO Pin State Register (PAGE 1) The GPSR register determines the state of pins which are either pull-down or Hi-Z. This register is valid for pins configured as inputs (IO bit = “0”). Addr 13H Name GPSR D15 PS7 D14 PS6 D13 PS5 D12 PS4 D11 PS3 D10 PS2 D9 PS1 D8 PS0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 Table 31. GPIO Pin State Register Format Bits 15:8 Name PS 7:0 Description GPIO Pin state select 0: GPIO Pull-down (Rgp=1MΩ typ.) state (default) 1: GPIO pin Hi-Z state Reserved Table 32. GPIO Pin state Register ■ GPIO Pin Level Register (PAGE 0) The state of each GPIO pin can be determined by reading this register (GPLR). Each bit corresponds to one pin. Use the GPLR read-only registers to determine the current level of a certain pin irrespective of the programmed pin direction. The upper eight bits returns zero when read. Addr 10H Name GPLR D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 0 D7 GPD7 D6 GPD6 D5 GPD5 D4 GPD4 D3 GPD3 D2 GPD2 D1 GPD1 Table 33. GPIO Pin Level Register Format Bits 15:8 7:0 Name 0 GPD Description Reserved GPIO Pin Level bits for GPIO pins 0: Pin state is low 1: Pin state is high Table 34. GPIO Pin Level Register MS0947-E-00 2008/04 - 27 - D0 GPD0 [AK4184A] ■ LED contrast control The AK4184A contains an oscillator and a PWM control circuit for controlling the brightness of an LED by modulating the “on” time. The brightness is determined by the PWM basic frequency (fpwm) and duty cycles. The PWM block divides the internal oscillator frequency (fosc) and modulates this output. The range of PWM frequency (fpwm) is 80Hz minimum. The modulating range is provided by 32 duty cycle steps from the PWM logic controller. The output control is determined by the PACT bit. The duty cycle width of the PWM frequency is controlled by the BRV and DIV bits. The PWM signal stays constant on normal mode until duty cycle, PWM frequency changed. The output type is possible to select either CMOS or Open Drain, set by the LPU bit. After reset, the PWM block is in power-down state and the BRCONT pin outputs a “L” level. Oscillator fosc fpwm Divider 2 PWM Logic (DIV[2:0]+7) fbrcont BRCONT Controller Figure 16. PWM output block Example BRV [4:0] =11H setting Internal 0 PWM 1 2 3 8 9 10 11 12 13 14 15 16 17 18 PWM frequency(fpwm) = fosc / 2 Counter 8 24 25 26 27 28 29 30 31 0 (DIV[2:0]+7) BRCONT Duty Cycle BR[4:0] =11H Figure 17. PWM output waveform ■ PWM Control Register (PAGE 1) Addr Name 18H PWMCTRL D15 MSB LPU D14 D13 0 0 D12 D11 D10 BRV[4:0] D9 D8 D7 D6 D5 D4 D3 0 PACT 0 0 0 D2 D1 D0 LSB DIV[2:0] Table 35. PWM Control Register Format Bits 15 Name LPU 14:13 12:8 BRV 7 6 PACT 5:3 2:0 DIV Description Output type Open drain / CMOS 0: CMOS type (default) 1: Open Drain type Reserved Bright Control Value The period of “H” output level is (control value + 1) cycle in unit of (fpwm/32) Reserved Oscillator and PWM Logic Controller Power Up 0: Power Down State (default) 1: Normal mode (Oscillator power up and enable output) Reserved PWM clock divider index fpwm(typ.)=fosc/2[DIV + 7] Table 36. PWM Control Register MS0947-E-00 2008/04 - 28 - [AK4184A] ■ Power Down Register (PAGE 1) The power down register determines the power down control of the keypad scanner block and touch screen block. The power down state in the touch screen block (TPPD bit = “1”) holds all of the touch panel driver switches off, so that current cannot flow through the touch panel. The pen interrupt function is disabled and the PENIRQN pin always stays “H”, effective for reducing power consumption of the touch screen block. A power down state in the keypad scanner block (KPPD bit = “1”) holds all the C1 ~ C6 pins outputs “L”. By setting this bit = “1” stops key scanning and clears the keypad data register (KPDATA1, KPDATA2). The keypad function is restored after the keypad scanner block is powered up. The keypad interrupt is disabled at power-down. The power down control register format is shown here. Addr NAME D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 08H PDCTRL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KPPD TPPD Table 37. Power Down Register Format Bits Name 15:2 1 KPPD 0 TPPD Description Reserved Enable keypad block power up/down 0: power up (default) 1: power down Enable the touch screen control block power up/down 0: power up (default) 1: power down Table 38. Power Down Register MS0947-E-00 2008/04 - 29 - [AK4184A] SYSTEM DESIGN Figure 18 shows a system connection diagram for the AK4184A. The evaluation board [AKD4184A] is available, which demonstrates the optimum layout and power supply arrangement. LED Driver GPIO Keypad NC C3 C5 BRCONT C1 C4 C6 GP0 R4 C2 GP1 GP3 GP2 GP5 NC GP4 6x5 R3 0.1µ Digital I/O Supply 1.6∼AVDD + 10µ VSS2 GP7 R5 Top View R2 VSS2 IOVDD R1 BUSY NC KEYIRQN DOUT DIN GP6 Analog Supply 0.1µ XP AVDD XN YP CSN SCLK RESETN PEN IRQN YN VSS1 NC 0.01µ* 0.01µ* 0.01µ* 0.01µ* + 10µ 2.5∼3.6V 4-wire Touch Screen µP Note: - VSS1 and VSS2 of the AK4184A must be distributed separately from the ground of external controllers. - Do not allow digital input pins (CSN, SCLK, DIN pins) to float. - The DOUT pin is floating except when communicating with the host processor. A 100kΩ pull-down or pull-up register must be connected. Figure 18. Typical connection diagram ■ Attention to the PCB wiring The AK4184A requires careful attention to power and grounding. VSS1, VSS2 must be connected to analog ground system analog ground and digital ground must be connected together as close as possible to where the supplies are brought onto the printed circuit board. Decoupling capacitors must be as close to the AK4184A as possible, with the small value ceramic capacitor being the closest. When an EMI source is close to the touch panel analog signal line, EMI noise reduces analog performance characteristics. Noise canceling capacitors as close as possible to each pin (XP, XN, YP, YN pins) of the AK4184A should be connected to avoid this noise. (Figure 18) In addition, ESD protection devices should be mounted on the printed circuit board for countermeasure for surge and static electricity on the touch panel, GPIO and keypad signal lines. MS0947-E-00 2008/04 - 30 - [AK4184A] CONTROL SEQUENCE ■ X-, Y- Coordinate measurements Cycle repeat CSN pin X, 0 X, 1 repeat X, 0 Y, 0 Y, 1 Y, 0 X: X-measurement, Y: Y-measurement. 0: PD bit = “0” setting, 1: PD bit = “1” setting. Figure 19. Timing Sequence for detecting X, Y position MS0947-E-00 2008/04 - 31 - [AK4184A] ■ Keypad Scanner Flowchart 1. Host Scan Keypad Touch No Read KPDATA1,2 Register? Yes KEYIRQN pin Low Write KPScanInitiate Register Start Clock BUSY pin High Start Scanning & Debouncing keys Store scan results in KPDATA1, 2 Register BUSY pin Low Stop Clock KEYIRQN pin High Done Figure 20. Keypad scanner sequence initiated by Host command MS0947-E-00 2008/04 - 32 - [AK4184A] 2. Keypress scan mode Keypad Touch No Read KPDATA1,2 Register? Yes KEYIRQN pin Low Start Clock BUSY pin High Start Scanning & Debouncing keys Store scan results in KPDATA1, 2 Register BUSY pin Low Stop Clock KEYIRQN pin High Done Figure 21. Keypad scanner sequence initiated by key press MS0947-E-00 2008/04 - 33 - [AK4184A] PACKAGE 41pin FBGA (Unit: mm) 4.0 ± 0.1 φ 0.15 A 41 - φ 0.3 ± 0.05 M S AB 7 6 5 4 3 2 1 A B B D 3.0 4.0 ± 0.1 C E F G 0.5 0.5 3.0 S 0.89 ± 0.11 0.24 ± 0.06 0.08 S ■ Material & Lead finish Package molding compound: Interposer material: Solder ball material: Epoxy BT resin SnAgCu MS0947-E-00 2008/04 - 34 - [AK4184A] MARKING 4184A XXXX • XXXX: Date code identifier (4 digits) Pin #A1 indication REVISION HISTORY Date (YY/MM/DD) 08/04/16 Revision 00 Reason First Edition Page MS0947-E-00 Contents 2008/04 - 35 - [AK4184A] IMPORTANT NOTICE z These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status of the products. z AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. z Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKEMD. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any and all claims arising from the use of said product in the absence of such notification. MS0947-E-00 2008/04 - 36 -