[AK4645A] AK4645A Stereo CODEC with MIC/HP-AMP GENERAL DESCRIPTION The AK4645A is a stereo CODEC with a built-in Microphone-Amplifier and Headphone-Amplifier. The AK4645A features analog mixing circuit that allows easy interfacing in mobile phone and portable A/V player designs. The AK4645A is available in a 32pin QFN (4mm x 4mm), utilizing less board space than competitive offerings. FEATURES 1. Recording Function • 4 Stereo Input Selector • Stereo Mic Input (Full-differential or Single-ended) • Stereo Line Input • MIC Amplifier (+32dB/+26dB/+20dB or 0dB) • Digital ALC (Automatic Level Control) (+36dB ∼ −54dB, 0.375dB Step, Mute) • ADC Performance: S/(N+D): 83dB, DR, S/N: 86dB (MIC-Amp=+20dB) S/(N+D): 88dB, DR, S/N: 95dB (MIC-Amp=0dB) • Wind-noise Reduction Filter • Stereo Separation Emphasis • Programmable EQ 2. Playback Function • Digital De-emphasis Filter (tc=50/15(s, fs=32kHz, 44.1kHz, 48kHz) • Bass Boost • Soft Mute • Digital Volume (+12dB ( (115.0dB, 0.5dB Step, Mute) • Digital ALC (Automatic Level Control) (+36dB ∼ −54dB, 0.375dB Step, Mute) • Stereo Separation Emphasis • Programmable EQ • Stereo Line Output - Performance: S/(N+D): 88dB, S/N: 92dB • Stereo Headphone-Amp - S/(N+D): [email protected], S/N: 90dB - Output Power: 70mW@16Ω (HVDD=5V), 62mW@16Ω (HVDD=3.3V) - Pop Noise Free at Power ON/OFF • Analog Mixing: 4 Stereo Input 3. Power Management 4. Master Clock: External Clock Mode • Frequencies: 256fs, 384fs, 512fs or 1024fs (MCKI pin) 5. Sampling Rate: • EXT Master/Slave Mode: 7.35kHz ∼ 48kHz (256fs), 7.35kHz ∼ 48kHz (384fs), 7.35kHz ∼ 26kHz (512fs), 7.35kHz ∼ 13kHz (1024fs) 6. μP I/F: 3-wire serial, I2C Bus (Ver 1.0, 400kHz Fast-mode) 7. Master/Slave mode 8. Audio Interface Format: MSB First, 2’s complement • ADC: 16bit MSB justified, I2S, DSP Mode • DAC: 16bit MSB justified, 16bit LSB justified, 16-24bit I2S, DSP Mode MS0986-E-00 2008/07 -1- [AK4645A] 9. Ta = −30 ∼ 85°C 10. Power Supply: • AVDD, DVDD: 2.6 ∼ 3.5V (typ. 3.3V) • HVDD: 2.6 ∼ 5.25V (typ. 3.3V/5.0V) • TVDD (Digital I/O): 1.6 ∼ 3.5V (typ. 3.3V) 11. Package: 32pin QFN (4mm x 4mm, 0.4mm pitch) 12. Register Compatible with AK4644 ■ Block Diagram AVSS AVDD VCOM DVDD TVDD PMMP MPWR MIC Power Supply I2C Control Register PMADL or PMMICL LIN1/IN1− CSN/CAD0 CCLK/SCL CDTI/SDA Internal MIC RIN1/IN1+ Wind-Noise Stereo HPF Reduction Separation ALC A/D MIC-Amp LIN2/IN2+ External MIC PDN PMADL or PMADR PMADR or PMMICR BICK RIN2/IN2− LRCK SDTO PMAINR2 MIN/LIN3 Line In * RIN3 Line In RIN4/IN4− Audio I/F PMAINL2 SDTI LIN4/IN4+ PMAINR3 PMAINR4 PMAINL3 PMAINL4 PMMIN PMLO PMDAC LOUT/LOP Stereo Line Out D/A Stereo DATT Bass ALC Separation SMUTE Boost HPF ROUT/LON PMHPL MCKI HPL Headphone PMHPR HPR MUTET HVDD HVSS Figure 1. Block Diagram MS0986-E-00 2008/07 -2- [AK4645A] ■ Ordering Guide −30 ∼ +85°C 32pin QFN (0.4mm pitch) Evaluation board for AK4645A AK4645AEZ AKD4645A RIN4 / IN4− MUTET HPL HPR HVDD HVSS TESTO MCKI 24 23 22 21 20 19 18 17 ■ Pin Layout LRCK RIN2 / IN2− 29 Top View 12 SDTO LIN2 / IN2+ 30 11 SDTI LIN1 / IN1− 31 10 CDTI / SDA RIN1 / IN1+ 32 9 CCLK / SCL 8 13 CSN / CAD0 AK4645A 7 28 PDN MIN / LIN3 6 BICK I2C 14 5 27 RIN3 LOUT / LOP 4 DVDD AVDD 15 3 26 AVSS ROUT / LON 2 TVDD VCOM 16 1 25 MPWR LIN4 / IN4+ ■ Compatibility with AK4643/44 1. Function Function Digital I/O of μP I/F Analog Mixing for Playback Input Selector for Recording HP-Amp Hi-Z Setting for wired OR PLL Speaker-Amp Receiver-Amp Package AK4643 2.6 to 3.6V 3 Stereo 3 Stereo No 11.2896/12/12.288/ 13.5/24/27MHz Yes Yes 32QFN (5mm x 5mm, 0.5mm pitch) MS0986-E-00 AK4644 Å Å Å Å AK4645A 1.6 to 3.5V 4 Stereo 4 Stereo Yes Å No No Å Å No 32QFN (4mm x 4mm, 0.4mm pitch) Å 2008/07 -3- [AK4645A] 2. Pin Pin# 16 18 19 20 21 22 23 24 25 26 27 AK4643 DVSS MCKO SPN SPP HVDD HVSS HPR HPL MUTET ROUT/RCN LOUT/RCP AK4644 Å MCKO TEST1 TEST2 Å Å Å Å Å Å Å AK4645A TVDD TESTO HVSS HVDD HPR HPL MUTET RIN4 / IN4− LIN4 / IN4+ ROUT/LON LOUT/LOP 3. Register (difference from AK4644) Addr 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H Register Name Power Management 1 Power Management 2 Signal Select 1 Signal Select 2 Mode Control 1 Mode Control 2 Timer Select ALC Mode Control 1 ALC Mode Control 2 Lch Input Volume Control Lch Digital Volume Control ALC Mode Control 3 Rch Input Volume Control Rch Digital Volume Control Mode Control 3 Mode Control 4 Power Management 3 Digital Filter Select FIL3 Co-efficient 0 FIL3 Co-efficient 1 FIL3 Co-efficient 2 FIL3 Co-efficient 3 EQ Co-efficient 0 EQ Co-efficient 1 EQ Co-efficient 2 EQ Co-efficient 3 EQ Co-efficient 4 EQ Co-efficient 5 FIL1 Co-efficient 0 FIL1 Co-efficient 1 FIL1 Co-efficient 2 FIL1 Co-efficient 3 Power Management 4 Mode Control 5 Lineout Mixing Select HP Mixing Select Reserved D7 0 HPZ 0 LOVL 0 0 DVTM 0 REF7 IVL7 DVL7 RGAIN1 IVR7 DVR7 0 0 INR1 GN1 F3A7 F3AS F3B7 0 EQA7 EQA15 EQB7 0 EQC7 EQC15 F1A7 F1AS F1B7 0 HPMTN 0 LOPS 0 0 WTM2 0 REF6 IVL6 DVL6 LMTH1 IVR6 DVR6 LOOP 0 INL1 GN0 F3A6 0 F3B6 0 EQA6 EQA14 EQB6 0 EQC6 EQC14 F1A6 0 F1B6 0 PMAINR4 PMAINL4 0 LOM 0 0 D6 PMVCM D5 PMMIN PMHPL 0 0 FS3 ZTM1 ALC REF5 IVL5 DVL5 0 IVR5 DVR5 SMUTE 0 HPG 0 F3A5 F3A13 F3B5 F3B13 EQA5 EQA13 EQB5 EQB13 EQC5 EQC13 F1A5 F1A13 F1B5 F1B13 D4 0 PMHPR DACL 0 0 MSBS ZTM0 ZELMN REF4 IVL4 DVL4 0 IVR4 DVR4 DVOLC 0 MDIF2 FIL1 F3A4 F3A12 F3B4 F3B12 EQA4 EQA12 EQB4 EQB12 EQC4 EQC12 F1A4 F1A12 F1B4 F1B12 D3 PMLO M/S 0 0 BCKO BCKP WTM1 LMAT1 REF3 IVL3 DVL3 0 IVR3 DVR3 BST1 IVOLC MDIF1 EQ F3A3 F3A11 F3B3 F3B11 EQA3 EQA11 EQB3 EQB11 EQC3 EQC11 F1A3 F1A11 F1B3 F1B11 D2 PMDAC 0 PMMP MINL 0 FS2 WTM0 LMAT0 REF2 IVL2 DVL2 0 IVR2 DVR2 BST0 HPM INR0 FIL3 F3A2 F3A10 F3B2 F3B10 EQA2 EQA10 EQB2 EQB10 EQC2 EQC10 F1A2 F1A10 F1B2 F1B10 D1 0 0 0 0 DIF1 FS1 RFST1 RGAIN0 REF1 IVL1 DVL1 VBAT IVR1 DVR1 DEM1 MINH INL0 0 F3A1 F3A9 F3B1 F3B9 EQA1 EQA9 EQB1 EQB9 EQC1 EQC9 F1A1 F1A9 F1B1 F1B9 0 DIF0 FS0 RFST0 LMTH0 REF0 IVL0 DVL0 0 IVR0 DVR0 DEM0 DACH PMADR 0 F3A0 F3A8 F3B0 F3B8 EQA0 EQA8 EQB0 EQB8 EQC0 EQC8 F1A0 F1A8 F1B0 F1B8 PMAINR3 PMAINL3 PMAINR2 PMAINL2 PMMICR PMMICL MIX LINL3 LINH3 0 AIN3 RINR2 RINH2 0 LODIF MGAIN1 0 MICR3 MICL3 L4DIF LOM3 RINR4 LINL4 RINR3 HPM3 RINH4 LINH4 RINH3 0 0 0 0 These bits are added in the AK4645A. MS0986-E-00 D0 PMADL 0 MGAIN0 LINL2 LINH2 0 2008/07 -4- [AK4645A] PIN/FUNCTION No. 1 Pin Name MPWR I/O O Function MIC Power Supply Pin Common Voltage Output Pin, 0.45 x AVDD 2 VCOM O Bias voltage of ADC inputs and DAC outputs. 3 AVSS Analog Ground Pin 4 AVDD Analog Power Supply Pin, 2.6 ∼ 3.5V 5 RIN3 I Rch Analog Input 3 Pin (AIN3 bit = “1”) Control Mode Select Pin 6 I2C I “H”: I2C Bus, “L”: 3-wire Serial Power-Down Mode Pin 7 PDN I “H”: Power-up, “L”: Power-down, reset and initializes the control register. CSN I Chip Select Pin (I2C pin = “L”: 3-wire Serial Mode) 8 CAD0 I Chip Address 1 Select Pin (I2C pin = “H”: I2C Bus Mode) CCLK I Control Data Clock Pin (I2C pin = “L”: 3-wire Serial Mode) 9 SCL I Control Data Clock Pin (I2C pin = “H”: I2C Bus Mode) CDTI I Control Data Input Pin (I2C pin = “L”: 3-wire Serial Mode) 10 SDA I/O Control Data Input Pin (I2C pin = “H”: I2C Bus Mode) 11 SDTI I Audio Serial Data Input Pin 12 SDTO O Audio Serial Data Output Pin 13 LRCK I/O Input / Output Channel Clock Pin 14 BICK I/O Audio Serial Data Clock Pin 15 DVDD Digital Power Supply Pin, 2.6 ∼ 3.5V 16 TVDD Digital I/O Power Supply Pin, 1.6 ∼ 3.5V 17 MCKI I External Master Clock Input Pin Test Pin 18 TESTO O This pin must be open. 19 HVSS Headphone Amp Ground Pin 20 HVDD Headphone Amp Power Supply Pin 21 HPR O Rch Headphone-Amp Output Pin 22 HPL O Lch Headphone-Amp Output Pin Mute Time Constant Control Pin 23 MUTET O Connected to HVSS pin with a capacitor for mute time constant. RIN4 I Rch Analog Input 4 Pin (L4DIF bit = “0”: Single-ended Input) 24 IN4− I Negative Line Input 4 Pin (L4DIF bit = “1”: Full-differential Input) LIN4 I Lch Analog Input 4 Pin (L4DIF bit = “0”: Single-ended Input) 25 IN4+ I Positive Line Input 4 Pin (L4DIF bit = “1”: Full-differential Input) ROUT O Rch Stereo Line Output Pin (LODIF bit = “0”: Single-ended Stereo Output) 26 LON O Negative Line Output Pin (LODIF bit = “1”: Full-differential Mono Output) LOUT O Lch Stereo Line Output Pin (LODIF bit = “0”: Single-ended Stereo Output) 27 LOP O Positive Line Output Pin (LODIF bit = “1”: Full-differential Mono Output) MIN I Mono Signal Input Pin 28 LIN3 I Lch Analog Input 3 Pin RIN2 I Rch Analog Input 2 Pin (MDIF2 bit = “0”: Single-ended Input) 29 IN2− I Microphone Negative Input 2 Pin (MDIF2 bit = “1”: Full-differential Input) LIN2 I Lch Analog Input 2 Pin (MDIF2 bit = “0”: Single-ended Input) 30 IN2+ I Microphone Positive Input 2 Pin (MDIF2 bit = “1”: Full-differential Input) LIN1 I Lch Analog Input 1 Pin (MDIF1 bit = “0”: Single-ended Input) 31 IN1− I Microphone Negative Input 1 Pin (MDIF1 bit = “1”: Full-differential Input) RIN1 I Rch Analog Input 1 Pin (MDIF1 bit = “0”: Single-ended Input) 32 IN1+ I Microphone Positive Input 1 Pin (MDIF1 bit = “1”: Full-differential Input) Note 1. All input pins except analog input pins (MIN/LIN3, LIN1, RIN1, LIN2, RIN2, RIN3, RIN4, LIN4) must not be left floating. Note 2. AVDD or AVSS voltage must be input to I2C pin. MS0986-E-00 2008/07 -5- [AK4645A] ■ Handling of Unused Pin The unused I/O pins must be processed appropriately as below. Classification Analog Digital Pin Name MPWR, RIN3, HPR, HPL, MUTET, RIN4/IN4−, LIN4/IN4+, ROUT/LOP, LOUT/LON, MIN/LIN3, RIN2/IN2−, LIN2/IN2+, LIN1/IN1−, RIN1/IN1+ TESTO MCKI Setting These pins must be open. This pin must be open. This pin must be connected to HVSS. ABSOLUTE MAXIMUM RATINGS (AVSS=HVSS=0V; Note 3, Note 4) Parameter Symbol min Power Supplies: Analog AVDD −0.3 Digital DVDD −0.3 Digital I/O TVDD −0.3 Headphone-Amp HVDD −0.3 Input Current, Any Pin Except Supplies IIN Analog Input Voltage (Note 5) VINA −0.3 Digital Input Voltage (Note 6) VIND −0.3 Ambient Temperature (powered applied) Ta −30 Storage Temperature Tstg −65 max 6.0 6.0 6.0 6.0 ±10 AVDD+0.3 TVDD+0.3 85 150 Units V V V V mA V V °C °C Note 3. All voltages with respect to ground. Note 4. AVSS and HVSS must be connected to the same analog ground plane. Note 5. I2C, RIN4/IN4−, LIN4/IN4+, MIN/LIN3, RIN3, RIN2/IN2−, LIN2/IN2+, LIN1/IN1−, RIN1/IN1+ pins Note 6. PDN, CSN/CAD0, CCLK/SCL, CDTI/SDA, SDTI, LRCK, BICK, MCKI pins Pull-up resistors at SDA and SCL pins should be connected to (TVDD+0.3)V or less voltage. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (AVSS=HVSS=0V; Note 3) Parameter Power Supplies Analog (Note 7) Digital Digital I/O HP-Amp Difference Difference Symbol AVDD DVDD TVDD HVDD AVDD−DVDD TVDD-DVDD min 2.6 2.6 1.6 2.6 −0.3 - typ 3.3 3.3 3.3 3.3 / 5.0 0 0 max 3.5 3.5 3.5 5.25 +0.3 +0.3 Units V V V V V V Note 3. All voltages with respect to ground. Note 7. The power-up sequence between AVDD, DVDD, TVDD and HVDD is not critical. PDN pin must be held to “L” upon power-up. PDN pin must be set to “H” after all power supplies are powered-up. The AK4645A must be operated by the recommended power-up/down sequence shown in “System Design (Grounding and Power Supply Decoupling)” to avoid the pop noise at line output and headphone output. When one of power supplies is partially powered OFF, the power supply current at power-down mode may be increased. All the power supplies should be powered OFF when the power supply is powered OFF. * AKEMD assumes no responsibility for the usage beyond the conditions in this datasheet. MS0986-E-00 2008/07 -6- [AK4645A] ANALOG CHARACTERISTICS (Ta=25°C; AVDD=DVDD=TVDD=HVDD=3.3V; AVSS=HVSS=0V; fs=44.1kHz, BICK=64fs; Signal Frequency=1kHz; 16bit Data; Measurement frequency=20Hz ∼ 20kHz; unless otherwise specified) Parameter min typ max Units MIC Amplifier: LIN1/RIN1/LIN2/RIN2/LIN4/RIN4 pins & LIN3/RIN3 pins (AIN3 bit = “1”); MDIF1=MDIF2 bits = “0” (Single-ended inputs) Input MGAIN1-0 bits = “00” 40 60 80 kΩ Resistance MGAIN1-0 bits = “01”, “10”or “11” 20 30 40 kΩ MGAIN1-0 bits = “00” 0 dB MGAIN1-0 bits = “01” +20 dB Gain MGAIN1-0 bits = “10” +26 dB MGAIN1-0 bits = “11” +32 dB MIC Amplifier: IN1+/IN1−/IN2+/IN2− pins; MDIF1 = MDIF2 bits = “1” (Full-differential input) Maximum Input Voltage (Note 8) MGAIN1-0 bits = “01” 0.228 Vpp MGAIN1-0 bits = “10” 0.114 Vpp MGAIN1-0 bits = “11” 0.057 Vpp MIC Power Supply: MPWR pin Output Voltage (Note 9) 2.22 2.47 2.72 V Load Resistance 0.5 kΩ Load Capacitance 30 pF ADC Analog Input Characteristics: LIN1/RIN1/LIN2/RIN2/LIN4/RIN4 pins & LIN3/RIN3 pins (AIN3 bit = “1”) → ADC → IVOL, IVOL=0dB, ALC=OFF Resolution 16 Bits (Note 11) 0.168 0.198 0.228 Vpp Input Voltage (Note 10) 1.68 1.98 2.28 Vpp (Note 12) (Note 11, LIN1/RIN1/LIN2/RIN2) 71 83 dBFS S/(N+D) (Note 11, LIN3/RIN3/LIN4/RIN4) 83 dBFS (−1dBFS) (Note 12, except for LIN3/RIN3) 88 dBFS (Note 12, LIN3/RIN3) 72 dBFS (Note 11) 76 86 dB D-Range (−60dBFS, A-weighted) 95 dB (Note 12) (Note 11) 76 86 dB S/N (A-weighted) 95 dB (Note 12) (Note 11) 75 90 dB Interchannel Isolation 100 dB (Note 12) (Note 11) 0.1 0.8 dB Interchannel Gain Mismatch 0.1 0.8 dB (Note 12) Note 8. The voltage difference between IN1/2+ and IN1/2− pins. AC coupling capacitor should be inserted in series at each input pin. Full-differential mic input is not available at MGAIN1-0 bits = “00”. Maximum input voltage of IN1+, IN1−, IN2+ and IN2− pins are proportional to AVDD voltage, respectively. Vin = 0.069 x AVDD (max)@MGAIN1-0 bits = “01”, 0.035 x AVDD (max)@MGAIN1-0 bits = “10”, 0.017 x AVDD (max)@MGAIN1-0 bits = “11”. When the signal larger than above value is input to IN1+, IN1−, IN2+ or IN2− pin, ADC does not operate normally. Note 9. Output voltage is proportional to AVDD voltage. Vout = 0.75 x AVDD (typ) Note 10. Input voltage is proportional to AVDD voltage. Vin = 0.06 x AVDD (typ)@MGAIN1-0 bits = “01” (+20dB), Vin = 0.6 x AVDD(typ)@MGAIN1-0 bits = “00” (0dB) Note 11. MGAIN1-0 bits = “01” (+20dB) Note 12. MGAIN1-0 bits = “00” (0dB) MS0986-E-00 2008/07 -7- [AK4645A] Parameter min typ max Units DAC Characteristics: Resolution 16 Bits Stereo Line Output Characteristics: DAC → LOUT/ROUT pins, ALC=OFF, IVOL=0dB, DVOL=0dB, LOVL bit = “0”, LODIF bit = “0”, RL=10kΩ (Single-ended); unless otherwise specified. Output Voltage (Note 13) LOVL bit = “0” 1.78 1.98 2.18 Vpp LOVL bit = “1” 2.25 2.50 2.75 Vpp 78 88 dBFS S/(N+D) (−3dBFS) S/N (A-weighted) 82 92 dB Interchannel Isolation 80 100 dB Interchannel Gain Mismatch 0.1 0.5 dB Load Resistance 10 kΩ Load Capacitance 30 pF Mono Line Output Characteristics: DAC → LOP/LON pins, ALC=OFF, IVOL=0dB, DVOL=0dB, LOVL bit = “0”, LODIF bit = “1”, RL=10kΩ for each pin (Full-differential) Output Voltage (Note 14) LOVL bit = “0” 3.52 3.96 4.36 Vpp LOVL bit = “1” 5.00 Vpp 78 88 dBFS S/(N+D) (−3dBFS) S/N (A-weighted) 85 95 dB Load Resistance (LOP/LON pins, respectively) 10 kΩ Load Capacitance (LOP/LON pins, respectively) 30 pF Note 13. Output voltage is proportional to AVDD voltage. Vout = 0.6 x AVDD (typ)@LOVL bit = “0”. Note 14. Output voltage is proportional to AVDD voltage. Vout = (LOP) − (LON) = 1.2 x AVDD (typ)@LOVL bit = “0”. MS0986-E-00 2008/07 -8- [AK4645A] Parameter min typ max Units Headphone-Amp Characteristics: DAC → HPL/HPR pins, ALC=OFF, IVOL=0dB, DVOL=0dB, VBAT bit = “0”; unless otherwise specified. Output Voltage (Note 15) 1.58 1.98 2.38 Vpp HPG bit = “0”, 0dBFS, HVDD=3.3V, RL=22.8Ω 2.40 3.00 3.60 Vpp HPG bit = “1”, 0dBFS, HVDD=5V, RL=100Ω HPG bit = “1”, 0dBFS, HVDD=3.3V, RL=16Ω (Po=62mW) 1.0 Vrms HPG bit = “1”, 0dBFS, HVDD=5V, RL=16Ω (Po=70mW) 1.06 Vrms S/(N+D) 57 67 dBFS HPG bit = “0”, −3dBFS, HVDD=3.3V, RL=22.8Ω 75 dBFS HPG bit = “1”, −3dBFS, HVDD=5V, RL=100Ω HPG bit = “1”, 0dBFS, HVDD=3.3V, RL=16Ω (Po=62mW) 20 dBFS HPG bit = “1”, 0dBFS, HVDD=5V, RL=16Ω (Po=70mW) 65 dBFS (Note 16) 80 90 dB S/N (A-weighted) 90 dB (Note 17) (Note 16) 65 75 dB Interchannel Isolation 80 dB (Note 17) (Note 16) 0.1 0.8 dB Interchannel Gain Mismatch 0.1 0.8 dB (Note 17) Load Resistance 16 Ω C1 in Figure 2 30 pF Load Capacitance 300 pF C2 in Figure 2 Note 15. Output voltage is proportional to AVDD voltage. Vout = 0.6 x AVDD(typ)@HPG bit = “0”, 0.91 x AVDD(typ)@HPG bit = “1”. Note 16. HPG bit = “0”, HVDD=3.3V, RL=22.8Ω. Note 17. HPG bit = “1”, HVDD=5V, RL=100Ω. HP-Amp HPL/HPR pin Measurement Point 47μF 6.8Ω C1 0.22μF C2 16Ω 10Ω Figure 2. Headphone-Amp output circuit MS0986-E-00 2008/07 -9- [AK4645A] Parameter min typ Mono Input: MIN pin (AIN3 bit = “0”; External Input Resistance=20kΩ) Maximum Input Voltage (Note 18) 1.98 Gain (Note 19) MIN Æ LOUT/ROUT LOVL bit = “0” 0 −4.5 LOVL bit = “1” +2 MIN Æ HPL/HPR HPG bit = “0” −24.5 −20 HPG bit = “1” −16.4 Stereo Input: LIN2/RIN2/LIN4/RIN4 pins; LIN3/RIN3 pins (AIN3 bit = “1”) Maximum Input Voltage (Note 20) 1.98 Gain LIN/RIN Æ LOUT/ROUT LOVL bit = “0” 0 −4.5 LOVL bit = “1” +2 LIN/RIN Æ HPL/HPR HPG bit = “0” 0 −4.5 HPG bit = “1” +3.6 Full-differential Mono Input: IN4+/− pins (L4DIF bit = “1”) Maximum Input Voltage (Note 21) 3.96 Gain LOVL bit = “0” IN4+/− Æ LOUT/ROUT −10.5 −6 (LODIF bit = “0”) LOVL bit = “1” −4 LOVL bit = “0” 0 IN4+/− Æ LOP/LON −4.5 (LODIF bit = “1”, Note 22) LOVL bit = “1” +2 HPG bit = “0” IN4+/− Æ HPL/HPR −10.5 −6 HPG bit = “1” −2.4 Power Supplies: Power-Up (PDN pin = “H”) All Circuit Power-up: AVDD+DVDD+TVDD (Note 23) 12 HVDD: HP-Amp Normal Operation 3 No Output (Note 24) Power-Down (PDN pin = “L”) (Note 25) AVDD+DVDD+TVDD+HVDD 1 max Units - Vpp +4.5 −15.5 - dB dB dB dB - Vpp +4.5 +4.5 - dB dB dB dB - Vpp −1.5 +4.5 −1.5 - dB dB dB dB dB dB 18 mA 4.5 mA 100 μA Note 18. Maximum voltage is in proportion to both AVDD and external input resistance (Rin). Vin = 0.6 x AVDD x Rin / 20kΩ (typ). Note 19. The gain is in inverse proportion to external input resistance. Note 20. Maximum Input voltage is proportional to AVDD voltage. Vout = 0.6 x AVDD (typ). Note 21. Maximum Input voltage is proportional to AVDD voltage. Vout = (IN4+) − (IN4−) = 1.2 x AVDD (typ). The signals with same amplitude and inverted phase should be input to IN4+ and IN4− pins, respectively. Note 22. Vout = (LOP) − (LON) at LODIF bit = “1”. Note 23. When EXT Slave Mode (M/S = bit = “0”, MCKI = 12.288MHz), PMVCM = PMADL = PMADR = PMDAC = PMLO = PMHPL = PMHPR = PMMIN = PMMP = “1”: AVDD=9mA (typ), DVDD=3mA (typ), TVDD=0.03mA (typ). Note 24. When PMADL = PMADR = PMDAC = PMLO = PMHPL = PMHPR = PMVCM = PMMIN bits = “1” Note 25. All digital input pins are fixed to TVDD or HVSS. MS0986-E-00 2008/07 - 10 - [AK4645A] ■ Power Consumption for Each Operation Mode Condtions: Ta=25°C; AVDD=DVDD=TVDD=HVDD=3.3V; AVSS=HVSS=0V; fs=44.1kHz, External Slave Mode, BICK=64fs; 1kHz, 0dBFS input; Headphone = No output. PMDAC PMADL PMHPR PMADR PMMICL PMMICR PMAINL2 PMAINR2 PMAINL3 PMAINR3 PMAINL4 PMAINR4 AVDD [mA] DVDD [mA] TVDD [mA] PMHPL HVDD [mA] Total Power [mW] 20H PMLO 10H PMMIN 01H PMVCM 00H Power Management Bit 0 1 1 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3.2 2.6 1.9 5.5 3.5 0 1.8 1.8 0 1.6 1.5 0 0.03 0.03 0 0.03 0.03 0 0.2 3.0 3.0 0.2 0.2 0 17.2 24.5 16.2 24.2 17.3 1 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 7.1 2.7 0.03 3.0 42.3 Mode All Power-down DAC Æ Lineout DAC Æ HP LIN2/RIN2 Æ HP LIN2/RIN2 Æ ADC LIN1 (Mono) Æ ADC LIN2/RIN2 Æ ADC & DAC Æ HP Table 1. Power Consumption for each operation mode (typ) MS0986-E-00 2008/07 - 11 - [AK4645A] FILTER CHARACTERISTICS (Ta=25°C; AVDD=DVDD=2.6 ∼ 3.5V; TVDD=1.6 ∼ 3.5V; HVDD=2.6 ∼ 5.25V; fs=44.1kHz; DEM=OFF; FIL1=FIL3=EQ=OFF) Parameter Symbol min typ max Units ADC Digital Filter (Decimation LPF): Passband (Note 26) PB 0 17.3 kHz ±0.16dB 19.4 kHz −0.66dB 19.9 kHz −1.1dB 22.1 kHz −6.9dB Stopband SB 26.1 kHz Passband Ripple PR dB ±0.1 Stopband Attenuation SA 73 dB Group Delay (Note 27) GD 19 1/fs Group Delay Distortion 0 ΔGD μs ADC Digital Filter (HPF): (Note 28) Frequency Response (Note 26) −3.0dB FR 0.9 Hz 2.7 Hz −0.5dB 6.0 Hz −0.1dB DAC Digital Filter (LPF): Passband (Note 26) PB 0 19.6 kHz ±0.1dB 20.0 kHz −0.7dB 22.05 kHz −6.0dB Stopband SB 25.2 kHz Passband Ripple PR dB ±0.01 Stopband Attenuation SA 59 dB Group Delay (Note 27) GD 25 1/fs DAC Digital Filter (LPF) + SCF: FR dB Frequency Response: 0 ∼ 20.0kHz ±1.0 DAC Digital Filter (HPF): (Note 28) Frequency Response (Note 26) −3.0dB FR 0.9 Hz 2.7 Hz −0.5dB 6.0 Hz −0.1dB BOOST Filter: (Note 29) Frequency Response MIN FR 20Hz dB 5.76 100Hz dB 2.92 1kHz dB 0.02 MID FR 20Hz dB 10.80 100Hz dB 6.84 1kHz dB 0.13 MAX 20Hz FR dB 16.06 100Hz dB 10.54 1kHz dB 0.37 Note 26. The passband and stopband frequencies scale with fs (system sampling rate). For example, DAC is PB=0.454*fs (@−0.7dB). Each response refers to that of 1kHz. Note 27. The calculated delay time caused by digital filtering. This time is from the input of analog signal to setting of the 16-bit data of both channels from the input register to the output register of the ADC. This time includes the group delay of the HPF. For the DAC, this time is from setting the 16-bit data of both channels from the input register to the output of analog signal. Group delay of DAC part is 25/fs(typ) at PMADL=PMADR bits = “0”. Note 28. When PMADL bit = “1” or PMADR bit = “1”, the HPF of ADC is enabled but the HPF of DAC is disabled. When PMADL=PMADR bits = “0”, PMDAC bit = “1”, the HPF of DAC is enabled but the HPF of ADC is disabled. Note 29. These frequency responses scale with fs. If a high-level signal is input, the analog output clips to the full-scale at low frequency. MS0986-E-00 2008/07 - 12 - [AK4645A] DC CHARACTERISTICS (Ta=25°C; AVDD=DVDD=2.6 ∼ 3.5V; TVDD=1.6 ∼ 3.5V; HVDD=2.6 ∼ 5.25V) Parameter Symbol min High-Level Input Voltage 2.2V≤TVDD≤3.5V VIH 70%TVDD 1.6V≤TVDD<2.2V VIH 75%TVDD Low-Level Input Voltage 2.2V≤TVDD≤3.5V VIL 1.6V≤TVDD<2.2V VIL High-Level Output Voltage VOH (Iout=−200μA) TVDD−0.2 Low-Level Output Voltage VOL (Except SDA pin: Iout=200μA) (SDA pin: Iout=3mA) VOL Input Leakage Current Iin - typ - max 30%TVDD 25%TVDD - Units V V V V V - 0.2 0.4 ±10 V V μA SWITCHING CHARACTERISTICS (Ta=25°C; AVDD=DVDD=2.6 ∼ 3.5V;or 3.3V TVDD=1.6 ∼ 3.5V; HVDD=2.6 ∼ 5.25V or AVdd=DVdd=3.3V; CL=20pF; unless otherwise specified) Parameter Symbol min typ max Units External Slave Mode MCKI Input Timing 256fs fCLK 1.8816 12.288 MHz Frequency 384fs fCLK 2.8224 18.432 MHz 512fs fCLK 3.7632 13.312 MHz 1024fs fCLK 7.5264 13.312 MHz Pulse Width Low tCLKL 0.4/fCLK ns Pulse Width High tCLKH 0.4/fCLK ns LRCK Input Timing 256fs fs 7.35 48 kHz Frequency 384fs fs 7.35 48 kHz 512fs fs 7.35 26 kHz 1024fs fs 7.35 13 kHz DSP Mode: Pulse Width High tLRCKH ns tBCK−60 1/fs − tBCK Except DSP Mode: Duty Cycle Duty 45 55 % BICK Input Timing Period tBCK 312.5 ns Pulse Width Low tBCKL 130 ns Pulse Width High tBCKH 130 ns External Master Mode MCKI Input Timing 256fs fCLK 1.8816 12.288 MHz Frequency 384fs fCLK 2.8224 18.432 MHz 512fs fCLK 3.7632 13.312 MHz 1024fs fCLK 7.5264 13.312 MHz Pulse Width Low tCLKL 0.4/fCLK ns Pulse Width High tCLKH 0.4/fCLK ns LRCK Output Timing Frequency fs 7.35 48 kHz DSP Mode: Pulse Width High tLRCKH tBCK ns Except DSP Mode: Duty Cycle Duty 50 % BICK Output Timing Period BCKO bit = “0” tBCK 1/(32fs) ns BCKO bit = “1” tBCK 1/(64fs) ns Duty Cycle dBCK 50 % MS0986-E-00 2008/07 - 13 - [AK4645A] Parameter Symbol Audio Interface Timing (DSP Mode) Master Mode tDBF LRCK “↑” to BICK “↑” (Note 30) tDBF LRCK “↑” to BICK “↓” (Note 31) tBSD BICK “↑” to SDTO (BCKP bit = “0”) tBSD BICK “↓” to SDTO (BCKP bit = “1”) SDTI Hold Time tSDH SDTI Setup Time tSDS Slave Mode tLRB LRCK “↑” to BICK “↑” (Note 30) tLRB LRCK “↑” to BICK “↓” (Note 31) tBLR BICK “↑” to LRCK “↑” (Note 30) tBLR BICK “↓” to LRCK “↑” (Note 31) tBSD BICK “↑” to SDTO (BCKP bit = “0”) tBSD BICK “↓” to SDTO (BCKP bit = “1”) SDTI Hold Time tSDH SDTI Setup Time tSDS Audio Interface Timing (Right/Left justified & I2S) Master Mode tMBLR BICK “↓” to LRCK Edge (Note 32) tLRD LRCK Edge to SDTO (MSB) (Except I2S mode) tBSD BICK “↓” to SDTO SDTI Hold Time tSDH SDTI Setup Time tSDS Slave Mode tLRB LRCK Edge to BICK “↑” (Note 32) tBLR BICK “↑” to LRCK Edge (Note 32) tLRD LRCK Edge to SDTO (MSB) (Except I2S mode) tBSD BICK “↓” to SDTO SDTI Hold Time tSDH SDTI Setup Time tSDS min typ max Units 0.5 x tBCK − 40 0.5 x tBCK − 40 −70 −70 50 50 0.5 x tBCK 0.5 x tBCK - 0.5 x tBCK + 40 0.5 x tBCK + 40 70 70 - ns ns ns ns ns ns 0.4 x tBCK 0.4 x tBCK 0.4 x tBCK 0.4 x tBCK 50 50 - 80 80 - ns ns ns ns ns ns ns ns −40 −70 - 40 70 ns ns −70 50 50 - 70 - ns ns ns 50 50 - - 80 ns ns ns 50 50 - 80 - ns ns ns Note 30. MSBS, BCKP bits = “00” or “11”. Note 31. MSBS, BCKP bits = “01” or “10”. Note 32. BICK rising edge must not occur at the same time as LRCK edge. MS0986-E-00 2008/07 - 14 - [AK4645A] Parameter Symbol min Control Interface Timing (3-wire Serial mode) CCLK Period tCCK 200 CCLK Pulse Width Low tCCKL 80 Pulse Width High tCCKH 80 CDTI Setup Time tCDS 40 CDTI Hold Time tCDH 40 CSN “H” Time tCSW 150 tCSS 50 CSN Edge to CCLK “↑” (Note 34) tCSH 50 CCLK “↑” to CSN Edge (Note 34) Control Interface Timing (I2C Bus mode): (Note 33) SCL Clock Frequency fSCL Bus Free Time Between Transmissions tBUF 1.3 Start Condition Hold Time (prior to first clock pulse) tHD:STA 0.6 Clock Low Time tLOW 1.3 Clock High Time tHIGH 0.6 Setup Time for Repeated Start Condition tSU:STA 0.6 SDA Hold Time from SCL Falling (Note 35) tHD:DAT 0 SDA Setup Time from SCL Rising tSU:DAT 0.1 Rise Time of Both SDA and SCL Lines tR Fall Time of Both SDA and SCL Lines tF Setup Time for Stop Condition tSU:STO 0.6 Capacitive Load on Bus Cb Pulse Width of Spike Noise Suppressed by Input Filter tSP 0 Power-down & Reset Timing PDN Pulse Width (Note 36) tPD 150 tPDV PMADL or PMADR “↑” to SDTO valid (Note 37) 2 Note 33. I C is a registered trademark of Philips Semiconductors. Note 34. CCLK rising edge must not occur at the same time as CSN edge. Note 35. Data must be held long enough to bridge the 300ns-transition time of SCL. Note 36. The AK4645A can be reset by the PDN pin = “L”. Note 37. This is the count of LRCK “↑” from the PMADL or PMADR bit = “1”. MS0986-E-00 typ max Units - - ns ns ns ns ns ns ns ns - 400 0.3 0.3 400 50 kHz μs μs μs μs μs μs μs μs μs μs pF ns 1059 - ns 1/fs 2008/07 - 15 - [AK4645A] ■ Timing Diagram 1/fCLK VIH MCKI VIL tCLKH tCLKL 1/fs 50%TVDD LRCK tLRCKH tLRCKL Duty = tLRCKH x fs x 100 tLRCKL x fs x 100 tBCK 50%TVDD BICK tBCKH tBCKL dBCK = tBCKH / tBCK x 100 tBCKL / tBCK x 100 Figure 3. Clock Timing (EXT Master mode) tLRCKH LRCK 50%TVDD tBCK tDBF dBCK BICK (BCKP = "0") 50%TVDD BICK (BCKP = "1") 50%TVDD tBSD SDTO MSB tSDS 50%TVDD tSDH VIH SDTI VIL Figure 4. Audio Interface Timing (EXT Master mode, DSP mode, MSBS = “0”) MS0986-E-00 2008/07 - 16 - [AK4645A] tLRCKH LRCK 50%TVDD tBCK tDBF dBCK BICK (BCKP = "1") 50%TVDD BICK (BCKP = "0") 50%TVDD tBSD SDTO 50%TVDD MSB tSDS tSDH VIH SDTI VIL Figure 5. Audio Interface Timing (EXT Master mode, DSP mode, MSBS = “1”) 50%TVDD LRCK tBLR tBCKL BICK 50%TVDD tLRD tBSD SDTO 50%TVDD tSDS tSDH VIH SDTI VIL Figure 6. Audio Interface Timing (EXT Master mode, Except DSP mode) MS0986-E-00 2008/07 - 17 - [AK4645A] 1/fCLK VIH MCKI VIL tCLKH tCLKL 1/fs VIH LRCK VIL tLRCKH tLRCKL Duty = tLRCKH x fs x 100 tLRCKL x fs x 100 tBCK VIH BICK VIL tBCKH tBCKL Figure 7. Clock Timing (EXT Slave mode) tLRCKH VIH LRCK VIL tLRB VIH BICK VIL (BCKP = "0") VIH BICK (BCKP = "1") VIL tBSD SDTO MSB tSDS 50%TVDD tSDH VIH SDTI MSB VIL Figure 8. Audio Interface Timing (EXT Slave mode, DSP mode; MSBS = “0”) MS0986-E-00 2008/07 - 18 - [AK4645A] tLRCKH VIH LRCK VIL tLRB VIH BICK VIL (BCKP = "1") VIH BICK (BCKP = "0") VIL tBSD SDTO 50%TVDD MSB tSDS tSDH VIH SDTI MSB VIL Figure 9. Audio Interface Timing (EXT Slave mode, DSP mode, MSBS = “1”) VIH LRCK VIL tBLR tLRB VIH BICK VIL tBSD tLRD SDTO MSB 50%TVDD tSDH tSDS VIH SDTI VIL Figure 10. Audio Interface Timing (EXT Slave mode, Except DSP mode) MS0986-E-00 2008/07 - 19 - [AK4645A] VIH CSN VIL tCSH tCCKL tCSS tCCKH VIH CCLK VIL tCCK tCDH tCDS VIH CDTI C1 C0 R/W VIL Figure 11. WRITE Command Input Timing tCSW VIH CSN VIL tCSH tCSS VIH CCLK VIL VIH CDTI D2 D1 D0 VIL Figure 12. WRITE Data Input Timing MS0986-E-00 2008/07 - 20 - [AK4645A] VIH SDA VIL tBUF tLOW tHIGH tR tF tSP VIH SCL VIL tHD:STA Stop tHD:DAT tSU:DAT Start tSU:STA tSU:STO Start Stop Figure 13. I2C Bus Mode Timing PMADL bit or PMADR bit tPDV SDTO 50%TVDD Figure 14. Power Down & Reset Timing 1 tPD PDN VIL Figure 15. Power Down & Reset Timing 2 MS0986-E-00 2008/07 - 21 - [AK4645A] OPERATION OVERVIEW ■ System Clock There are the following two clock modes to interface with external devices (Table 2 and Table 3). Mode M/S bit EXT Slave Mode 0 EXT Master Mode 1 Table 2. Clock Mode Setting (x: Don’t care) Mode EXT Slave Mode EXT Master Mode MCKI pin BICK pin Input Selected by FS1-0 bits (≥ 32fs) Output Selected by FS1-0 bits (Selcted byBCKO bit) Table 3. Clock pins state in Clock Mode Figure Figure 16 Figure 17 LRCK pin Input (1fs) Output (1fs) ■ Master Mode/Slave Mode The M/S bit selects either master or slave mode. M/S bit = “1” selects master mode and “0” selects slave mode. When the AK4645A is powered-down (PDN pin = “L”) and exits reset state, the AK4645A is in slave mode. After exiting reset state, the AK4645A goes to master mode by changing M/S bit = “1”. When the AK4645A is in master mode, LRCK and BICK pins are floating state until M/S bit becomes “1”. LRCK and BICK pins of the AK4645A should be pulled-down or pulled-up by the resistor (about 100kΩ) externally to avoid the floating state. M/S bit Mode 0 Slave Mode 1 Master Mode Table 4. Select Master/Slave Mode MS0986-E-00 (default) 2008/07 - 22 - [AK4645A] ■ EXT Slave Mode (M/S bit = “0”) The Master clock is input from the MCKI pin for ADC and DAC. This mode is compatible with I/F of the normal audio CODEC. The clocks required to operate are MCKI (256fs, 384fs, 512fs or 1024fs), LRCK (fs) and BICK (≥32fs). The master clock (MCKI) should be synchronized with LRCK. The phase between these clocks does not matter. The input frequency of MCKI is selected by FS1-0 bits (Table 5). Mode 0 1 2 3 MCKI Input Sampling Frequency Frequency Range Don’t care 0 0 256fs 7.35kHz ∼ 48kHz Don’t care 0 1 1024fs 7.35kHz ∼ 13kHz Don’t care 1 0 384fs 7.35kHz ∼ 48kHz Don’t care 1 1 512fs 7.35kHz ∼ 26kHz Table 5. MCKI Frequency at EXT Slave Mode (M/S bit = “0”) FS3-2 bits FS1 bit FS0 bit (default) The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise. The out-of-band noise can be improved by using higher frequency of the master clock. The S/N of the DAC output through LOUT/ROUT pins at fs=8kHz is shown in Table 6. S/N (fs=8kHz, 20kHzLPF + A-weighted) 256fs 83dB 384fs 83dB 512fs 93dB 1024fs 93dB Table 6. Relationship between MCKI and S/N of LOUT/ROUT pins MCKI The external clocks (MCKI, BICK and LRCK) should always be present whenever the ADC or DAC is in operation (PMADL bit = “1”, PMADR bit = “1” or PMDAC bit = “1”). If these clocks are not provided, the AK4645A may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. If the external clocks are not present, the ADC and DAC should be in the power-down mode (PMADL=PMADR=PMDAC bits = “0”). AK4645A DSP or μP 256fs, 384fs, 512fs or 1024fs MCLK MCKI BICK LRCK ≥ 32fs 1fs BCLK LRCK SDTO SDTI SDTI SDTO Figure 16. EXT Slave Mode MS0986-E-00 2008/07 - 23 - [AK4645A] ■ EXT Master Mode (M/S bit = “1”) The AK4645A becomes EXT Master Mode by setting M/S bit = “1”. Master clock is input from the MCKI pin for ADC and DAC. The clock required to operate is MCKI (256fs, 384fs, 512fs or 1024fs). The input frequency of MCKI is selected by FS1-0 bits (Table 7). Mode 0 1 2 3 MCKI Input Sampling Frequency Frequency Range Don’t care 0 0 256fs 7.35kHz ∼ 48kHz Don’t care 0 1 1024fs 7.35kHz ∼ 13kHz Don’t care 1 0 384fs 7.35kHz ∼ 48kHz Don’t care 1 1 512fs 7.35kHz ∼ 26kHz Table 7. MCKI Frequency at EXT Master Mode (M/S bit = “1”) FS3-2 bits FS1 bit FS0 bit (default) The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise. The out-of-band noise can be improved by using higher frequency of the master clock. The S/N of the DAC output through LOUT/ROUT pins at fs=8kHz is shown in Table 8. S/N (fs=8kHz, 20kHzLPF + A-weighted) 256fs 83dB 384fs 83dB 512fs 93dB 1024fs 93dB Table 8. Relationship between MCKI and S/N of LOUT/ROUT pins MCKI MCKI should always be present whenever the ADC or DAC is in operation (PMADL bit = “1”, PMADR bit = “1” or PMDAC bit = “1”). If MCKI is not provided, the AK4645A may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. If MCKI is not present, the ADC and DAC should be in power-down mode (PMADL=PMADR=PMDAC bits = “0”). AK4645A DSP or μP 256fs, 384fs, 512fs or 1024fs MCKI 32fs or 64fs BICK 1fs LRCK MCLK BCLK LRCK SDTO SDTI SDTI SDTO Figure 17. EXT Master Mode BICK Output Frequency 0 32fs (default) 1 64fs Table 9. BICK Output Frequency at Master Mode BCKO bit MS0986-E-00 2008/07 - 24 - [AK4645A] ■ System Reset Upon power-up, the AK4645A must be reset by bringing the PDN pin = “L”. This ensures that all internal registers reset to their initial values. The ADC enters an initialization cycle when the PMADL or PMADR bit is changed from “0” to “1” at PMDAC bits is “0”. The initialization cycle time is 1059/fs=24ms@fs=44.1kHz. During the initialization cycle, the ADC digital data of both channels is forced to output a 2’s compliment, “0” data. The ADC output reflects the analog input signal after the initialization cycle is completed. When PMDAC bit is “1”, the ADC does not require an initialization cycle. The DAC enters an initialization cycle when the PMDAC bit is changed from “0” to “1” at PMADL and PMADR bits are “0”. The initialization cycle time is 1059/fs=24ms@fs=44.1kHz. During the initialization cycle, the DAC input digital data of both channels are internally forced to a 2’s compliment, “0”. The DAC output reflects the digital input data after the initialization cycle is completed. When PMADL or PMADR bit is “1”, the DAC does not require an initialization cycle. ■ Audio Interface Format Four types of data formats are available and are selected by setting the DIF1-0 bits (Table 10). In all modes, the serial data is MSB first, 2’s complement format. Audio interface formats can be used in both master and slave modes. LRCK and BICK are output from the AK4645A in master mode, but must be input to the AK4645A in slave mode. Mode 0 1 2 3 DIF1 bit 0 0 1 1 DIF0 bit 0 1 0 1 SDTO (ADC) SDTI (DAC) DSP Mode DSP Mode MSB justified LSB justified MSB justified MSB justified I2S compatible I2S compatible Table 10. Audio Interface Format BICK ≥ 32fs ≥ 32fs ≥ 32fs ≥ 32fs Figure Table 11 Figure 22 Figure 23 Figure 24 (default) In modes 1, 2 and 3, the SDTO is clocked out on the falling edge (“↓”) of BICK and the SDTI is latched on the rising edge (“↑”). In Modes 0 (DSP mode), the audio I/F timing is changed by BCKP and MSBS bits (Table 11). DIF1 DIF0 0 MSBS BCKP 0 0 0 1 1 0 1 1 0 Audio Interface Format MSB of SDTO is output by the rising edge (“↑”) of the first BICK after the rising edge (“↑”) of LRCK. MSB of SDTI is latched by the falling edge (“↓”) of the BICK just after the output timing of SDTO’s MSB. MSB of SDTO is output by the falling edge (“↓”) of the first BICK after the rising edge (“↑”) of LRCK. MSB of SDTI is latched by the rising edge (“↑”) of the BICK just after the output timing of SDTO’s MSB. MSB of SDTO is output by next rising edge (“↑”) of the falling edge (“↓”) of the first BICK after the rising edge (“↑”) of LRCK. MSB of SDTI is latched by the falling edge (“↓”) of the BICK just after the output timing of SDTO’s MSB. MSB of SDTO is output by next falling edge (“↓”) of the rising edge (“↑”) of the first BICK after the rising edge (“↑”) of LRCK. MSB of SDTI is latched by the rising edge (“↑”) of the BICK just after the output timing of SDTO’s MSB. Table 11. Audio Interface Format in Mode 0 Figure Figure 18 (default) Figure 19 Figure 20 Figure 21 If 16-bit data that ADC outputs is converted to 8-bit data by removing LSB 8-bit, “−1” at 16bit data is converted to “−1” at 8-bit data. And when the DAC playbacks this 8-bit data, “−1” at 8-bit data will be converted to “−256” at 16-bit data and this is a large offset. This offset can be removed by adding the offset of “128” to 16-bit data before converting to 8-bit data. MS0986-E-00 2008/07 - 25 - [AK4645A] LRCK (Master) LRCK (Slave) 15 0 1 8 2 9 10 11 12 13 14 15 16 17 24 18 25 26 27 26 29 30 31 0 BICK(32fs) Lch SDTO(o) 0 SDTI(i) 0 Rch 15 14 8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 Lch 15 1 8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 Rch 15 14 0 15 14 14 2 15 16 17 18 30 31 15 14 32 33 46 34 47 48 49 50 26 27 26 62 63 30 31 BICK(64fs) Lch SDTO(o) Rch 15 14 2 1 0 2 1 0 15 14 1 0 2 1 0 Rch Lch SDTI(i) 2 15 14 15 14 1/fs 15:MSB, 0:LSB Figure 18. Mode 0 Timing (BCKP = “0”, MSBS = “0”) LRCK (Master) LRCK (Slave) 15 0 1 8 2 9 10 11 12 13 14 15 16 17 24 18 25 29 0 BICK(32fs) Lch SDTO(o) 0 SDTI(i) 0 Rch 15 14 8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 Lch 15 1 8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 Rch 15 14 0 15 14 14 2 15 16 17 18 30 31 15 14 32 33 34 46 47 48 49 50 62 63 BICK(64fs) Lch SDTO(o) 15 14 Rch 2 1 0 2 1 0 15 14 2 1 0 2 1 0 Rch Lch SDTI(i) 15 14 15 14 1/fs 15:MSB, 0:LSB Figure 19. Mode 0 Timing (BCKP = “1”, MSBS = “0”) MS0986-E-00 2008/07 - 26 - [AK4645A] LRCK (Master) LRCK (Slave) 15 0 1 8 2 9 10 11 12 13 14 15 16 17 24 18 25 26 27 26 29 30 31 0 BICK(32fs) Lch SDTO(o) 0 SDTI(i) 0 Rch 15 14 8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 Lch 15 1 8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 Rch 15 14 0 15 14 14 2 15 16 17 18 30 31 15 14 32 33 46 34 47 48 49 50 26 27 26 62 63 30 31 BICK(64fs) Lch SDTO(o) Rch 15 14 2 1 0 15 14 Lch SDTI(i) 2 1 0 2 1 0 Rch 15 14 2 1 0 15 14 1/fs 15:MSB, 0:LSB Figure 20. Mode 0 Timing (BCKP = “0”, MSBS = “1”) LRCK (Master) LRCK (Slave) 15 0 1 8 2 9 10 11 12 13 14 15 16 17 24 18 25 29 0 BICK(32fs) Lch SDTO(o) 0 Rch 15 14 8 7 6 5 4 3 2 1 0 Lch SDTI(i) 0 15 15 14 0 1 15 14 8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 Rch 8 7 14 2 6 15 5 16 4 17 3 2 18 1 30 0 31 15 14 32 33 34 46 47 48 49 50 62 63 BICK(64fs) Lch SDTO(o) 15 14 Rch 2 1 0 2 1 0 Lch SDTI(i) 15 14 15 14 2 1 0 2 1 0 Rch 15 14 1/fs 15:MSB, 0:LSB Figure 21. Mode 0 Timing (BCKP = “1”, MSBS = “1”) MS0986-E-00 2008/07 - 27 - [AK4645A] LRCK 0 1 2 3 9 10 11 12 13 14 15 0 1 2 3 9 10 11 12 13 14 15 0 1 BICK(32fs) SDTO(o) 15 14 13 7 6 5 4 3 2 1 0 15 14 13 7 6 5 4 3 2 1 0 15 SDTI(i) 15 14 13 7 6 5 4 3 2 1 0 15 14 13 7 6 5 4 3 2 1 0 15 0 1 2 3 15 16 17 18 31 0 1 2 3 15 16 17 18 31 0 1 BICK(64fs) SDTO(o) SDTI(i) 1 0 15 14 13 15 14 13 15 14 Don't Care 1 0 1 0 Don't Care 15 15 14 2 1 0 15:MSB, 0:LSB Lch Data Rch Data Figure 22. Mode 1 Timing LRCK 0 1 2 3 9 10 11 12 13 14 15 0 1 2 3 9 10 11 12 13 14 15 0 1 BICK(32fs) SDTO(o) 15 14 13 7 6 5 4 3 2 1 0 15 14 13 7 6 5 4 3 2 1 0 15 SDTI(i) 15 14 13 7 6 5 4 3 2 1 0 15 14 13 7 6 5 4 3 2 1 0 15 0 1 2 3 15 16 17 18 31 0 1 2 3 15 16 17 18 31 0 1 BICK(64fs) SDTO(o) 15 14 13 1 0 SDTI(i) 15 14 13 1 0 Don't Care 15 14 13 1 0 15 14 13 1 0 15 Don't Care 15 15:MSB, 0:LSB Lch Data Rch Data Figure 23. Mode 2 Timing MS0986-E-00 2008/07 - 28 - [AK4645A] LRCK 0 1 2 3 9 10 11 12 13 14 15 0 1 2 3 9 10 11 12 13 14 15 0 1 BICK(32fs) SDTO(o) 0 15 14 8 7 6 5 4 3 2 1 0 15 14 8 7 6 5 4 3 2 1 0 SDTI(i) 0 15 14 8 7 6 5 4 3 2 1 0 15 14 8 7 6 5 4 3 2 1 0 0 1 2 3 15 16 17 18 31 0 1 2 3 15 16 17 18 31 0 1 BICK(64fs) SDTO(o) 15 14 2 1 0 SDTI(i) 15 14 2 1 0 Don't Care 15 14 2 1 0 15 14 2 1 0 Don't Care 15:MSB, 0:LSB Lch Data Rch Data Figure 24. Mode 3 Timing ■ Mono/Stereo Mode PMADL, PMADR and MIX bits set mono/stereo ADC operation. When MIX bit = “1”, EQ and FIL3 bits should be set to “0”. ALC operation (ALC bit = “1”) or digital volume operation (ALC bit = “0”) is applied to the data in Table 12. PMADL bit 0 0 1 1 PMADR bit 0 1 0 MIX bit ADC Lch data ADC Rch data x All “0” All “0” x Rch Input Signal Rch Input Signal x Lch Input Signal Lch Input Signal 0 Lch Input Signal Rch Input Signal 1 1 (L+R)/2 (L+R)/2 Table 12. Mono/Stereo ADC operation (x: Don’t care) (default) ■ Digital High Pass Filter The AK4645A has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 0.9Hz (@fs=44.1kHz) and scales with sampling rate (fs). When PMADL bit = “1” or PMADR bit = “1”, the HPF of ADC is enabled but the HPF of DAC is disabled. When PMADL=PMADR bits = “0”, PMDAC bit = “1”, the HPF of DAC is enabled but the HPF of ADC is disabled. MS0986-E-00 2008/07 - 29 - [AK4645A] ■ MIC/LINE Input Selector The AK4645A has input selector for MIC-Amp. When MDIF1 and MDIF2 bits are “0”, INL1-0 and INR1-0 bits select LIN1/LIN2/LIN3/LIN4 and RIN1/RIN2/RIN3/RIN4, respectively. When MDIF1 and MDIF2 bits are “1”, LIN1, RIN1, LIN2 and RIN2 pins become IN1−, IN1+, IN2+ and IN2− pins respectively. In this case, full-differential input is available (Figure 26). When full-differential input is used, the signal must not be input to the pins marked by “X” in Table 14. MDIF1 bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 Others MDIF2 bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 INL1 bit 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 1 0 0 0 0 INL0 bit 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 0 0 0 0 INR1 bit 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 INR0 bit 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 1 0 1 0 Lch LIN1 LIN1 LIN1 LIN1 LIN2 LIN2 LIN2 LIN2 LIN3 LIN3 LIN3 LIN3 LIN4 LIN4 LIN4 LIN4 LIN1 LIN3 LIN4 IN1+/− IN1+/− IN1+/− IN1+/− N/A Rch RIN1 RIN2 RIN3 RIN4 RIN1 RIN2 RIN3 RIN4 RIN1 RIN2 RIN3 RIN4 RIN1 RIN2 RIN3 RIN4 IN2+/− IN2+/− IN2+/− RIN2 RIN3 RIN4 IN2+/− N/A (default) Table 13. MIC/Line In Path Select Register AIN3 bit 0 0 0 0 1 1 1 1 Pin RIN2 LIN1 MIN LIN4 RIN1 LIN2 MDIF1 bit MDIF2 bit LIN3 RIN3 IN4+ IN1+ IN2+ IN2− IN1− 0 0 O O O O O O 0 1 O X O O O O 1 0 O O X O O X 1 1 O O O O O X 0 0 O O O O O O O 0 1 O X O O O X O 1 0 O O X O X O X 1 1 O O O O X X X Table 14. Handling of MIC/Line Input Pins (“-“: N/A; “X”: Signal should not be input.) MS0986-E-00 RIN4 IN4− O X O X O X O X 2008/07 - 30 - [AK4645A] AK4645A INL1-0 bits LIN1/IN1− pin ADC Lch RIN1/IN1+ pin MDIF1 bit MIC-Amp INR1-0 bits RIN2/IN2− pin ADC Rch LIN2/IN2+ pin MDIF2 bit MIC-Amp MIN/LIN3 pin PMAINR2 bit PMAINL2 bit PMAINL4 bit PMAINR4 bit MICR3 bit RIN4/IN4− pin PMAINR3 bit LIN4/IN4+ pin PMAINL3 bit MICL3 bit RIN3 pin Lineout, HP-Amp Figure 25. Mic/Line Input Selector AK4645A MPWR pin 1k IN1− pin MIC-Amp IN1+ pin A/D SDTO pin 1k Figure 26. Connection Example for Full-differential Mic Input (MDIF1/2 bits = “1”) <Input Selector Setting Example> In case that IN1+/− pins are used as full-differential mic input and LIN2/RIN2 pins are used as stereo line input, it is recommended that the following two modes are set by register setting according to each case. MDIF1 bit 1 0 MDIF2 bit 0 0 INL1 bit INL0 bit INR1 bit INR0 bit 0 0 0 1 0 1 0 1 Table 15. MIC/Line In Path Select Example MS0986-E-00 Lch IN1+/− LIN2 Rch RIN2 RIN2 2008/07 - 31 - [AK4645A] ■ MIC Gain Amplifier The AK4645A has a gain amplifier for microphone input. The gain of MIC-Amp is selected by the MGAIN1-0 bits (Table 16). The typical input impedance is 60kΩ(typ)@MGAIN1-0 bits = “00” or 30kΩ(typ)@MGAIN1-0 bits = “01”, “10” or “11”. MGAIN1 bit 0 0 1 1 MGAIN0 bit Input Gain 0 0dB 1 +20dB 0 +26dB 1 +32dB Table 16. Mic Input Gain (default) ■ MIC Power When PMMP bit = “1”, the MPWR pin supplies power for the microphone. This output voltage is typically 0.75 x AVDD and the load resistance is minimum 0.5kΩ. In case of using two sets of stereo mic, the load resistance is minimum 2kΩ for each channel. Capacitor must not be connected directly to MPWR pin (Figure 27). PMMP bit MPWR pin 0 Hi-Z 1 Output Table 17. MIC Power (default) MIC Power ≥ 2kΩ ≥ 2kΩ ≥ 2kΩ ≥ 2kΩ MPWR pin Microphone LIN1 pin Microphone RIN1 pin Microphone LIN2 pin Microphone RIN2 pin Figure 27. MIC Block Circuit MS0986-E-00 2008/07 - 32 - [AK4645A] ■ Digital EQ/HPF/LPF The AK4645A performs wind-noise reduction filter, stereo separation emphasis, gain compensation and ALC (Automatic Level Control) by digital domain for A/D converted data (Figure 28). FIL1, FIL3 and EQ blocks are IIR filters of 1st order. The filter coefficient of FIL3, EQ and FIL1 blocks can be set to any value. Refer to the section of “ALC operation” about ALC. When only DAC is powered-up, digital EQ/HPF/LPF circuit operates at playback path. When only ADC is powered-up or both ADC and DAC are powered-up, digital EQ/HPF/LPF circuit operates at recording path. Even if the path is switched from recording to playback, the register setting of filter coefficient at recording remains. Therefore, FIL3, EQ, FIL1 and GN1-0 bits should be set to “0” if digital EQ/HPF/LPF is not used for playback path. PMADL bit, PMADR bit “00” PMDAC bit LOOP bit Status Digital EQ/HPF/LPF 0 x Power-down Power-down (default ) x Playback Playback path x Recording Recording path 0 Recording & Playback Recording path 1 1 Recording Monitor Playback Recording path Note 38. Stereo separation emphasis circuit is effective only at stereo operation. Table 18. Digital EQ/HPF/LPF Cirtcuit Setting (x: Don’t care) “01”, “10” or “11” 1 0 FIL3 coefficient also sets the attenuation of the stereo separation emphasis. The combination of GN1-0 bit (Table 19) and EQ coefficient set the compensation gain. FIL1 and FIL3 blocks become HPF when F1AS and F3AS bits are “0” and become LPF when F1AS and F3AS bits are “1”, respectively. When EQ and FIL1 bits are “0”, EQ and FIL1 blocks become “through” (0dB). When FIL3 bit is “0”, FIL3 block become “MUTE”. When each filter coefficient is changed, each filter should be set to “through” (“MUTE” in case of FIL3). When MIX bit = “1”, only FIL1 is available. In this case, EQ and FIL3 bits should be set to “0”. Wind-noise reduction FIL1 An y coefficient F1A13-0 F1B13-0 F1AS Stereo separation emphasis FIL3 Gain compensation EQ An y coefficient 0dB ∼ -10dB F3A13-0 MUTE F3B13-0 (set by F3AS FIL3 coefficient) Gain ALC An y coefficient GN1-0 EQA15-0 +24/+12/0dB EQB13-0 EQC15-0 +12dB ∼ 0dB Figure 28. Digital EQ/HPF/LPF GN1 GN0 Gain 0 0 0dB (default) 0 1 +12dB 1 x +24dB Table 19. Gain select of gain block (x: Don’t care) MS0986-E-00 2008/07 - 33 - [AK4645A] [Filter Coefficient Setting] 1) When FIL1 and FIL3 are set to “HPF” fs: Sampling frequency fc: Cut-off frequency f: Input signal frequency K: Filter gain [dB] (Filter gain of should be set to 0dB.) Register setting FIL1: F1AS bit = “0”, F1A[13:0] bits =A, F1B[13:0] bits =B FIL3: F3AS bit = “0”, F3A[13:0] bits =A, F3B[13:0] bits =B (MSB=F1A13, F1B13, F3A13, F3B13; LSB=F1A0, F1B0, F3A0, F3B0) 1 − 1 / tan (πfc/fs) 1 / tan (πfc/fs) A = 10K/20 x , B= 1 + 1 / tan (πfc/fs) 1 + 1 / tan (πfc/fs) Transfer function Amplitude 1 − z −1 H(z) = A 2 − 2cos (2πf/fs) M(f) = A 1 + Bz −1 Phase θ(f) = tan −1 1 + B2 + 2Bcos (2πf/fs) (B+1)sin (2πf/fs) 1 - B + (B−1)cos (2πf/fs) 2) When FIL1 and FIL3 are set to “LPF” fs: Sampling frequency fc: Cut-off frequency f: Input signal frequency K: Filter gain [dB] (Filter gain of FIL1 should be set to 0dB.) Register setting FIL1: F1AS bit = “1”, F1A[13:0] bits =A, F1B[13:0] bits =B FIL3: F3AS bit = “1”, F3A[13:0] bits =A, F3B[13:0] bits =B (MSB=F1A13, F1B13, F3A13, F3B13; LSB=F1A0, F1B0, F3A0, F3B0) 1 − 1 / tan (πfc/fs) 1 A = 10K/20 x , 1 + 1 / tan (πfc/fs) Transfer function 1 + Bz −1 1 + 1 / tan (πfc/fs) Amplitude 1 + z −1 H(z) = A B= 2 + 2cos (2πf/fs) M(f) = A 1 + B2 + 2Bcos (2πf/fs) MS0986-E-00 Phase θ(f) = tan −1 (B−1)sin (2πf/fs) 1 + B + (B+1)cos (2πf/fs) 2008/07 - 34 - [AK4645A] 3) EQ fs: Sampling frequency fc1: Pole frequency fc2: Zero-point frequency f: Input signal frequency K: Filter gain [dB] (Maximum +12dB) Register setting EQA[15:0] bits =A, EQB[13:0] bits =B, EQC[15:0] bits =C (MSB=EQA15, EQB13, EQC15; LSB=EQA0, EQB0, EQC0) A = 10K/20 x 1 − 1 / tan (πfc1/fs) 1 + 1 / tan (πfc2/fs) , B= 1 + 1 / tan (πfc1/fs) A + Cz Amplitude −1 1 + Bz −1 C =10K/20 x 1 + 1 / tan (πfc1/fs) Transfer function H(z) = , 2 1 − 1 / tan (πfc2/fs) 1 + 1 / tan (πfc1/fs) Phase 2 A + C + 2ACcos (2πf/fs) M(f) = 1 + B2 + 2Bcos (2πf/fs) θ(f) = tan −1 (AB−C)sin (2πf/fs) A + BC + (AB+C)cos (2πf/fs) [Translation the filter coefficient calculated by the equations above from real number to binary code (2’s complement)] X = (Real number of filter coefficient calculated by the equations above) x 213 X should be rounded to integer, and then should be translated to binary code (2’s complement). MSB of each filter coefficient setting register is sine bit. [Filter Coefficient Setting Example] 1) FIL1 block Example: HPF, fs=44.1kHz, fc=100Hz F1AS bit = “0” F1A[13:0] bits = 01 1111 1100 0110 F1B[13:0] bits = 10 0000 0111 0100 2) EQ block Example: fs=44.1kHz, fc1=300Hz, fc2=3000Hz, Gain=+8dB Gain[dB] +8dB fc1 fc2 Frequency EQA[15:0] bits = 0000 1001 0110 1110 EQB[13:0] bits = 10 0001 0101 1001 EQC[15:0] bits = 1111 1001 1110 1111 MS0986-E-00 2008/07 - 35 - [AK4645A] ■ ALC Operation The ALC (Automatic Level Control) is operated by ALC block when ALC bit is “1”. When only DAC is powered-up, ALC circuit operates at playback path. When only ADC is powered-up or both ADC and DAC are powered-up, ALC circuit operates at recording path. PMADL bit, PMADR bit PMDAC bit 0 1 0 “00” “01”, “10” or “11” 1. 1 LOOP bit Status x Power-down x Playback x Recording 0 Recording & Playback 1 Recording Monitor Playback Table 20. ALC Setting (x: Don’t care) Digital EQ/HPF/LPF Power-down Playback path Recording path Recording path Recording path (default) ALC Limiter Operation During the ALC limiter operation, when either Lch or Rch exceeds the ALC limiter detection level (Table 21), the IVL and IVR values (same value) are attenuated automatically by the amount defined by the ALC limiter ATT step (Table 22). The IVL and IVR are then set to the same value for both channels. When ZELMN bit = “0” (zero cross detection is enabled), the IVL and IVR values are changed by ALC limiter operation at the individual zero crossing points of Lch and Rch or at the zero crossing timeout. ZTM1-0 bits set the zero crossing timeout period of both ALC limiter and recovery operation (Table 23). When ZELMN bit = “1” (zero cross detection is disabled), IVL and IVR values are immediately (period: 1/fs) changed by ALC limiter operation. Attenuation step is fixed to 1 step regardless of the setting of LMAT1-0 bits. The attenuation operation is executed continuously until the input signal level becomes ALC limiter detection level (Table 21) or less. After completing the attenuate operation, unless ALC bit is changed to “0”, the operation repeats when the input signal level exceeds LMTH1-0 bits. LMTH1 0 0 1 1 LMTH0 0 1 0 1 ALC Limier Detection Level ALC Recovery Waiting Counter Reset Level ALC Output ≥ −2.5dBFS −2.5dBFS > ALC Output ≥ −4.1dBFS ALC Output ≥ −4.1dBFS −4.1dBFS > ALC Output ≥ −6.0dBFS ALC Output ≥ −6.0dBFS −6.0dBFS > ALC Output ≥ −8.5dBFS ALC Output ≥ −8.5dBFS −8.5dBFS > ALC Output ≥ −12dBFS Table 21. ALC Limiter Detection Level / Recovery Counter Reset Level ZELMN 0 1 ZTM1 ZTM0 0 0 1 1 0 1 0 1 LMAT1 LMAT0 ALC Limiter ATT Step 0 0 1 step 0.375dB 0 1 2 step 0.750dB 1 0 4 step 1.500dB 1 1 8 step 3.000dB x x 1step 0.375dB Table 22. ALC Limiter ATT Step (x: Don’t care) (default) Zero Crossing Timeout Period 8kHz 16kHz 44.1kHz 128/fs 16ms 8ms 2.9ms 256/fs 32ms 16ms 5.8ms 512/fs 64ms 32ms 11.6ms 1024/fs 128ms 64ms 23.2ms Table 23. ALC Zero Crossing Timeout Period MS0986-E-00 (default) (default) 2008/07 - 36 - [AK4645A] 2. ALC Recovery Operation The ALC recovery operation waits for the WTM2-0 bits (Table 24) to be set after completing the ALC limiter operation. If the input signal does not exceed “ALC recovery waiting counter reset level” (Table 21) during the wait time, the ALC recovery operation is executed. The IVL and IVR values are automatically incremented by RGAIN1-0 bits (Table 25) up to the set reference level (Table 26) with zero crossing detection which timeout period is set by ZTM1-0 bits (Table 23). Then the IVL and IVR are set to the same value for both channels. The ALC recovery operation is executed at a period set by WTM2-0 bits. When zero cross is detected at both channels during the wait period set by WTM2-0 bits, the ALC recovery operation waits until WTM2-0 period and the next recovery operation is executed. If ZTM1-0 is longer than WTM2-0 and no zero crossing occurs, the ALC recovery operation is executed at a period set by ZTM1-0 bits. For example, when the current IVOL value is 30H and RGAIN1-0 bits are set to “01”, IVOL is changed to 32H by the auto limiter operation and then the input signal level is gained by 0.75dB (=0.375dB x 2). When the IVOL value exceeds the reference level (REF7-0), the IVOL values are not increased. When “ALC recovery waiting counter reset level (LMTH1-0) ≤ Output Signal < ALC limiter detection level (LMTH1-0)” during the ALC recovery operation, the waiting timer of ALC recovery operation is reset. When “ALC recovery waiting counter reset level (LMTH1-0) > Output Signal”, the waiting timer of ALC recovery operation starts. The ALC operation corresponds to the impulse noise. When the impulse noise is input, the ALC recovery operation becomes faster than a normal recovery operation (Fast Recovery Operation). When large noise is input to microphone instantaneously, the quality of small level in the large noise can be improved by this fast recovery operation. The speed of fast recovery operation is set by RFST1-0 bits (Table 27). WTM2 WTM1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 ALC Recovery Operation Waiting Period 8kHz 16kHz 44.1kHz 0 128/fs 16ms 8ms 2.9ms 1 256/fs 32ms 16ms 5.8ms 0 512/fs 64ms 32ms 11.6ms 1 1024/fs 128ms 64ms 23.2ms 0 2048/fs 256ms 128ms 46.4ms 1 4096/fs 512ms 256ms 92.9ms 0 8192/fs 1024ms 512ms 185.8ms 1 16384/fs 2048ms 1024ms 371.5ms Table 24. ALC Recovery Operation Waiting Period WTM0 RGAIN1 0 0 1 1 RGAIN0 GAIN STEP 0 1 step 0.375dB 1 2 step 0.750dB 0 3 step 1.125dB 1 4 step 1.500dB Table 25. ALC Recovery GAIN Step MS0986-E-00 (default) (default) 2008/07 - 37 - [AK4645A] REF7-0 GAIN(dB) Step F1H +36.0 F0H +35.625 EFH +35.25 : : E2H +30.375 0.375dB E1H +30.0 (default) E0H +29.625 : : 03H −53.25 02H −53.625 01H −54.0 00H MUTE Table 26. Reference Level at ALC Recovery operation RFST1 bit 0 0 1 1 RFST0 bit Recovery Speed 0 4 times 1 8 times 0 16times 1 N/A Table 27. Fast Recovery Speed Setting MS0986-E-00 (default) 2008/07 - 38 - [AK4645A] 3. Example of ALC Operation Table 28 shows the examples of the ALC setting for mic recording. Register Name Comment LMTH1-0 ZELMN ZTM1-0 Limiter detection Level Limiter zero crossing detection Zero crossing timeout period Recovery waiting period *WTM2-0 bits should be the same or longer data as ZTM1-0 bits. Maximum gain at recovery operation WTM2-0 REF7-0 IVL7-0, IVR7-0 LMAT1-0 RGAIN1-0 RFST1-0 ALC Gain of IVOL Limiter ATT step Recovery GAIN step Fast Recovery Speed ALC enable Data 01 0 01 fs=8kHz Operation −4.1dBFS Enable 32ms Data 01 0 11 fs=44.1kHz Operation −4.1dBFS Enable 23.2ms 001 32ms 011 23.2ms E1H +30dB E1H +30dB E1H +30dB E1H +30dB 00 00 00 1 1 step 1 step 4 times Enable 00 1 step 00 1 step 00 4 times 1 Enable Table 28. Example of the ALC setting The following registers should not be changed during the ALC operation. These bits should be changed after the ALC operation is finished by ALC bit = “0” or PMADL=PMADR bits = “0”. • LMTH1-0, LMAT1-0, WTM2-0, ZTM1-0, RGAIN1-0, REF7-0, ZELMN, RFST1-0 Example: Limiter = Zero crossing Enable Recovery Cycle = 32ms@8kHz Zero Crossing Timeout Period = 32ms@8kHz Limiter and Recovery Step = 1 Fast Recovery Speed = 4 step Gain of IVOL = +30dB Maximum Gain = +30.0dB Limiter Detection Level = −4.1dBFS ALC bit = “1” Manual Mode WR (ZTM1-0, WTM2-0, RFST1-0) (1) Addr=06H, Data=14H WR (REF7-0) (2) Addr=08H, Data=E1H WR (IVL/R7-0) * The value of IVOL should be (3) Addr=09H&0CH, Data=E1H the same or smaller than REF’s WR (RGAIN1, LMTH1) (4) Addr=0BH, Data=00H WR (LMAT1-0, RGAIN0, ZELMN, LMTH0; ALC= “1”) (5) Addr=07H, Data=21H ALC Operation Note : WR : Write Figure 29. Registers set-up sequence at ALC operation MS0986-E-00 2008/07 - 39 - [AK4645A] ■ Input Digital Volume (Manual Mode) The input digital volume becomes manual mode when ALC bit is “0”. This mode is used in the case shown below. 1. 2. 3. After exiting reset state, set-up the registers for the ALC operation (ZTM1-0, LMTH1-0 and etc) When the registers for the ALC operation (Limiter period, Recovery period and etc) are changed. For example; when the change of the sampling frequency. When IVOL is used as a manual volume. IVL7-0 and IVR7-0 bits set the gain of the volume control (Table 29). The IVOL value is changed at zero crossing or timeout. Zero crossing timeout period is set by ZTM1-0 bits. If IVL7-0 or IVR7-0 bits are written during PMADL=PMADR bits = “0”, IVOL operation starts with the written values at the end of the ADC initialization cycle after PMADL or PMADR bit is changed to “1”. Even if the path is switched from recording to playback, the register setting of IVOL remains. Therefore, IVL7-0 and IVR7-0 bits should be set to “91H” (0dB). IVL7-0 IVR7-0 F1H F0H EFH : E2H E1H E0H : 03H 02H 01H 00H GAIN (dB) Step +36.0 +35.625 +35.25 : +30.375 0.375dB +30.0 +29.625 : −53.25 −53.625 −54 MUTE Table 29. Input Digital Volume Setting MS0986-E-00 (default) 2008/07 - 40 - [AK4645A] When writing to the IVL7-0 and IVR7-0 bits continuouslly, the control register should be written by an interval more than zero crossing timeout. If not, IVL and IVR are not changed since zero crossing counter is reset at every write operation. If the same register value as the previous write operation is written to IVL and IVR, zero crossing counter is not reset. Therefore, IVL and IVR can be written by an interval less than zero crossing timeout. ALC bit ALC Status Disable Enable IVL7-0 bits E1H(+30dB) IVR7-0 bits C6H(+20dB) Internal IVL E1H(+30dB) Internal IVR C6H(+20dB) E1(+30dB) --> F1(+36dB) (1) Disable E1(+30dB) (2) E1(+30dB) --> F1(+36dB) C6H(+20dB) Figure 30. IVOL value during ALC operation (1) The IVL value becomes the start value if the IVL and IVR are different when the ALC starts. The wait time from ALC bit = “1” to ALC operation start by IVL7-0 bits is at most recovery time (WTM2-0 bits) plus zerocross timeout period (ZTM1-0 bits). (2) Writing to IVL and IVR registers (09H and 0CH) is ignored during ALC operation. After ALC is disabled, the IVOL changes to the last written data by zero crossing or timeout. When ALC is enabled again, ALC bit should be set to “1” by an interval more than zero crossing timeout period after ALC bit = “0”. MS0986-E-00 2008/07 - 41 - [AK4645A] ■ De-emphasis Filter The AK4645A includes the digital de-emphasis filter (tc = 50/15μs) by IIR filter. Setting the DEM1-0 bits enables the de-emphasis filter (Table 30). DEM1 0 0 1 1 DEM0 Mode 0 44.1kHz 1 OFF (default) 0 48kHz 1 32kHz Table 30. De-emphasis Control ■ Bass Boost Function The BST1-0 bits control the amount of low frequency boost applied to the DAC output signal (Table 31). If the BST1-0 bits are set to “01” (MIN Level), use a 47μF capacitor for AC-coupling. If the boosted signal exceeds full scale, the analog output clips to the full scale. Figure 31 shows the boost frequency response at –20dB signal input. Boost Filter (fs=44.1kHz) 0 MAX Level [dB] -5 MID -10 MIN -15 -20 -25 10 100 1000 10000 Frequency [Hz] Figure 31. Bass Boost Frequency Response (fs=44.1kHz) BST1 0 0 1 1 BST0 Mode 0 OFF 1 MIN 0 MID 1 MAX Table 31. Bass Boost Control MS0986-E-00 (default) 2008/07 - 42 - [AK4645A] ■ Digital Output Volume The AK4645A has a digital output volume (256 levels, 0.5dB step, Mute). The volume can be set by the DVL7-0 and DVR7-0 bits. The volume is included in front of the DAC block. The input data of DAC is changed from +12 to –115dB or MUTE. When the DVOLC bit = “1”, the DVL7-0 bits control both Lch and Rch attenuation levels. When the DVOLC bit = “0”, the DVL7-0 bits control Lch level and DVR7-0 bits control Rch level. This volume has a soft transition function. The DVTM bit sets the transition time between set values of DVL/R7-0 bits as either 1061/fs or 256/fs (Table 33). When DVTM bit = “0”, a soft transition between the set values occurs (1062 levels). It takes 1061/fs (=24ms@fs=44.1kHz) from 00H (+12dB) to FFH (MUTE). DVL/R7-0 00H 01H 02H : 18H : FDH FEH FFH DVTM bit 0 1 Gain Step +12.0dB +11.5dB +11.0dB : 0.5dB 0dB : −114.5dB −115.0dB MUTE (−∞) Table 32. Digital Volume Code Table (default) Transition time between DVL/R7-0 bits = 00H and FFH Setting fs=8kHz fs=44.1kHz 1061/fs 133ms 24ms 256/fs 32ms 6ms Table 33. Transition Time Setting of Digital Output Volume MS0986-E-00 (default) 2008/07 - 43 - [AK4645A] ■ Soft Mute Soft mute operation is performed in the digital domain. When the SMUTE bit goes to “1”, the output signal is attenuated by −∞ (“0”) during the cycle set by the DVTM bit. When the SMUTE bit is returned to “0”, the mute is cancelled and the output attenuation gradually changes to the value set by the DVL/R7-0 bits during the cycle set of the DVTM bit. If the soft mute is cancelled within the cycle set by the DVTM bit after starting the operation, the attenuation is discontinued and returned to the value set by the DVL/R7-0 bits. The soft mute is effective for changing the signal source without stopping the signal transmission (Figure 32). S M U T E bit D VTM bit D VL/R 7-0 bits D VTM bit (1) (3) A ttenuation -∞ GD (2) GD A nalog O utput Figure 32. Soft Mute Function (1) The output signal is attenuated until −∞ (“0”) by the cycle set by the DVTM bit. (2) Analog output corresponding to digital input has group delay (GD). (3) If the soft mute is cancelled within the cycle set by the DVTM bit, the attenuation is discounted and returned to the value set by the DVL/R7-0 bits. MS0986-E-00 2008/07 - 44 - [AK4645A] ■ Analog Mixing: Stereo Input (LIN2/RIN2/LIN4/RIN4, AIN3 bit = “1”: LIN3/RIN3 pins) When PMAINL2=PMAINR2 bits = “1”, LIN2 and RIN2 pins can be used as stereo line input for analog mixing. When LINH2 and RINH2 bits are set to “1”, the input signal from the LIN2/RIN2 pins is output to Headphone-Amp. When LINL2/RINR2 bits are set to “1”, the input signal from the LIN2/RIN2 pins is output to the stereo line output amplifier. When PMAINL4=PMAINR4 bits = “1”, LIN4 and RIN4 pins can be used as stereo line input for analog mixing. When LINH4 and RINH4 bits are set to “1”, the input signal from the LIN4/RIN4 pins is output to Headphone-Amp. When LINL4/RINR4 bits are set to “1”, the input signal from the LIN4/RIN4 pins is output to the stereo line output amplifier. When the analog mixing is used, A/D converter is also available if PMADL or PMADR bit is “1”. In this case, the input resistance of LIN2/RIN2/LIN4/RIN4 pins becomes 30kΩ (typ) at MGAIN1-0 bits = “00” and 20kΩ (typ) at MGAIN1-0 bits = “01”, “10” or “11”, respectively. When AIN3 bit = “1”, MIN and VCOC pins becomes LIN3 and RIN3 pins, respectively. When PMAINL3=PMAINR3 bits = “1”, LIN3 and RIN3 pins can be used as stereo line input for analog mixing. When PMMICL=PMMICR=MICL3=MICR3 bits = “1”, analog mixing source is changed from LIN3/RIN3 iput to MIC-Amp output signal. When the LINH3 and RINH3 bits are set to “1”, the input signal from the LIN3/RIN3 pins is output to Headphone-Amp. When the LINL3/RINR3 bits are set to “1”, the input signal from the LIN3/RIN3 pins is output to the stereo line output amplifier. When the analog mixing is used, A/D converter is also available if PMADL or PMADR bit is “1”. When the analog mixing is used at MICL3=MICR3 bits = “0”, the input resistance of LIN3/RIN3 pins becomes 30kΩ (typ) at MGAIN1-0 bits = “00” and 20kΩ (typ) at MGAIN1-0 bits = “01”, “10” or “11”, respectively. When the analog mixing is used at MICL3=MICR3 bits = “1”, the input resistance of LIN3/RIN3 pins becomes 60kΩ (typ) at MGAIN1-0 bits = “00” and 30kΩ (typ) at MGAIN1-0 bits = “01”, “10” or “11”, respectively. Table 34, Table 35 and Table 36 show the typical gain. AK4645A INL1-0 bits LIN1/IN1− pin ADC Lch RIN1/IN1+ pin MDIF1 bit MIC-Am p INR1-0 bits RIN2/IN2− pin ADC Rch LIN2/IN2+ pin MDIF2 bit MIC-Amp MIN/LIN3 pin MICR3 bit PMAINR3 bit PMAINR2 bit PMAINL2 bit PMAINR4 bit PMAINL4 bit RIN4/IN4− pin MICL3 bit LIN4/IN4+ pin PMAINL3 bit RIN3 pin Lineout, HP-Amp Figure 33. Analog Mixing Circuit (Stereo Input) MS0986-E-00 2008/07 - 45 - [AK4645A] PMAINL2 bit PMAINR2 bit LINL2/RINR2 LOUT/LOP pin, ROUT/LON pin LIN2/RIN2 LINH2/RINH2 HPL, HPR pins Figure 34. Analog Mixing Circuit (LIN2/RIN2) PMAINL4 bit PMAINR4 bit LINL4/RINR4 LOUT/LOP pin, ROUT/LON pin LIN4/RIN4 LINH4/RINH4 HPL, HPR pins Figure 35. Analog Mixing Circuit (LIN4/RIN4) PMAINL3 bit PMAINR3 bit LINL3/RINR3 LOUT/LOP pin, ROUT/LON pin LIN3/RIN3 LINH3/RINH3 HPL, HPR pins Figure 36. Analog Mixing Circuit (LIN3/RIN3) LOVL bit LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 Æ LOUT/ROUT 0 0dB (default) 1 +2dB Table 34. LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 Input Æ LOUT/ROUT Output Gain (typ) LOVL bit LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 Æ LOP/LON 0 0dB (default) 1 +2dB Table 35. LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 Input Æ LOP/LON Output Gain (typ) HPG bit LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 Æ HPL/HPR 0 0dB (default) 1 +3.6dB Table 36. LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 Input Æ Headphone-Amp Output Gain (typ) MS0986-E-00 2008/07 - 46 - [AK4645A] ■ Analog Mixing: Full-differentical Mono Input (L4DIF bit = “1”: IN4+/IN4− pins) When L4DIF bit = “1”, LIN4 and RIN4 pins becomes IN4+ and IN4− pins, respectively. When PMAINL4 bit = “1”, IN4+ and IN4− pins can be used as full-differentinal mono line input for analog mixing. When the LINH4 and RINH4 bits are set to “1”, the input signal from the IN4+/IN4− pins is output to Headphone-Amp. When the LINL4/RINR4 bits are set to “1”, the input signal from the IN4+/IN4− pins is output to the stereo line output amplifier. Table 37, Table 38 and Table 39 show the typical gain. Input signal amplitude is defined as (IN4+) − (IN4−). AK4645A MIC-Amp Lch LIN4/IN4+ pin L4DIF bit PMAINL4 bit MIC-Amp Rch RIN4/IN4− pin PMAINR4 bit Lineout, HP-Amp Figure 37. Full-differential Mono Analog Mixing Circuit LOVL bit IN4+/IN4− Æ LOUT/ROUT 0 (default) −6dB 1 −4dB Table 37. IN4+/IN4− Input Æ LOUT/ROUT Output Gain (typ) LOVL bit IN4+/IN4− Æ LOP/LON 0 0dB (default) 1 +2dB Table 38. IN4+/IN4− Input Æ LOP/LON Output Gain (typ) HPG bit IN4+/IN4− Æ HPL/HPR 0 (default) −6dB 1 −2.4dB Table 39. IN4+/IN4− Input Æ Headphone-Amp Output Gain (typ) MS0986-E-00 2008/07 - 47 - [AK4645A] ■ Analog Mixing: Mono Input (AIN3 bit = “0”: MIN pin) When AIN3 bit = “0”, the MIN pin is used as mono input for analog mixing. When the PMMIN bit is set to “1”, the mono input is powered-up. When the MINH bit is set to “1”, the input signal from the MIN pin is output to Headphone-Amp. When the MINL bit is set to “1”, the input signal from the MIN pin is output to the stereo line output amplifier. The external resister Ri adjusts the signal level of MIN input. Table 40, Table 41 and Table 42 show the typical gain example at Ri = 20kΩ. This gain is in inverse proportion to Ri . Ri MINL MIN LOUT/LOP pin, ROUT/LON pin MINH HPL, HPR pin Figure 38. Block Diagram of MIN pin LOVL bit MIN Æ LOUT/ROUT 0 0dB (default) 1 +2dB Table 40. MIN Input Æ LOUT/ROUT Output Gain (typ) at Ri = 20kΩ LOVL bit MIN Æ LOP/LON 0 +6dB (default) 1 +8dB Table 41. MIN Input Æ LOP/LON Output Gain (typ) at Ri = 20kΩ HPG bit MIN Æ HPL/HPR 0 (default) −20dB 1 −16.4dB Table 42. MIN Input Æ Headphone-Amp Output Gain (typ) at Ri = 20kΩ MS0986-E-00 2008/07 - 48 - [AK4645A] ■ Stereo Line Output (LOUT/ROUT pins) When DACL bit is “1”, Lch/Rch signal of DAC is output from the LOUT/ROUT pins which is single-ended. When DACL bit is “0”, output signal is muted and LOUT/ROUT pins output VCOM voltage. The load impedance is 10kΩ (min.). When the PMLO=LOPS bits = “0”, the stereo line output enters power-down mode and the output is pulled-down to AVSS by 100kΩ(typ). When the LOPS bit is “1”, stereo line output enters power-save mode. Pop noise at power-up/down can be reduced by changing PMLO bit at LOPS bit = “1”. In this case, output signal line should be pulled-down to AVSS by 20kΩ after AC coupled as Figure 40. Rise/Fall time is 300ms(max) at C=1μF and AVDD=3.3V. When PMLO bit = “1” and LOPS bit = “0”, stereo line output is in normal operation. LOVL bit set the gain of stereo line output. When LOM bit = “1”, DAC output signal is output to LOUT and ROUT pins as (L+R)/2 mono signal. When LOM3 bit = “1”, the signal selected by MICL3 and MICR3 bits (LIN3/RIN3 inputs or MIC-Amp outputs) to LOUT and ROUT pins as (L+R)/2 mono signal. “DACL” “LOVL” LOUT pin DAC ROUT pin Figure 39. Stereo Line Output LOPS 0 1 PMLO Mode LOUT/ROUT pin 0 Power-down Pull-down to AVSS 1 Normal Operation Normal Operation 0 Power-save Fall down to AVSS 1 Power-save Rise up to VCOM Table 43. Stereo Line Output Mode Select (x: Don’t care) (default) LOVL Gain Output Voltage (typ) 0 0dB 0.6 x AVDD (default) 1 +2dB 0.757 x AVDD Table 44. Stereo Line Output Volume Setting LOUT ROUT 1μF 220Ω 20kΩ Figure 40. External Circuit for Stereo Line Output (in case of using Pop Reduction Circuit) MS0986-E-00 2008/07 - 49 - [AK4645A] <Stereo Line Output Control Sequence (in case of using Pop Reduction Circuit)> (2 ) (5 ) P M L O b it (1 ) (3 ) (4 ) (6 ) L O P S b it L O U T , R O U T p in s N o r m a l O u tp u t ≥ 300 m s ≥ 300 m s Figure 41. Stereo Line Output Control Sequence (in case of using Pop Reduction Circuit) (1) Set LOPS bit = “1”. Stereo line output enters the power-save mode. (2) Set PMLO bit = “1”. Stereo line output exits the power-down mode. LOUT and ROUT pins rise up to VCOM voltage. Rise time is 200ms (max 300ms) at C=1μF and AVDD=3.3V. (3) Set LOPS bit = “0” after LOUT and ROUT pins rise up. Stereo line output exits the power-save mode. Stereo line output is enabled. (4) Set LOPS bit = “1”. Stereo line output enters power-save mode. (5) Set PMLO bit = “0”. Stereo line output enters power-down mode. LOUT and ROUT pins fall down to AVSS. Fall time is 200ms (max 300ms) at C=1μF and AVDD=3.3V. (6) Set LOPS bit = “0” after LOUT and ROUT pins fall down. Stereo line output exits the power-save mode. MS0986-E-00 2008/07 - 50 - [AK4645A] <Analog Mixing Circuit for Stereo Line Output> When AIN3 bit = “0”, DACL, MINL, LINL2, RINR2, LINL4 and RINR4 bits controls each path switch. MIN path mixing gain is 0dB(typ)@LOVL bit = “0” when the external input resistance is 20kΩ. LIN2, RIN2, LIN4, RIN4 and DAC pathe’s mixing gains are 0dB(typ)@LOVL bit = “0”. LINL2 bit LIN2 pin 0dB LIN4 pin 0dB LINL4 bit M MINL bit MIN pin 0dB I LOUT pin X DACL bit DAC Lch 0dB Figure 42. LOUT Mixing Circuit (AIN3 bit = “0”, LOVL bit = “0”) RINR2 bit RIN2 pin 0dB RINR4 bit RIN4 pin M 0dB MINL bit MIN pin 0dB I ROUT pin X DACL bit DAC Rch 0dB Figure 43. ROUT Mixing Circuit (AIN3 bit = “0”, LOVL bit = “0”) MS0986-E-00 2008/07 - 51 - [AK4645A] When AIN3 bit = “1”, DACL, LINL2, RINR2, LINL3, RINR3, LINL4, RINR4, MICL3 and MICR3 bits controls each path switch. All pathe’s mixing gains are 0dB(typ)@LOVL bit = “0”. LINL2 bit LIN2 pin 0dB LINL4 bit LIN4 pin 0dB MICL3 bit LIN3 pin LINL3 bit M I 0dB LOUT pin X LIN1 pin MIC-Amp Lch DACL bit DAC Lch 0dB Figure 44. LOUT Mixing Circuit (AIN3 bit = “1”, LOVL bit = “0”) RINR2 bit RIN2 pin 0dB RINR4 bit RIN4 pin 0dB MICR3 bit RIN3 pin RINR3 bit M I 0dB ROUT pin X RIN1 pin MIC-Amp Rch DACL bit DAC Rch 0dB Figure 45. ROUT Mixing Circuit (AIN3 bit = “1”, LOVL bit = “0”) MS0986-E-00 2008/07 - 52 - [AK4645A] ■ Full-differential Mono Line Output (LOP/LON pins) When LODIF bit = “1”, LOUT/ROUT pins become LOP/LON pins, respectively. Lch/Rch signal of DAC or LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 is output from the LOP/LON pins which is full-differential as (L+R)/2 signal. The load impedance is 10kΩ (min) for LOP and LON pins, respectively. When the PMLO bit = “0”, the mono line output enters power-down mode and the output is Hi-Z. When the PMLO bit is “1” and LOPS bit is “1”, mono line output enters power-save mode. Pop noise at power-up/down can be reduced by changing PMLO bit at LOPS bit = “0”. When PMLO bit = “1” and LOPS bit = “0”, mono line output enters in normal operation. LOVL bit set the gain of mono line output. When L4DIF=LODIF bits = “1”, full-differential output signal is as follows: (LOP) − (LON) = (IN4+) − (IN4−). “DACL” “LOVL” LOP pin DAC LON pin Figure 46. Mono Line Output PMLO 0 1 LOPS Mode LOP LON x Power-down Hi-Z Hi-Z 1 Power-save Hi-Z VCOM/2 0 Normal Operation Normal Operation Normal Operation Table 45. Mono Line Output Mode Setting (x: Don’t care) LOVL 0 1 (default) Gain Output Voltage (typ) +6dB 1.2 x AVDD (default) +8dB 1.5 x AVDD Table 46. Mono Line Output Volume Setting PMLO bit LOPS bit LOP pin LON pin Hi-Z Hi-Z Hi-Z VCOM VCOM Hi-Z Figure 47. Power-up/Power-down Timing for Mono Line Output MS0986-E-00 2008/07 - 53 - [AK4645A] <Analog Mixing Circuit for Mono Line Output> When AIN3 bit = “0”, DACL, MINL, LINL2, RINR2, LINL4 and RINR4 bits controls each path switch. MIN path mixing gain is +6dB(typ)@LOVL bit = “0” when the external input resistance is 20kΩ. LIN2, RIN2, LIN4, RIN4 and DAC pathes mixing gain is 0dB(typ)@LOVL bit = “0”. LINL2 bit LIN2 pin 0dB RIN2 pin 0dB RINR2 bit LINL4 bit LIN4 pin 0dB M RINR4 bit RIN4 pin LOP/N pin I 0dB X MINL bit MIN pin +6dB DACL bit DAC Lch 0dB DAC Rch 0dB DACL bit Figure 48. Mono Line Output Mixing Circuit (AIN3 bit = “0”, LOVL bit = “0”) When AIN3 bit = “1”, DACL, LINL2, RINR2, LINL3, RINR3, LINL4, RINR4, MICL3 and MICR3 bits controls each path switch. All pathe’s mixing gains are 0dB(typ)@LOVL bit = “0”. LINL2 bit LIN2 pin 0dB LINL4 bit LIN4 pin 0dB MICL3 bit LIN3 pin LIN1 pin LINL3 bit 0dB MIC-Amp Lch RINR2 bit RIN2 pin M 0dB RINR4 bit RIN4 pin 0dB MICR3 bit RIN3 pin RIN1 pin I LOP/N pin X RINR3 bit 0dB MIC-Amp Rch DACL bit DAC Lch 0dB DACL bit DAC Rch 0dB Figure 49. Mono Line Output Mixing Circuit (AIN3 bit = “1”, LOVL bit = “0”) MS0986-E-00 2008/07 - 54 - [AK4645A] ■ Headphone Output Power supply voltage for the Headphone-Amp is supplied from the HVDD pin and centered on the HVDD/2 voltage at VBAT bit = “0”. The load resistance is 16Ω (min). HPG bit selects the output voltage (Table 47). When HPM bit = “1”, DAC output signal is output to HPL and HPR pins as (L+R)/2 mono signal. When HPM3 bit = “1”, the signal selected by MICL3 and MICR3 bits (LIN3/RIN3 inputs or MIC-Amp outputs) to HPL and HPR pins as (L+R)/2 mono signal. HPG bit 0 1 Output Voltage [Vpp] 0.6 x AVDD 0.91 x AVDD Table 47. Headphone-Amp Output Voltage When the HPMTN bit is “0”, the common voltage of Headphone-Amp falls and the outputs (HPL and HPR pins) go to “L” (HVSS). When the HPMTN bit is “1”, the common voltage rises to HVDD/2 at VBAT bit = “0”. A capacitor between the MUTET pin and ground reduces pop noise at power-up. Rise/Fall time constant is in proportional to HVDD voltage and the capacitor at MUTET pin. [Example]: A capacitor between the MUTET pin and ground = 1.0μF, HVDD=3.3V: Rise/fall time constant: τ = 100ms(typ), 250ms(max) Time until the common goes to HVSS when HPMTN bit = “1” Æ “0”: 500ms(max) When PMHPL and PMHPR bits are “0”, the Headphone-Amp is powered-down, and the outputs (HPL and HPR pins) go to “L” (HVSS). PMHPL bit, PMHPR bit HPMTN bit HPL pin, HPR pin (1) (2) (3) (4) Figure 50. Power-up/Power-down Timing for Headphone-Amp (1) Headphone-Amp power-up (PMHPL, PMHPR bit = “1”). The outputs are still HVSS. (2) Headphone-Amp common voltage rises up (HPMTN bit = “1”). Common voltage of Headphone-Amp is rising. (3) Headphone-Amp common voltage falls down (HPMTN bit = “0”). Common voltage of Headphone-Amp is falling. (4) Headphone-Amp power-down (PMHPL, PMHPR bit = “0”). The outputs are HVSS. If the power supply is switched off or Headphone-Amp is powered-down before the common voltage goes to HVSS, some pop noise occurs. <External Circuit of Headphone-Amp > When BOOST=OFF, the cut-off frequency (fc) of Headphone-Amp depends on the external resistor and capacitor. This fc can be shifted to lower frequency by using bass boost function. Table 48 shows the cut off frequency and the output power for various resistor/capacitor combinations. The headphone impedance RL is 16Ω. Output powers are shown at HVDD = 3.0, 3.3 and 5.0V. The output voltage of headphone is 0.6 x AVDD (Vpp) @HPG bit = “0” and 0.91 x AVDD (Vpp) @HPG bit = “1”. When an external resistor R is smaller than 12Ω, put an oscillation prevention circuit (0.22μF±20% capacitor and 10Ω±20% resistor) because it has the possibility that Headphone-Amp oscillates. MS0986-E-00 2008/07 - 55 - [AK4645A] HP-AMP C AK4645A 0.22μ R Headphone 16Ω 10Ω Figure 51. External Circuit Example of Headphone HPG bit R [Ω] fc [Hz] BOOST =OFF C [μF] 220 100 100 0 6.8 47 100 16 47 220 0 100 1 22 100 10 Note 39. Output power at 16Ω load. Note 40. Output signal is clipped. 0 45 100 70 149 50 106 45 100 62 137 fc [Hz] BOOST =MIN @fs=44.1kHz 17 43 28 78 19 47 17 43 25 69 Output Power [mW]@0dBFS HVDD=3.0V AVDD=3.0V HVDD=3.3V AVDD=3.3V HVDD=5V AVDD=3.3V 25.3 30.6 30.6 12.5 15.1 15.1 6.3 7.7 7.7 51 (Note 40) 62 (Note 40) 70 1.1 1.3 1.3 Table 48. External Circuit Example <Headphone-Amp PSRR> When HVDD is directly supplied from the battery in a mobile phone system, RF noise may influences headphone output performance. When VBAT bit is set to “1”, HP-Amp PSRR for the noise applied to HVDD is reduced. In this case, HP-Amp common voltage is 0.64 x AVDD (typ). When AVDD is 3.3V, common voltage is 2.1V. Therefore, when HVDD voltage becomes lower than 4.2V, the output signal will be clipped easily. VBAT bit Common Voltage [V] 0 0.5 x HVDD Table 49. HP-Amp Common Voltage 1 0.64 x AVDD <Wired OR with External Headphone-Amp> When PMVCM=PMHPL=PMHPR bits = “0” and HPZ bit = “1”, HP-Amp is powered-down and HPL/R pins are pulled-down to HVSS by 200kΩ (typ). In this setting, it is available to connect HP-Amp of AK4645A and external single supply HP-Amp by “wired OR”. In this mode, power supply current is 20μA(typ). PMVCM x 0 1 1 PMHPL/R 0 0 1 1 HPMTN HPZ Mode x 0 Power-down & Mute x 1 Power-down 0 x Mute 1 x Normal Operation Table 50. HP-Amp Mode Setting (x: Don’t care) MS0986-E-00 HPL/R pins HVSS Pull-down by 200kΩ HVSS Normal Operation (default) 2008/07 - 56 - [AK4645A] HPL pin AK4645A Headphone HPR pin Another HP-Amp Figure 52. Wired OR with External HP-Amp <Analog Mixing Circuit for Headphone Output> When AIN3 bit = “0”, DACH, MINH, LINH2, RINH2, LINH4 and RINH4 bits controls each path switch. MIN path mixing gain is −20dB(typ)@HPG bit = “0” when the external input resistance is 20kΩ. LIN2, RIN2, LIN4, RIN4 and DAC pathes mixing gain is 0dB(typ)@HPG bit = “0”. LINH2 bit LIN2 pin 0dB LINH4 bit LIN4 pin M 0dB MINH bit −20dB MIN pin I HPL pin X DACH bit DAC Lch 0dB Figure 53. HPL Mixing Circuit (AIN3 bit = “0”, HPG bit = “0”) RINH2 bit RIN2 pin 0dB RINH4 bit RIN4 pin M 0dB MINH bit −20dB MIN pin I HPR pin X DACH bit DAC Rch 0dB Figure 54. HPR Mixing Circuit (AIN3 bit = “0”, HPG bit = “0”) MS0986-E-00 2008/07 - 57 - [AK4645A] When AIN3 bit = “1”, DACH, LINH2, RINH2, LINH3, RINH3, LINH4, RINH4, MICL3 and MICR3 bits controls each path switch. All pathe’s mixing gains are 0dB(typ)@HPG bit = “0”. LINH2 bit LIN2 pin 0dB LINH4 bit LIN4 pin 0dB MICL3 bit LIN3 pin LINH3 bit M I 0dB HPL pin X LIN1 pin MIC-Amp Lch DACH bit DAC Lch 0dB Figure 55. HPL Mixing Circuit (AIN3 bit = “1”, HPG bit = “0”) RINH2 bit RIN2 pin 0dB RINH4 bit RIN4 pin 0dB MICR3 bit RIN3 pin RINH3 bit M I 0dB HPR pin X RIN1 pin MIC-Amp Rch DACH bit DAC Rch 0dB Figure 56. HPR Mixing Circuit (AIN3 bit = “1”, HPG bit = “0”) MS0986-E-00 2008/07 - 58 - [AK4645A] ■ Serial Control Interface (1) 3-wire Serial Control Mode (I2C pin = “L”) Internal registers may be written by using the 3-wire µP interface pins (CSN, CCLK and CDTI). The data on this interface consists of a 1-bit Chip address (Fixed to “1”), Read/Write (Fixed to “1”), Register address (MSB first, 6bits) and Control data (MSB first, 8bits). Each bit is clocked in on the rising edge (“↑”) of CCLK. Address and data are latched on the 16th CCLK rising edge (“↑”) after CSN falling edge(“↓”). CSN should be set to “H” once after 16 CCLKs for each address. Clock speed of CCLK is 5MHz (max). The value of internal registers are initialized by PDN pin = “L”. CSN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CCLK Clock, “H” or “L” CDTI “H” or “L” Clock, “H” or “L” C1 A5 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 “1” “1” C1: R/W: A5-A0: D7-D0: “H” or “L” Chip Address; Fixed to “1” READ/WRITE (“1”: WRITE, “0”: READ); Fixed to “1” Register Address Control data Figure 57. Serial Control I/F Timing MS0986-E-00 2008/07 - 59 - [AK4645A] (2) I2C-bus Control Mode (I2C pin = “H”) The AK4645A supports the fast-mode I2C-bus (max: 400kHz). Pull-up resistors at SDA and SCL pins should be connected to (TVDD+0.3)V or less voltage. (2)-1. WRITE Operations Figure 58 shows the data transfer sequence for the I2C-bus mode. All commands are preceded by START condition. A HIGH to LOW transition on the SDA line while SCL is HIGH indicates START condition (Figure 64). After the START condition, a slave address is sent. This address is 7 bits long followed by the eighth bit that is a data direction bit (R/W). The most significant six bits of the slave address are fixed as “001001”. The next bit is CAD0 (device address bit). This bit identifies the specific device on the bus. The hard-wired input pin (CAD0 pin) sets these device address bits (Figure 59). If the slave address matches that of the AK4645A, the AK4645A generates an acknowledge and the operation is executed. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse (Figure 65). R/W bit value of “1” indicates that the read operation is to be executed. “0” indicate that the write operation is to be executed. The second byte consists of the control register address of the AK4645A. The format is MSB first, and those most significant 2-bits are fixed to zeros (Figure 60). The data after the second byte contains control data. The format is MSB first, 8bits (Figure 61). The AK4645A generates an acknowledge after each byte has been received. A data transfer is always terminated by STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is HIGH defines STOP condition (Figure 64). The AK4645A can perform more than one byte write operation per sequence. After receiving the third byte the AK4645A generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. After receiving each data packet the internal 6-bit address counter is incremented by one, and the next data is automatically taken into the next address. If the address exceeds 24H prior to generating stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten. The data on the SDA line must remain stable during the HIGH period of the clock. HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW (Figure 66) except for the START and STOP conditions. S T A R T SDA S T O P R/W="0" Slave S Address Sub Address(n) Data(n) A C K A C K Data(n+1) A C K Data(n+x) A C K A C K P A C K Figure 58. Data Transfer Sequence at the I2C-Bus Mode 0 0 1 0 0 1 CAD0 R/W (Those CAD1/0 should match with CAD1/0 pins) Figure 59. The First Byte 0 0 A5 A4 A3 A2 A1 A0 D2 D1 D0 Figure 60. The Second Byte D7 D6 D5 D4 D3 Figure 61. Byte Structure after the second byte MS0986-E-00 2008/07 - 60 - [AK4645A] (2)-2. READ Operations Set the R/W bit = “1” for the READ operation of the AK4645A. After transmission of data, the master can read the next address’s data by generating an acknowledge instead of terminating the write cycle. After receiving each data packet the internal 6-bit address counter is incremented by one, and the next data is automatically taken into the next address. If the address exceeds 24H prior to generating a stop condition, the address counter will “roll over” to 00H and the data of 00H will be read out. The AK4645A supports two basic read operations: CURRENT ADDRESS READ and RANDOM ADDRESS READ. (2)-2-1. CURRENT ADDRESS READ The AK4645A contains an internal address counter that maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either a read or write) were to address “n”, the next CURRENT READ operation would access data from the address “n+1”. After receiving the slave address with R/W bit set to “1”, the AK4645A generates an acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal address counter by 1. If the master does not generate an acknowledge but instead generates stop condition, the AK4645A ceases transmission. S T A R T SDA S T O P R/W="1" Slave S Address Data(n) A C K Data(n+1) Data(n+2) A C K A C K Data(n+x) A C K A C K P A C K Figure 62. CURRENT ADDRESS READ (2)-2-2. RANDOM ADDRESS READ The random read operation allows the master to access any memory location at random. Prior to issuing the slave address with the R/W bit set to “1”, the master must first perform a “dummy” write operation. The master issues a start request, a slave address (R/W bit = “0”) and then the register address to read. After the register address is acknowledged, the master immediately reissues the start request and the slave address with the R/W bit set to “1”. The AK4645A then generates an acknowledge, 1 byte of data and increments the internal address counter by 1. If the master does not generate an acknowledge but instead generates stop condition, the AK4645A ceases transmission. S T A R T SDA S T A R T R/W="0" Slave S Address Slave S Address Sub Address(n) A C K A C K S T O P R/W="1" Data(n) A C K Data(n+1) A C K Data(n+x) A C K A C K P A C K Figure 63. RANDOM ADDRESS READ MS0986-E-00 2008/07 - 61 - [AK4645A] SDA SCL S P start condition stop condition Figure 64. START and STOP Conditions DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER 2 1 8 9 S clock pulse for acknowledgement START CONDITION Figure 65. Acknowledge on the I2C-Bus SDA SCL data line stable; data valid change of data allowed Figure 66. Bit Transfer on the I2C-Bus MS0986-E-00 2008/07 - 62 - [AK4645A] ■ Register Map Addr 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H Register Name Power Management 1 Power Management 2 Signal Select 1 Signal Select 2 Mode Control 1 Mode Control 2 Timer Select ALC Mode Control 1 ALC Mode Control 2 Lch Input Volume Control Lch Digital Volume Control ALC Mode Control 3 Rch Input Volume Control Rch Digital Volume Control Mode Control 3 Mode Control 4 Power Management 3 Digital Filter Select FIL3 Co-efficient 0 FIL3 Co-efficient 1 FIL3 Co-efficient 2 FIL3 Co-efficient 3 EQ Co-efficient 0 EQ Co-efficient 1 EQ Co-efficient 2 EQ Co-efficient 3 EQ Co-efficient 4 EQ Co-efficient 5 FIL1 Co-efficient 0 FIL1 Co-efficient 1 FIL1 Co-efficient 2 FIL1 Co-efficient 3 Power Management 4 Mode Control 5 Lineout Mixing Select HP Mixing Select Reserved D7 0 HPZ 0 LOVL 0 0 DVTM 0 REF7 D6 PMVCM HPMTN 0 LOPS 0 0 WTM2 0 REF6 D5 PMMIN PMHPL 0 MGAIN1 0 FS3 ZTM1 ALC REF5 D4 0 PMHPR DACL 0 0 MSBS ZTM0 ZELMN REF4 D3 PMLO M/S 0 0 BCKO BCKP WTM1 LMAT1 REF3 D2 PMDAC 0 PMMP MINL 0 FS2 WTM0 LMAT0 REF2 D1 0 0 0 0 DIF1 FS1 RFST1 RGAIN0 REF1 D0 PMADL 0 MGAIN0 0 DIF0 FS0 RFST0 LMTH0 REF0 IVL7 IVL6 IVL5 IVL4 IVL3 IVL2 IVL1 IVL0 DVL7 RGAIN1 IVR7 DVR7 0 0 INR1 GN1 F3A7 F3AS F3B7 0 EQA7 EQA15 EQB7 0 EQC7 EQC15 F1A7 F1AS F1B7 0 DVL6 LMTH1 IVR6 DVR6 LOOP 0 INL1 GN0 F3A6 0 F3B6 0 EQA6 EQA14 EQB6 0 EQC6 EQC14 F1A6 0 F1B6 0 DVL5 0 IVR5 DVR5 SMUTE 0 HPG 0 F3A5 F3A13 F3B5 F3B13 EQA5 EQA13 EQB5 EQB13 EQC5 EQC13 F1A5 F1A13 F1B5 F1B13 DVL4 0 IVR4 DVR4 DVOLC 0 MDIF2 FIL1 F3A4 F3A12 F3B4 F3B12 EQA4 EQA12 EQB4 EQB12 EQC4 EQC12 F1A4 F1A12 F1B4 F1B12 DVL3 0 IVR3 DVR3 BST1 IVOLC MDIF1 EQ F3A3 F3A11 F3B3 F3B11 EQA3 EQA11 EQB3 EQB11 EQC3 EQC11 F1A3 F1A11 F1B3 F1B11 DVL2 0 IVR2 DVR2 BST0 HPM INR0 FIL3 F3A2 F3A10 F3B2 F3B10 EQA2 EQA10 EQB2 EQB10 EQC2 EQC10 F1A2 F1A10 F1B2 F1B10 DVL1 VBAT IVR1 DVR1 DEM1 MINH INL0 0 F3A1 F3A9 F3B1 F3B9 EQA1 EQA9 EQB1 EQB9 EQC1 EQC9 F1A1 F1A9 F1B1 F1B9 DVL0 0 IVR0 DVR0 DEM0 DACH PMADR 0 F3A0 F3A8 F3B0 F3B8 EQA0 EQA8 EQB0 EQB8 EQC0 EQC8 F1A0 F1A8 F1B0 F1B8 PMAINR4 PMAINL4 PMAINR3 PMAINL3 PMAINR2 PMAINL2 PMMICR PMMICL 0 LOM 0 0 0 LOM3 HPM3 0 MICR3 RINR4 RINH4 0 MICL3 LINL4 LINH4 0 L4DIF RINR3 RINH3 0 MIX LINL3 LINH3 0 AIN3 RINR2 RINH2 0 LODIF LINL2 LINH2 0 Note 41. PDN pin = “L” resets the registers to their default values. Note 42. Unused bits must contain a “0” value. MS0986-E-00 2008/07 - 63 - [AK4645A] ■ Register Definitions Addr 00H Register Name Power Management 1 Default D7 0 0 D6 PMVCM 0 D5 PMMIN 0 D4 0 0 D3 PMLO 0 D2 PMDAC 0 D1 0 0 D0 PMADL 0 PMADL: MIC-Amp Lch and ADC Lch Power Management 0: Power-down (default) 1: Power-up When the PMADL or PMADR bit is changed from “0” to “1”, the initialization cycle (1059/fs=24ms @44.1kHz) starts. After initializing, digital data of the ADC is output. PMDAC: DAC Power Management 0: Power-down (default) 1: Power-up PMLO: Stereo Line Out Power Management 0: Power-down (default) 1: Power-up PMMIN: MIN Input Power Management 0: Power-down (default) 1: Power-up PMMIN or PMAINL3 bit should be set to “1” for playback. PMVCM: VCOM Power Management 0: Power-down (default) 1: Power-up When any blocks are powered-up, the PMVCM bit must be set to “1”. PMVCM bit can be set to “0” only when all power management bits of 00H, 01H, 02H, 10H, 20H and MCKO bits are “0”. Each block can be powered-down respectively by writing “0” in each bit of this address. When the PDN pin is “L”, all blocks are powered-down regardless of setting of this address. In this case, register is initialized to the default value. When all power management bits are “0” in the 00H, 01H, 02H, 10H and 20H addresses and MCKO bit is “0”, all blocks are powered-down. The register values remain unchanged. Power supply current is 20μA(typ) in this case. For fully shut down (typ. 1μA), the PDN pin should be “L”. When neither ADC nor DAC are used, external clocks may not be present. When ADC or DAC is used, external clocks must always be present. MS0986-E-00 2008/07 - 64 - [AK4645A] Addr 01H Register Name Power Management 2 Default D7 HPZ 0 D6 HPMTN 0 D5 PMHPL 0 D4 PMHPR 0 D3 M/S 0 D2 0 0 D1 0 0 D5 0 0 D4 DACL 0 D3 0 0 D2 PMMP 0 D1 0 0 D0 0 0 M/S: Master / Slave Mode Select 0: Slave Mode (default) 1: Master Mode PMHPR: Headphone-Amp Rch Power Management 0: Power-down (default) 1: Power-up PMHPL: Headphone-Amp Lch Power Management 0: Power-down (default) 1: Power-up HPMTN: Headphone-Amp Mute Control 0: Mute (default) 1: Normal operation HPZ: Headphone-Amp Pull-down Control 0: Shorted to GND (default) 1: Pulled-down by 200kΩ (typ) Addr 02H Register Name Signal Select 1 Default D7 0 0 D6 0 0 D0 MGAIN0 1 MGAIN1-0: MIC-Amp Gain Control (Table 16) MGAIN1 bit is D5 bit of 03H. PMMP: MPWR pin Power Management 0: Power-down: Hi-Z (default) 1: Power-up DACL: Switch Control from DAC to Line Output 0: OFF (default) 1: ON When PMLO bit is “1”, DACL bit is enabled. When PMLO bit is “0”, the LOUT/ROUT pins go to AVSS. MS0986-E-00 2008/07 - 65 - [AK4645A] Addr 03H Register Name Signal Select 2 Default D7 LOVL 0 D6 LOPS 0 D5 MGAIN1 0 D4 0 0 D3 0 0 D2 MINL 0 D1 0 0 D0 0 0 MINL: Switch Control from MIN pin to Stereo Line Output 0: OFF (default) 1: ON When PMLO bit is “1”, MINL bit is enabled. When PMLO bit is “0”, the LOUT/ROUT pins go to AVSS. MGAIN1: MIC-Amp Gain Control (Table 16) LOPS: Stereo Line Output Power-Save Mode 0: Normal Operation (default) 1: Power-Save Mode LOVL: Stereo Line Output Gain Select (Table 44 and Table 46) 0: 0dB/+6dB (default) 1: +2dB/+8dB Addr 04H Register Name Mode Control 1 Default D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 BCKO 0 D2 0 0 D1 DIF1 1 D0 DIF0 0 D4 MSBS 0 D3 BCKP 0 D2 FS2 0 D1 FS1 0 D0 FS0 0 DIF1-0: Audio Interface Format (Table 10) Default: “10” (Left jutified) BCKO: BICK Output Frequency Select at Master Mode (Table 9) Addr 05H Register Name Mode Control 2 Default D7 0 0 D6 0 0 D5 FS3 0 FS3-0: MCKI Frequency Select (Table 5) FS3-0 bits select MCKI frequency. BCKP: BICK Polarity at DSP Mode (Table 11) “0”: SDTO is output by the rising edge (“↑”) of BICK and SDTI is latched by the falling edge (“↓”). (default) “1”: SDTO is output by the falling edge (“↓”) of BICK and SDTI is latched by the rising edge (“↑”). MSBS: LRCK Polarity at DSP Mode (Table 11) “0”: The rising edge (“↑”) of LRCK is half clock of BICK before the channel change. (default) “1”: The rising edge (“↑”) of LRCK is one clock of BICK before the channel change. MS0986-E-00 2008/07 - 66 - [AK4645A] Addr 06H Register Name Timer Select Default D7 DVTM 0 D6 WTM2 0 D5 ZTM1 0 D4 ZTM0 0 D3 WTM1 0 D2 WTM0 0 D1 RFST1 0 D0 RFST0 0 D2 LMAT0 0 D1 RGAIN0 0 D0 LMTH0 0 D2 REF2 0 D1 REF1 0 D0 REF0 1 RFST1-0: ALC First recovery Speed (Table 27) Default: “00”(4times) WTM2-0: ALC Recovery Waiting Period (Table 24) Default: “000” (128/fs) ZTM1-0: ALC Limiter/Recovery Operation Zero Crossing Timeout Period (Table 23) Default: “00” (128/fs) DVTM: Digital Volume Transition Time Setting (Table 33) 0: 1061/fs (default) 1: 256/fs This is the transition time between DVL/R7-0 bits = 00H and FFH. Addr 07H Register Name ALC Mode Control 1 Default D7 0 0 D6 0 0 D5 ALC 0 D4 ZELMN 0 D3 LMAT1 0 LMTH1-0: ALC Limiter Detection Level / Recovery Counter Reset Level (Table 21) Default: “00” LMTH1 bit is D6 bit of 0BH. RGAIN1-0: ALC Recovery GAIN Step (Table 25) Default: “00” RGAIN1 bit is D7 bit of 0BH. LMAT1-0: ALC Limiter ATT Step (Table 22) Default: “00” ZELMN: Zero Crossing Detection Enable at ALC Limiter Operation 0: Enable (default) 1: Disable ALC: ALC Enable 0: ALC Disable (default) 1: ALC Enable Addr 08H Register Name ALC Mode Control 2 Default D7 REF7 1 D6 REF6 1 D5 REF5 1 D4 REF4 0 D3 REF3 0 REF7-0: Reference Value at ALC Recovery Operation. 0.375dB step, 242 Level (Table 26) Default: “E1H” (+30.0dB) MS0986-E-00 2008/07 - 67 - [AK4645A] Addr 09H 0CH Register Name Lch Input Volume Control Rch Input Volume Control Default D7 IVL7 IVR7 1 D6 IVL6 IVR6 1 D5 IVL5 IVR5 1 D4 IVL4 IVR4 0 D3 IVL3 IVR3 0 D2 IVL2 IVR2 0 D1 IVL1 IVR1 0 D0 IVL0 IVR0 1 IVL7-0, IVR7-0: Input Digital Volume; 0.375dB step, 242 Level (Table 29) Default: “E1H” (+30.0dB) Addr 0AH 0DH Register Name Lch Digital Volume Control Rch Digital Volume Control Default D7 DVL7 DVR7 0 D6 DVL6 DVR6 0 D5 DVL5 DVR5 0 D4 DVL4 DVR4 1 D3 DVL3 DVR3 1 D2 DVL2 DVR2 0 D1 DVL1 DVR1 0 D0 DVL0 DVR0 0 D5 0 0 D4 0 0 D3 0 0 D2 0 0 D1 VBAT 0 D0 0 0 D2 BST0 0 D1 DEM1 0 D0 DEM0 1 DVL7-0, DVR7-0: Output Digital Volume (Table 32) Default: “18H” (0dB) Addr 0BH Register Name ALC Mode Control 3 Default D7 RGAIN1 0 D6 LMTH1 0 VBAT: HP-Amp Common Voltage (Table 49) 0: 0.5 x HVDD (default) 1: 0.64 x AVDD LMTH1: ALC Limiter Detection Level / Recovery Counter Reset Level (Table 21) RGAIN1: ALC Recovery GAIN Step (Table 25) Addr 0EH Register Name Mode Control 3 Default D7 0 0 D6 LOOP 0 D5 SMUTE 0 D4 DVOLC 1 D3 BST1 0 DEM1-0: De-emphasis Frequency Select (Table 30) Default: “01” (OFF) BST1-0: Bass Boost Function Select (Table 31) Default: “00” (OFF) DVOLC: Output Digital Volume Control Mode Select 0: Independent 1: Dependent (default) When DVOLC bit = “1”, DVL7-0 bits control both Lch and Rch volume level, while register values of DVL7-0 bits are not written to DVR7-0 bits. When DVOLC bit = “0”, DVL7-0 bits control Lch level and DVR7-0 bits control Rch level, respectively. SMUTE: Soft Mute Control 0: Normal Operation (default) 1: DAC outputs soft-muted LOOP: Digital Loopback Mode 0: SDTI → DAC (default) 1: SDTO → DAC MS0986-E-00 2008/07 - 68 - [AK4645A] Addr 0FH Register Name Mode Control 4 Default D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 IVOLC 1 D2 HPM 0 D1 MINH 0 D0 DACH 0 DACH: Switch Control from DAC to Headphone-Amp 0: OFF (default) 1: ON MINH: Switch Control from MIN pin to Headphone-Amp 0: OFF (default) 1: ON HPM: Headphone-Amp Mono Output Select 0: Stereo (default) 1: Mono When the HPM bit = “1”, DAC output signal is output to Lch and Rch of the Headphone-Amp as (L+R)/2. IVOLC: Input Digital Volume Control Mode Select 0: Independent 1: Dependent (default) When IVOLC bit = “1”, IVL7-0 bits control both Lch and Rch volume level, while register values of IVL7-0 bits are not written to IVR7-0 bits. When IVOLC bit = “0”, IVL7-0 bits control Lch level and IVR7-0 bits control Rch level, respectively. Addr 10H Register Name Power Management 3 Default D7 INR1 0 D6 INL1 0 D5 HPG 0 D4 MDIF2 0 D3 MDIF1 0 D2 INR0 0 D1 INL0 0 D0 PMADR 0 PMADR: MIC-Amp Lch and ADC Rch Power Management 0: Power-down (default) 1: Power-up INL1-0: ADC Lch Input Source Select (Table 13) Default: 00 (LIN1 pin) INR1-0: ADC Rch Input Source Select (Table 13) Default: 00 (RIN1 pin) MDIF1: Single-ended / Full-differential Input Select 1 0: Single-ended input (LIN1/RIN1 pins: Default) 1: Full-differential input (IN1+/IN1− pins) MDIF1 bit selects the input type of pins #32 and #31. MDIF2: Single-ended / Full-differential Input Select 2 0: Single-ended input (LIN2/RIN2 pins: Default) 1: Full-differential input (IN2+/IN2− pins) MDIF2 bit selects the input type of pins #30 and #29. HPG: Headphone-Amp Gain Select (Table 47) 0: 0dB (default) 1: +3.6dB MS0986-E-00 2008/07 - 69 - [AK4645A] Addr 11H Register Name Digital Filter Select Default D7 GN1 0 D6 GN0 0 D5 0 0 D4 FIL1 0 D3 EQ 0 D2 FIL3 0 D1 0 0 D0 0 0 GN1-0: Gain Select at GAIN block (Table 19) Default: “00” FIL3: FIL3 (Stereo Separation Emphasis Filter) Coefficient Setting Enable 0: Disable (default) 1: Enable When FIL3 bit is “1”, the settings of F3A13-0 and F3B13-0 bits are enabled. When FIL3 bit is “0”, FIL3 block is OFF (MUTE). EQ: EQ (Gain Compensation Filter) Coefficient Setting Enable 0: Disable (default) 1: Enable When EQ bit is “1”, the settings of EQA15-0, EQB13-0 and EQC15-0 bits are enabled. When EQ bit is “0”, EQ block is through (0dB). FIL1: FIL1 (Wind-noise Reduction Filter) Coefficient Setting Enable 0: Disable (default) 1: Enable When FIL1 bit is “1”, the settings of F1A13-0 and F1B13-0 bits are enabled. When FIL1 bit is “0”, FIL1 block is through (0dB). Addr 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH Register Name FIL3 Co-efficient 0 FIL3 Co-efficient 1 FIL3 Co-efficient 2 FIL3 Co-efficient 3 EQ Co-efficient 0 EQ Co-efficient 1 EQ Co-efficient 2 EQ Co-efficient 3 EQ Co-efficient 4 EQ Co-efficient 5 FIL1 Co-efficient 0 FIL1 Co-efficient 1 FIL1 Co-efficient 2 FIL1 Co-efficient 3 Default D7 F3A7 F3AS F3B7 0 EQA7 EQA15 EQB7 0 EQC7 EQC15 F1A7 F1AS F1B7 0 0 D6 F3A6 0 F3B6 0 EQA6 EQA14 EQB6 0 EQC6 EQC14 F1A6 0 F1B6 0 0 D5 F3A5 F3A13 F3B5 F3B13 EQA5 EQA13 EQB5 EQB13 EQC5 EQC13 F1A5 F1A13 F1B5 F1B13 0 D4 F3A4 F3A12 F3B4 F3B12 EQA4 EQA12 EQB4 EQB12 EQC4 EQC12 F1A4 F1A12 F1B4 F1B12 0 D3 F3A3 F3A11 F3B3 F3B11 EQA3 EQA11 EQB3 EQB11 EQC3 EQC11 F1A3 F1A11 F1B3 F1B11 0 D2 F3A2 F3A10 F3B2 F3B10 EQA2 EQA10 EQB2 EQB10 EQC2 EQC10 F1A2 F1A10 F1B2 F1B10 0 D1 F3A1 F3A9 F3B1 F3B9 EQA1 EQA9 EQB1 EQB9 EQC1 EQC9 F1A1 F1A9 F1B1 F1B9 0 D0 F3A0 F3A8 F3B0 F3B8 EQA0 EQA8 EQB0 EQB8 EQC0 EQC8 F1A0 F1A8 F1B0 F1B8 0 F3A13-0, F3B13-0: FIL3 (Stereo Separation Emphasis Filter) Coefficient (14bit x 2) Default: “0000H” F3AS: FIL3 (Stereo Separation Emphasis Filter) Select 0: HPF (default) 1: LPF EQA15-0, EQB13-0, EQC15-C0: EQ (Gain Compensation Filter) Coefficient (14bit x 2 + 16bit x 1) Default: “0000H” F1A13-0, F1B13-B0: FIL1 (Wind-noise Reduction Filter) Coefficient (14bit x 2) Default: “0000H” F1AS: FIL1 (Wind-noise Reduction Filter) Select 0: HPF (default) 1: LPF MS0986-E-00 2008/07 - 70 - [AK4645A] Addr 20H Register Name Power Management 4 Default D7 D6 D5 D4 D3 D2 D1 D0 PMAINR4 PMAINL4 PMAINR3 PMAINL3 PMAINR2 PMAINL2 PMMICR PMMICL 0 0 0 0 0 0 0 0 PMMICL: MIC-Amp Lch Power Management 0: Power down (default) 1: Power up PMMICR: MIC-Amp Rch Power Management 0: Power down (default) 1: Power up PMAINL2: LIN2 Mixing Circuit Power Management 0: Power down (default) 1: Power up PMAINR2: RIN2 Mixing Circuit Power Management 0: Power down (default) 1: Power up PMAINL3: LIN3 Mixing Circuit Power Management 0: Power down (default) 1: Power up PMAINR3: RIN3 Mixing Circuit Power Management 0: Power down (default) 1: Power up PMAINL4: LIN4 Mixing Circuit Power Management 0: Power down (default) 1: Power up PMAINR4: RIN4 Mixing Circuit Power Management 0: Power down (default) 1: Power up MS0986-E-00 2008/07 - 71 - [AK4645A] Addr 21H Register Name Mode Control 5 Default D7 0 0 D6 0 0 D5 MICR3 0 D4 MICL3 0 D3 L4DIF 0 D2 MIX 0 D1 AIN3 0 D0 LODIF 0 LODIF: Lineout Select 0: Single-ended Stereo Line Output (LOUT/ROUT pins) (default) 1: Full-differential Mono Line Output (LOP/LON pins) AIN3: Analog Mixing Select 0: Mono Input (MIN pin) (default) 1: Stereo Input (LIN3/RIN3 pins) MIX: Mono Recording 0: Stereo (default) 1: Mono: (L+R)/2 L4DIF: Line Input Type Select 0: Stereo Single-ended Input: LIN4/RIN4 pins (default) 1: Mono Full-differential Input: IN4+/− pins MICL3: Switch Control from MIC-Amp Lch to Analog Output 0: LIN3 input signal is selected. (default) 1: MIC-Amp Lch output signal is selected. MICR3: Switch Control from MIC-Amp Rch to Analog Output 0: RIN3 input signal is selected. (default) 1: MIC-Amp Rch output signal is selected. MS0986-E-00 2008/07 - 72 - [AK4645A] Addr 22H Register Name Lineout Mixing Select Default D7 LOM 0 D6 LOM3 0 D5 RINR4 0 D4 LINL4 0 D3 RINR3 0 D2 LINL3 0 D1 RINR2 0 D0 LINL2 0 LINL2: Switch Control from LIN2 pin to Stereo Line Output (without MIC-Amp) 0: OFF (default) 1: ON RINR2: Switch Control from RIN2 pin to Stereo Line Output (without MIC-Amp) 0: OFF (default) 1: ON LINL3: Switch Control from LIN3 pin (or MIC-Amp Lch) to Stereo Line Output 0: OFF (default) 1: ON RINR3: Switch Control from RIN3 pin (or MIC-Amp Lch) to Stereo Line Output 0: OFF (default) 1: ON LINL4: Switch Control from LIN4 pin to Stereo Line Output (without MIC-Amp) 0: OFF (default) 1: ON RINR4: Switch Control from RIN4 pin to Stereo Line Output (without MIC-Amp) 0: OFF (default) 1: ON LOM3: Mono Mixing from MIC-Amp (or LIN3/RIN3) to Stereo Line Output 0: Stereo Mixing (default) 1: Mono Mixing LOM: Mono Mixing from DAC to Stereo Line Output 0: Stereo Mixing (default) 1: Mono Mixing MS0986-E-00 2008/07 - 73 - [AK4645A] Addr 23H Register Name HP Mixing Select Default D7 0 0 D6 HPM3 0 D5 RINH4 0 D4 LINH4 0 D3 RINH3 0 D2 LINH3 0 D1 RINH2 0 D0 LINH2 0 LINH2: Switch Control from LIN2 pin to Headphone Output (without MIC-Amp) 0: OFF (default) 1: ON RINH2: Switch Control from RIN2 pin to Headphone Output (without MIC-Amp) 0: OFF (default) 1: ON LINH3: Switch Control from LIN3 pin (or MIC-Amp Lch) to Headphone Output 0: OFF (default) 1: ON RINH3: Switch Control from RIN3 pin (or MIC-Amp Lch) to Headphone Output 0: OFF (default) 1: ON LINH4: Switch Control from LIN4 pin to Headphone Output (without MIC-Amp) 0: OFF (default) 1: ON RINH4: Switch Control from RIN4 pin to Headphone Output (without MIC-Amp) 0: OFF (default) 1: ON HPM3: Mono Mixing from MIC-Amp (or LIN3/RIN3) to Headphone Output 0: Stereo Mixing (default) 1: Mono Mixing MS0986-E-00 2008/07 - 74 - [AK4645A] SYSTEM DESIGN Figure 67 and Figure 68 shows the system connection diagram for the AK4645A. An evaluation board [AKD4645] is available which demonstrates the optimum layout, power supply arrangements and measurement results. Headphone 47u 10 10 0.22u 6.8 47u 10u 6.8 Power Supply 2.6 ∼ 3.6V Power Supply 1.6 ∼ 3.6V 10 0.22u 17 0.1u MCKI TESTO 18 19 HVSS 20 HVDD 0.1u 21 22 HPL Line In HPR RIN4 External SPK-Amp MUTET 23 24 1u 25 LIN4 TVDD 16 26 ROUT DVDD 15 27 LOUT BICK 14 Speaker 0.1u Mono In External MIC DSP 28 MIN AK4645A LRCK 13 29 RIN2 Top View SDTO 12 30 LIN2 SDTI 11 31 LIN1 CDTI 10 32 RIN1 CCLK 9 AVSS AVDD RIN3 I2C PDN CSN 3 4 5 6 7 8 μP 2.2u 0.1u VCOM 2 MPWR 1 0.1u 2.2k 2.2k 2.2k 2.2k Internal MIC Analog Ground Digital Ground Notes: - AVSS and HVSS of the AK4645A must be distributed separately from the ground of external controllers. - All digital input pins must not be left floating. - When the AK4645A is used at master mode, LRCK and BICK pins are floating before M/S bit is changed to “1”. Therefore, 100kΩ around pull-up resistor must be connected to LRCK and BICK pins of the AK4645A. - 0.1μF ceramic capacitor must be attached to each supply pins. The type of other capacitors is not critical. - When DVDD is supplied from AVDD via 10Ω series resistor, the capacitor larger than 0.1μF must not be connected between DVDD and the ground. Figure 67. Typical Connection Diagram (AIN3 bit = “0”, MIC Input) MS0986-E-00 2008/07 - 75 - [AK4645A] Headphone 47u 10 10 0.22u 6.8 47u 10u 6.8 Power Supply 2.6 ∼ 3.6V Power Supply 1.6 ∼ 3.6V 10 0.22u 17 MCKI TESTO 18 19 20 HVDD HVSS 21 HPR 22 16 26 ROUT DVDD 15 27 LOUT BICK 14 0.1u DSP 31 LIN1 CDTI 10 32 RIN1 CCLK 9 μP 2.2u 0.1u 1 0.1u 8 11 CSN SDTI PDN 30 LIN2 7 12 I2C SDTO 6 Top View RIN3 29 RIN2 5 13 AVDD LRCK 4 AK4645A AVSS 28 LIN3 VCOM 1u TVDD 3 200 0.1u 25 LIN4 MPWR Line In 1u 2 Line Out 200 MUTET 23 Line In HPL RIN4 24 20k 20k 0.1u 1u Analog Ground Digital Ground Notes: - AVSS and HVSS of the AK4645A msut be distributed separately from the ground of external controllers. - All digital input pins must not be left floating. - When the AK4645A is used at master mode, LRCK and BICK pins are floating before M/S bit is changed to “1”. Therefore, 100kΩ around pull-up resistor must be connected to LRCK and BICK pins of the AK4645A. - 0.1μF ceramic capacitor should be attached to each supply pins. The type of other capacitors is not critical. - When DVDD is supplied from AVDD via 10Ω series resistor, the capacitor larger than 0.1μF must not be connected between DVDD and the ground. Figure 68. Typical Connection Diagram (AIN3 bit = “1”, Line Input) MS0986-E-00 2008/07 - 76 - [AK4645A] 1. Grounding and Power Supply Decoupling The AK4645A requires careful attention to power supply and grounding arrangements. AVDD, DVDD, TVDD and HVDD are usually supplied from the system’s analog supply. If AVDD, DVDD, TVDD and HVDD are supplied separately, the power-up sequence is not critical. The PDN pin must be held to “L” upon power-up. The PDN pin must be set to “H” after all power supplies are powered-up. In case that pop noise have to be avoided at line output and headphone output, the AK4645A should be operated by the following recommended power-up/down sequence. 1) Power-up - The PDN pin must be held to “L” upon power-up. The AK4645A must be reset by bringing PDN pin “L” for 150ns or more. - In case that the power supplies are separated in two or more groups, the power supply including TVDD should be powered ON at first. Regarding the relationship between DVDD and HVDD, the power supply including DVDD should be powered ON prior to the power supply including HVDD. 2) Power-down - Each power supplies must be powered OFF after the PDN pin is set to “L”. - In case that the power supplies are separated in two or more groups, the power supply including TVDD should be powered OFF at last. Regarding the relationship between DVDD and HVDD, the power supply including HVDD should be powered OFF prior to the power supply including DVDD. AVSS and HVSS of the AK4645A must be connected to the analog ground plane. System analog ground and digital ground must be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK4645A as possible, with the small value ceramic capacitor being the nearest. 2. Voltage Reference VCOM is a signal ground of this chip. A 2.2μF electrolytic capacitor in parallel with a 0.1μF ceramic capacitor attached to the VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from the VCOM pin. All signals, especially clocks, should be kept away from the VCOM pin in order to avoid unwanted coupling into the AK4645A. 3. Analog Inputs The Mic, Line and MIN inputs are single-ended. The input signal range scales with nominally at 0.06 x AVDD Vpp(typ) @MGAIN1-0 bits = “01”, 0.03 x AVDD Vpp(typ) @MGAIN1-0 bits = “10”, 0.015 x AVDD Vpp(typ) @MGAIN1-0 bits = “11” or 0.6 x AVDD Vpp(typ) @MGAIN1-0 bits = “00” for the Mic/Line input and 0.6 x AVDD Vpp (typ) for the MIN input, centered around the internal common voltage (0.45 x AVDD). Usually the input signal is AC coupled using a capacitor. The cut-off frequency is fc = (1/2πRC). The AK4645A can accept input voltages from AVSS to AVDD. 4. Analog Outputs The input data format for the DAC is 2’s complement. The output voltage is a positive full scale for 7FFFH(@16bit) and a negative full scale for 8000H(@16bit). The ideal output is VCOM voltage for 0000H(@16bit). Stereo Line Output is centered at 0.45 x AVDD. The Headphone-Amp output is centered at HVDD/2. MS0986-E-00 2008/07 - 77 - [AK4645A] CONTROL SEQUENCE ■ Clock Set up When ADC or DAC is powered-up, the clocks must be supplied. 1. 1. EXT Slave Mode Example: Audio I/F Format: MSB justified (ADC and DAC) Input MCKI frequency: 256fs Sampling Frequency: 44.1kHz Power Supply (1) Power Supply & PDN pin = “L” Æ “H” (1) PDN pin (2) (2) Addr:04H, Data:02H Addr:05H, Data:00H (3) PMVCM bit (Addr:00H, D6) (4) MCKI pin Input (3) Addr:00H, Data:40H (4) LRCK pin BICK pin Input MCKI, BICK and LRCK input Figure 69. Clock Set Up Sequence (4) <Example> (1) After Power Up, PDN pin = “L” Æ “H”. “L” time of 150ns or more is needed to reset the AK4645A. The AK4645A should be operated by the recommended power-up/down sequence shown in “System Design (Grounding and Power Supply Decoupling)” to avoid pop noise at line output and headphone output. (2) DIF1-0 and FS1-0 bits must be set during this period. (3) Power Up VCOM: PMVCM bit = “0” Æ “1” VCOM should first be powered up before the other block operates. (4) Normal operation starts after the MCKI, LRCK and BICK are supplied. MS0986-E-00 2008/07 - 78 - [AK4645A] 2. EXT Master Mode Example: Audio I/F Format: MSB justified (ADC and DAC) Input MCKI frequency: 256fs Sampling Frequency: 44.1kHz (1) Power Supply & PDN pin = “L” Æ “H” Power Supply (1) PDN pin (2) MCKI input (4) PMVCM bit (Addr:00H, D6) (3) Addr:04H, Data:02H Addr:05H, Data:00H Addr:01H, Data:08H (2) MCKI pin Input (3) M/S bit BICK and LRCK output (Addr:01H, D3) LRCK pin BICK pin Output (4) Addr:00H, Data:40H Figure 70. Clock Set Up Sequence (5) <Example> (1) After Power Up, PDN pin = “L” Æ “H”. “L” time of 150ns or more is needed to reset the AK4645A. The AK4645A must be operated by the recommended power-up/down sequence shown in “System Design (Grounding and Power Supply Decoupling)” to avoid the pop noise at line output and headphone output. (2) MCKI should be input. (3) After DIF1-0 and FS1-0 bits are set, M/S bit must be set to “1”. Then LRCK and BICK are output. (4) Power Up VCOM: PMVCM bit = “0” Æ “1” VCOM should first be powered up before the other block operates. MS0986-E-00 2008/07 - 79 - [AK4645A] ■ MIC Input Recording (Stereo) Example: FS3-0 bits (Addr:05H, D5&D2-0) 0,000 Audio I/F Format:MSB justified (ADC & DAC) Sampling Frequency:44.1kHz Pre MIC AMP:+20dB MIC Power On ALC setting:Refer to Table 34 ALC bit=“1” 0,010 (1) MIC Control (Addr:02H, D2-0) ALC Control 1 (Addr:06H) ALC Control 2 (Addr:08H) (1) Addr:05H, Data:27H 001 101 (2) Addr:02H, Data:05H (2) 00H 3CH (3) Addr:06H, Data:3CH E1H (4) Addr:08H, Data:E1H (3) E1H (4) (5) Addr:0BH, Data:00H ALC Control 3 (Addr:0BH) 00H 00H (6) Addr:07H, Data:21H (5) ALC Control 4 (Addr:07H) 07H 21H 01H (6) ALC State (9) ALC Disable ALC Enable (7) Addr:00H, Data:41H Addr:10H, Data:01H ALC Disable Recording PMADL/R bits (Addr:00H&10H, D0) 1059 / fs (8) (7) ADC Internal State Power Down (8) Addr:00H, Data:40H Addr:10H, Data:00H Initialize Normal State Power Down (9) Addr:07H, Data:01H Figure 71. MIC Input Recording Sequence <Example> This sequence is an example of ALC setting at fs=44.1kHz. If the parameter of the ALC is changed, please refer to “Figure 29. Registers set-up sequence at ALC operation” At first, clocks must be supplied according to “Clock Set Up” sequence. (1) Set up a sampling frequency (FS3-0 bit). (2) Set up MIC input (Addr: 02H) (3) Set up Timer Select for ALC (Addr: 06H) (4) Set up REF value for ALC (Addr: 08H) (5) Set up LMTH1 and RGAIN1 bits (Addr: 0BH) (6) Set up LMTH0, RGAIN0, LMAT1-0 and ALC bits (Addr: 07H) (7) Power Up MIC and ADC: PMADL = PMADR bits = “0” → “1” The initialization cycle time of ADC is 1059/fs=24ms@fs=44.1kHz. After the ALC bit is set to “1” and MIC&ADC block is powered-up, the ALC operation starts from IVOL default value (+30dB). The time of offset voltage going to “0” after the ADC initialization cycle depends on both the time of analog input pin going to the common voltage and the time constant of the offset cancel digital HPF. This time can be shorter by using the following sequence: At first, PMVCM and PMMP bits must set to “1”. Then, the ADC should be powered-up. The wait time to power-up the ADC should be longer than 4 times of the time constant that is determined by the AC coupling capacitor at analog input pin and the internal input resistance 60k(typ). (8) Power Down MIC and ADC: PMADL = PMADR bits = “1” → “0” When the registers for the ALC operation are not changed, ALC bit may be keeping “1”. The ALC operation is disabled because the MIC&ADC block is powered-down. If the registers for the ALC operation are also changed when the sampling frequency is changed, it should be done after the AK4645A goes to the manual mode (ALC bit = “0”) or MIC&ADC block is powered-down (PMADL=PMADR bits = “0”). IVOL gain is not reset when PMADL=PMADR bits = “0”, and then IVOL operation starts from the setting value when PMADL or PMADR bit is changed to “1”. (9) ALC Disable: ALC bit = “1” → “0” MS0986-E-00 2008/07 - 80 - [AK4645A] ■ Headphone-amp Output E x a m p le : FS3-0 bits (Addr:05H, D5&D2-0) 0,000 S a m p lin g F r e q u e n c y : 4 4 . 1 k H z D V O L C b it = “ 1 ” ( d e fa u lt ) D ig it a l V o lu m e L e v e l: − 8 d B B a s s B o o s t L e v e l: M id d le D e -e m p h a s e s re s p o n s e : O F F S o f t M u t e T im e : 2 5 6 /f s 0,010 (1) ( 1 ) A d d r : 0 5 H , D a ta : 2 7 H DACH bit (2) (Addr:0FH, D0) (13) ( 2 ) A d d r : 0 F H , D a ta 0 9 H BST1-0 bits (Addr:0EH, D3-2) IVL/R7-0 bits (Addr:09H&0CH, D7-0) 00 10 00 (3) E1H (4 ) A d d r:0 9 H & 0 C H , D a ta 9 1 H 91H (4) DVL/R7-0 bits (Addr:0AH&0DH, D7-0) (3 ) A d d r:0 E H , D a ta 1 9 H (12) ( 5 ) A d d r : 0 A H & 0 D H , D a ta 2 8 H 18H 28H ( 6 ) A d d r : 0 0 H , D a ta 6 4 H (5) PMDAC bit ( 7 ) A d d r : 0 1 H , D a ta 3 9 H (Addr:00H, D2) (6) (11) PMMIN bit ( 8 ) A d d r : 0 1 H , D a ta 7 9 H P la y b a c k (Addr:00H, D5) ( 9 ) A d d r : 0 1 H , D a ta 3 9 H PMHPL/R bits (7) (10) (Addr:01H, D5-4) HPMTN bit ( 1 0 ) A d d r :0 1 H , D a t a 0 9 H (8) (9) (Addr:01H, D6) ( 1 1 ) A d d r :0 0 H , D a t a 4 0 H ( 1 2 ) A d d r :0 E H , D a t a 0 0 H HPL/R pins Normal Output ( 1 3 ) A d d r :0 F H , D a t a 0 8 H Figure 72. Headphone-Amp Output Sequence <Example> At first, clocks must be supplied according to “Clock Set Up” sequence. (1) Set up a sampling frequency (FS3-0 bits). (2) Set up the path of “DAC → HP-Amp”: DACH bit = “0” → “1” (3) Set up the low frequency boost level (BST1-0 bits) (4) Set up the input digital volume (Addr: 09H and 0CH) When PMADL = PMADR bits = “0”, IVL7-0 and IVR7-0 bits must be set to “91H”(0dB). (5) Set up the output digital volume (Addr: 0AH and 0DH) When DVOLC bit is “1” (default), DVL7-0 bits set the volume of both channels. After DAC is powered-up, the digital volume changes from default value (0dB) to the register setting value by the soft transition. (6) Power up DAC and MIN-Amp: PMDAC = PMMIN bits = “0” → “1” The DAC enters an initialization cycle that starts when the PMDAC bit is changed from “0” to “1” at PMADL and PMADR bits are “0”. The initialization cycle time is 1059/fs=24ms@fs=44.1kHz. During the initialization cycle, the DAC input digital data of both channels are internally forced to a 2's compliment, “0”. The DAC output reflects the digital input data after the initialization cycle is complete. When PMADL or PMADR bit is “1”, the DAC does not require an initialization cycle. When ALC bit is “1”, ALC is disable (ALC gain is set by IVL/R7-0 bits) during an intialization cycle (1059/fs=24ms@fs=44.1kHz). After the initialization cycle, ALC operation starts from the gain set by IVL/R7-0 bits. (7) Power up headphone-amp: PMHPL = PMHPR bits = “0” → “1” Output voltage of headphone-amp is still HVSS. (8) Rise up the common voltage of headphone-amp: HPMTN bit = “0” → “1” The rise time depends on HVDD and the capacitor value connected with the MUTET pin. When HVDD=3.3V and the capacitor value is 1.0μF, the time constant is τr = 100ms(typ), 250ms(max). (9) Fall down the common voltage of headphone-amp: HPMTN bit = “1” → “0” The fall time depends on HVDD and the capacitor value connected with the MUTET pin. When HVDD=3.3V and the capacitor value is 1.0μF, the time constant is τ f = 100ms(typ), 250ms(max). If the power supply is powered-off or headphone-Amp is powered-down before the common voltage goes to GND, pop noise occurs. It takes twice of τf that the common voltage goes to GND. (10) Power down headphone-amp: PMHPL = PMHPR bits = “1” → “0” (11) Power down DAC and MIN-Amp: PMDAC = PMMIN bits = “1” → “0” (12) Off the bass boost: BST1-0 bits = “00” (13) Disable the path of “DAC → HP-Amp”: DACH bit = “1” → “0” MS0986-E-00 2008/07 - 81 - [AK4645A] ■ Stereo Line Output Example: FS3-0 bits (Addr:05H, D5&D2-0) 0,000 Audio I/F Format :MSB justified (ADC & DAC) Sampling Frequency: 44.1kHz Digital Volume: −8dB LOVL=MINL bits = “0” 0,010 (1) (1) Addr:05H, Data:27H (10) DACL bit (2) (2) Addr:02H, Data:10H (Addr:02H, D4) IVL/R7-0 bits (Addr:09H&0CH, D7-0) E1H (3) Addr:09H&0CH, Data:91H 91H (3) DVL/R7-0 bits (Addr:0AH&0DH, D7-0) (4) Addr:0AH&0DH, Data:28H 18H 28H (5) Addr:03H, Data:40H (4) LOPS bit (6) Addr:00H, Data:6CH (Addr:03H, D6) (5) (7) (8) (11) PMDAC bit (Addr:00H, D2) Playback PMMIN bit (8) Addr:03H, Data:40H (Addr:00H, D5) (6) (9) (9) Addr:00H, Data:40H PMLO bit (Addr:00H, D3) LOUT pin ROUT pin (7) Addr:03H, Data:00H >300 ms (10) Addr:02H, Data:00H >300 ms Normal Output (11) Addr:03H, Data:00H Figure 73. Stereo Lineout Sequence <Example> At first, clocks must be supplied according to “Clock Set Up” sequence. (1) Set up the sampling frequency (FS3-0 bits). (2) Set up the path of “DAC Æ Stereo Line Amp”: DACL bit = “0” Æ “1” (3) Set up the input digital volume (Addr: 09H and 0CH) When PMADL = PMADR bits = “0”, IVL7-0 and IVR7-0 bits must be set to “91H”(0dB). (4) Set up the output digital volume (Addr: 0AH and 0DH) When DVOLC bit is “1” (default), DVL7-0 bits set the volume of both channels. After DAC is powered-up, the digital volume changes from default value (0dB) to the register setting value by the soft transition. (5) Enter power-save mode of Stereo Line Amp: LOPS bit = “0” Æ “1” (6) Power-up DAC, MIN-Amp and Stereo Line-Amp: PMDAC = PMMIN = PMLO bits = “0” → “1” The DAC enters an initialization cycle that starts when the PMDAC bit is changed from “0” to “1” at PMADL and PMADR bits are “0”. The initialization cycle time is 1059/fs=24ms@fs=44.1kHz. During the initialization cycle, the DAC input digital data of both channels are internally forced to a 2's compliment, “0”. The DAC output reflects the digital input data after the initialization cycle is completed. When PMADL or PMADR bit is “1”, the DAC does not require an initialization cycle. When ALC bit is “1”, ALC is disable (ALC gain is set by IVL/R7-0 bits) during an intialization cycle (1059/fs=24ms@fs=44.1kHz). After the initialization cycle, ALC operation starts from the gain set by IVL/R7-0 bits. LOUT and ROUT pins rise up to VCOM voltage after PMLO bit is changed to “1”. Rise time is 300ms(max) at C=1μF and AVDD=3.3V. (7) Exit power-save mode of Stereo Line-Amp: LOPS bit = “1” Æ “0” LOPS bit should be set to “0” after LOUT and ROUT pins rise up. Stereo Line-Amp goes to normal operation by setting LOPS bit to “0”. (8) Enter power-save mode of Stereo Line-Amp: LOPS bit: “0” Æ “1” (9) Power-down DAC, MIN-Amp and Stereo Line-Amp: PMDAC = PMMIN = PMLO bits = “1” → “0” LOUT and ROUT pins fall down to AVSS. Fall time is 300ms(max) at C=1μF and AVDD=3.3V. (10) Disable the path of “DAC Æ Stereo Line-Amp”: DACL bit = “1” Æ “0” (11) Exit power-save mode of Stereo Line-Amp: LOPS bit = “1” Æ “0” LOPS bit should be set to “0” after LOUT and ROUT pins fall down. MS0986-E-00 2008/07 - 82 - [AK4645A] ■ Stop of Clock Master clock can be stopped when ADC and DAC are not in operation. 1. EXT Slave Mode (1) External MCKI Input Example (1) External BICK Input External LRCK Input Audio I/F Format: MSB justified (ADC & DAC) Input MCKI frequency: 1024fs Sampling Frequency: 44.1kHz (1) (1) Stop the external clocks Figure 74. Clock Stopping Sequence (4) <Example> (1) Stop the external MCKI, BICK and LRCK clocks. 2. EXT Master Mode (1) External MCKI Input Example BICK Output "H" or "L" LRCK Output "H" or "L" Audio I/F Format: MSB justified (ADC & DAC) Input MCKI frequency: 1024fs Sampling Frequency: 44.1kHz (1) Stop the external MCKI Figure 75. Clock Stopping Sequence (5) <Example> (1) Stop MCKI clock. BICK and LRCK are fixed to “H” or “L”. ■ Power down Power supply current can be shut down (typ. 20μA) by stopping clocks and setting PMVCM bit = “0” after all blocks except for VCOM are powered-down. Power supply current can also be shut down (typ. 1μA) by stopping clocks and setting the PDN pin = “L”. When the PDN pin = “L”, the registers are initialized. MS0986-E-00 2008/07 - 83 - [AK4645A] PACKAGE 32pin QFN (Unit: mm) 4.0 ± 0.1 2.4 ± 0.1 17 24 0.40 ± 0.10 25 2.4 ± 0.1 4.0 ± 0.1 16 A Exposed Pad 32 9 0.45 ± 0.10 8 1 0.22 ± 0.05 B 0.18 ± 0.05 0.05 M C0.3 PIN #1 ID 0.65 MAX 0.4 0.00 MIN 0.05 MAX 0.08 Note) The exposed pad on the bottom surface of the package must be open or connected to the ground. ■ Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder (Pb free) plate MS0986-E-00 2008/07 - 84 - [AK4645A] MARKING 4645A XXXX 1 XXXX: Date code (4 digit) Pin #1 indication REVISION HISTORY Date (YY/MM/DD) 08/07/31 Revision 00 Reason First Edition Page Contents IMPORTANT NOTICE z These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status of the products. z AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. z Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKEMD. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any and all claims arising from the use of said product in the absence of such notification. MS0986-E-00 2008/07 - 85 -