MAXIM MAX499

19-1143; Rev 0; 10/96
KIT
ATION
EVALU
LE
B
A
IL
A
AV
Quad/Triple, SPDT, RGB Switches
with 250MHz Video Buffer Amplifiers
________________________Applications
____________________________Features
♦ High Speed:
250MHz Small-Signal -3dB Bandwidth
135MHz Full-Power -3dB Bandwidth
♦ 70MHz 0.1dB Gain Flatness
♦ 1250V/µs Slew Rate
♦ 12ns to 0.1% Settling Time
♦ 0.03°/0.06% Differential Phase/Gain Error
♦ 2pF Input Capacitance
♦ 3ns Channel-Switching Time
♦ 120mVp-p Channel-Switching Transient
♦ Three-State Output Allows Large Switch Arrays
♦ Directly Drives 50Ω or 75Ω Back-Terminated
Cables
______________Ordering Information
PART
TEMP. RANGE
PIN-PACKAGE
MAX498CWI
0°C to +70°C
28 SO
MAX499CWG
0°C to +70°C
24 SO
_________________Pin Configurations
Video Switching and Routing
Broadcast-Quality Composite-Video Multiplexing
TOP VIEW
Workstations
IN1A 1
24 GND
Video Editing
GND 2
23 LE
Broadcast and High-Definition TV Systems
Multimedia Products
Medical Imaging
IN2A 3
22 EN
GND 4
21 A0
IN3A 5
MAX499
20 CS
VCC 6
19 OUT1
VEE 7
18 VCC
IN1B 8
17 VEE
GND 9
16 OUT2
IN2B 10
15 N.C.
GND 11
14 OUT3
IN3B 12
13 N.C.
SO
MAX498 appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
MAX498/MAX499
_______________General Description
The MAX498/MAX499 are high-speed, quad/triple, single-pole/double-throw video switches with on-board
closed-loop buffer amplifiers. The buffer amplifiers feature +6dB gain (AVCL = 2V/V), 250MHz -3dB bandwidth, 70MHz 0.1dB gain flatness, and 1250V/µs slew
rate. Fast switching time (3ns) and fast settling time
(12ns for a 4V step) make these devices excellent
choices for a wide variety of video applications. The low
differential gain/phase errors (0.03%/0.06°) and wide
bandwidth make them ideal for both composite-video
and RGB applications. The amplifiers are capable of
delivering ±2.5V into back-terminated 50Ω or 75Ω
cables, and they deliver ±2V to a 75Ω load, allowing
multiple cables to be driven from a single output.
For implementation of large switch arrays, a low-power
disable mode places the amplifier outputs in a highimpedance state. Channel selection and output
enable/disable are controlled by four TTL/CMOScompatible logic inputs. Each video input is isolated by
an AC-ground pin, which minimizes channel-to-channel
capacitance and reduces crosstalk to 90dB at 10MHz.
The four-channel MAX498 dissipates 390mW (typical)
from ±5VDC power supplies with all output buffers
enabled. Power consumption is reduced to 130mW with
all buffers disabled. The corresponding dissipation for
the three-channel MAX499 is 300mW enabled and
100mW disabled.
MAX498/MAX499
Quad/Triple, SPDT, RGB Switches
with 250MHz Video Buffer Amplifiers
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VCC to VEE)................................................+12V
Voltage on IN_ _ to GND ..................(VEE - 0.3V) to (VCC + 0.3V)
Voltage on Digital Inputs
(LE, EN, A0, CS) .........................................-0.3V to (VCC + 0.3V)
Voltage on OUT_ (disabled) ..................................................±4V
Output Short-Circuit Duration
to -4V ≤ OUT_ ≤ +4V ..................................................Continuous
Continuous Power Dissipation (TA = +70°C)
24-Pin SO (derate 11.76mW/°C above +70°C).............941mW
28-Pin SO (derate 12.5mW/°C above +70°C)......................1W
Operating Temperature Range .................................0°C to +70°
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +5V, VEE = -5V, VIN_ _ = 0V, RL = 150Ω, LE = EN = CS = 0V, TA = 0°C to +70°C, unless otherwise noted. Typical values are at
TA = +25°C.)
PARAMETER
Input Voltage Range
Voltage Gain
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Resistance
Input Capacitance
Output Short-Circuit Current
SYMBOL
CONDITIONS
VIN
AV
MIN
TYP
±1.25
±1.70
1.985
2.030
RL = 75Ω, -1.0V ≤ VIN ≤ +1.0V
1.965
2.030
VOS
±2
±50
IB
±1
RIN
-1.25V ≤ VIN ≤ +1.25V
CIN
Channel on or off
Output Current
IOUT_
On Output Resistance
ROUT
200
-3.5V ≤ OUT_ ≤ +3.5V (Note 1)
-2.0V ≤ VOUT_ ≤ +2.0V, RL = 75Ω
On Output Impedance
f = 10MHz
Off Output Resistance
-2.50V ≤ VOUT ≤ +2.50V
±27
1.0
Operating Supply-Voltage Range
UNITS
V
RL = 150Ω, -1.25V ≤ VIN ≤ +1.25V
TCVOS
IOUT(SC)
MAX
±9
V/V
mV
µV/°C
±7
700
µA
kΩ
2
pF
120
mA
±40
mA
0.15
Ω
3.0
Ω
1.2
kΩ
±4.50
±5.50
V
Positive Power-Supply Rejection
PSR+
4.50V ≤ VCC ≤ 5.50V, VEE = -5.0V
55
72
dB
Negative Power-Supply
Rejection
PSR-
-5.50V ≤ VEE ≤ -4.5V, VCC = +5.0V
55
72
dB
Logic Low Voltage
VINLL
Logic High Voltage
VINLH
Logic Input Current
IINL
0.8
0V ≤ VINL ≤ VCC
EN = 0
Positive Supply Current
ICC
EN = 1
EN = 0
Negative Supply Current
IEE
EN = 1
Note 1:
2
V
-10
2
V
130
µA
MAX498
40
52
MAX499
31
41
MAX498
14
17
MAX499
11
14
MAX498
38
50
MAX499
29
39
MAX498
12
15
MAX499
9
12
Limited by package power dissipation.
_______________________________________________________________________________________
mA
mA
Quad/Triple, SPDT, RGB Switches
with 250MHz Video Buffer Amplifiers
MAX498/MAX499
AC ELECTRICAL CHARACTERISTICS
(VCC = +5V, VEE = -5V, VIN_ _ = 0V, RL = 100Ω, LE = EN = CS = 0V, TA = +25°C, unless otherwise noted.)
PARAMETER
Small-Signal, -3dB Bandwidth
SYMBOL
BW-3dB
±0.1dB Gain Flatness
Full-Power, -3dB Bandwidth
FPBW
CONDITIONS
MIN
TYP
MAX
UNITS
VIN ≤ 100mVp-p
250
MHz
VIN ≤ 100mVp-p
70
MHz
VOUT = ±2V
135
MHz
1250
V/µs
Slew Rate
SR
VOUT = 4V step
Settling Time
ts
0.1%, VOUT = 4V step
12
ns
f = 100kHz
7.8
nV/√Hz
pA/√Hz
Input Voltage Noise Density
Input Current Noise Density
f = 100kHz
2.6
Total Harmonic Distortion
THD
f = 10MHz
-50
dB
Spurious-Free Dynamic Range
SFDR
fC = 3MHz
-66
dBc
Adjacent-Channel Crosstalk
f = 10MHz (Note 2)
90
dB
All-Hostile Crosstalk
f = 10MHz (Note 3)
62
dB
Off-Isolation
EN = 1, f = 10MHz (Note 4)
81
dB
Differential Gain
f = 3.58MHz (Note 5), RL = 150Ω
0.03
%
Diff Phase f = 3.58MHz (Note 5), RL = 150Ω
0.06
degrees
Diff Gain
Differential Phase
TIMING CHARACTERISTICS
(VCC = +5V, VEE = -5V, VIN_ _ = 0V, RL = 150Ω, LE = EN = CS = 0V, TA = 0°C to +70°C. Typical values are at TA = +25°C, unless
otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
A0/EN to CS Setup Time
tSU
LE = high (Note 6)
A0/EN to CS Hold Time
tH
LE = high (Note 6)
CS Pulse Width
tCS
(Note 6)
Channel-Switching
Propagation Delay
tPD
(Note 7)
Channel-Switching Time
tSW
(Note 8)
Channel-Switching Transient
VINA = VINB = 0V
Enable/Disable Switching
Transient
VINA = VINB = 0V
MIN
TYP
MAX
8
UNITS
ns
4
15
ns
ns
20
ns
3
ns
Positive
70
Negative
50
Positive
10
Negative
150
mV
mV
Amplifier-Disable Time
tOFF
(Note 9)
16
ns
Amplifier-Enable Time
tON
(Note 10)
24
ns
Test-channel input grounded through a 50Ω resistor. Adjacent channel driven to a 2Vp-p output with a 10MHz sine wave
(Figure 9).
Note 3: Same as Note 2, except all channels but the test channel are driven to a 2Vp-p output with a 10MHz sine wave (Figure 9).
Note 4: Test-channel input connected to a 2Vp-p sine wave at 10MHz. The test channel’s output is measured with the outputs
disabled (Figure 9).
Note 5: Input test signal is a 3.58MHz sine wave of 40IRE amplitude, superimposed on a 0IRE to 100IRE linear ramp (Figure 10).
Note 6: Guaranteed by design.
Note 7: VINA = +1V, VINB = -1V, delay from CS to 10% of VOUT.
Note 8: VINA = +1V, VINB = -1V, delay from CS to 10% of VOUT.
Note 9: Delay from EN to 90% of VOUT.
Note 10: Delay from EN to 10% of VOUT.
Note 2:
_______________________________________________________________________________________
3
__________________________________________Typical Operating Characteristics
(VCC = +5V, VEE = -5V, RL = 100Ω, TA = +25°C, unless otherwise noted.)
5.9
3
1
5.5
0
5.4
-1
5.3
100M
1G
2
1
0
1M
FREQUENCY (Hz)
1M
1G
GAIN (dB)
5
4
3
1000
100
OUT0–OUT1
0.06
OUT0–OUT3
0.02
-0.02
2
0
10M
100M
10M
10k
100M
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
OFF-ISOLATION
vs. FREQUENCY
CROSSTALK
vs. FREQUENCY
POWER-SUPPLY REJECTION
vs. FREQUENCY
-40
-25
-35
-60
-70
ALL HOSTILE
-40
-60
ADJACENT
PSR (dB)
CROSSTALK (dB)
-20
-50
-55
-80
-65
-100
-75
-90
-120
-85
-100
-140
100M
FREQUENCY (Hz)
1G
PSR-
-45
-80
10M
MAX498/499-09
VOUT = 2Vp-p
0
-15
MAX498/499-08
20
MAX498/499-07
-30
1M
100k
FREQUENCY (Hz)
-20
4
1M
500M
1
0.01
-0.10
1M
10
0.1
OUT0–OUT2
-0.06
1
1G
OUTPUT IMPEDANCE
vs. FREQUENCY
VOUT = 2Vp-p
0.10
100M
10M
FREQUENCY (Hz)
0.14
6
GAIN (dB)
100M
LARGE-SIGNAL GAIN
vs. FREQUENCY
MAX498/499-04
RL = 50Ω
VOUT = 2Vp-p
7
10M
FREQUENCY (Hz)
LARGE-SIGNAL GAIN
vs. FREQUENCY
8
4
MAX498/499 TOC-06
10M
5
3
MAX498/499-05
1M
MAX498/499-02
5.7
5.6
VOUT = 2Vp-p
7
6
5.8
2
8
GAIN (dB)
6.0
5
GAIN (dB)
GAIN (dB)
6
4
VIN = 20mVp-p
6.1
IMPEDANCE (Ω)
VIN = 20mVp-p
7
LARGE-SIGNAL GAIN
vs. FREQUENCY
6.2
MAX498/499-01
8
GAIN FLATNESS
vs. FREQUENCY
MAX498/499-03
SMALL-SIGNAL GAIN
vs. FREQUENCY
OFF-ISOLATION (dB)
MAX498/MAX499
Quad/Triple, SPDT, RGB Switches
with 250MHz Video Buffer Amplifiers
PSR+
-95
1M
10M
FREQUENCY (Hz)
100M
30k 0.1M
1M
10M
FREQUENCY (Hz)
_______________________________________________________________________________________
100M
Quad/Triple, SPDT, RGB Switches
with 250MHz Video Buffer Amplifiers
MAX498/MAX499
____________________________Typical Operating Characteristics (continued)
(VCC = +5V, VEE = -5V, RL = 100Ω, TA = +25°C, unless otherwise noted.)
MAX498
SUPPLY CURRENT
vs. TEMPERATURE
DISABLED SUPPLY CURRENT
vs. TEMPERATURE
GAIN vs. TEMPERATURE
40
IEE
SUPPLY CURRENT (mA)
ICC
13
ICC
12
11
IEE
10
35
MAX498/499-12
EN = HIGH (OUTPUTS DISABLED)
14
45
2.0200
MAX498/499-11
MAX498/499-10
15
CURRENT (mA)
SUPPLY CURRENT (mA)
50
2.0175
VIN = +1V
VIN = -1V
2.0150
2.0125
9
30
2.0100
-55 -35
8
-35
-15
5
25
45
65
85
-55
TEMPERATURE (°C)
-35
-15
5
25
45
65
85
8
2
0
-2
-4
-6
-8
6
0
-2
-4
-6
-8
-10
45
65
85
-55
-35
TEMPERATURE (°C)
65
85
+1
-1
+2
-1
+2
OUT 0
OUT 0
OUT 0
-2
-2
-2
TIME (10ns/div)
45
IN 0
VOLTAGE (V)
+2
25
LARGE-SIGNAL
PULSE RESPONSE (CL = 100pF)
MAX498/499 TOC-17
+1
IN 0
VOLTAGE (V)
VOLTAGE (V)
-1
5
LARGE-SIGNAL
PULSE RESPONSE (CL = 47pF)
MAX498/499 TOC-16
+1
-15
TEMPERATURE (°C)
LARGE-SIGNAL
PULSE RESPONSE
IN 0
85
2
-12
25
65
4
-10
5
45
MAX498/499-14
MAX498/499-13
10
INPUT BIAS CURRENT (µA)
VOS (mV)
10
8
6
4
-15
25
INPUT BIAS CURRENT
vs. TEMPERATURE
12
-35
5
TEMPERATURE (°C)
INPUT OFFSET VOLTAGE
vs. TEMPERATURE
-55
-15
TEMPERATURE (°C)
TIME (10ns/div)
MAX498/499 TOC-18
-55
TIME (10ns/div)
_______________________________________________________________________________________
5
Quad/Triple, SPDT, RGB Switches
with 250MHz Video Buffer Amplifiers
MAX498/MAX499
____________________________Typical Operating Characteristics (continued)
(VCC = +5V, VEE = -5V, RL = 100Ω, TA = +25°C, unless otherwise noted.)
SMALL-SIGNAL
PULSE RESPONSE
-100
+200
+200
OUT
0
MAX498/499 TOC-21
+100
IN
+200
OUT
0
0
-100
0
-200
-200
CHANNEL SWITCHING
ENABLE/DISABLE
SWITCHING
CHANNEL-SWITCHING
TRANSIENT
VOLTAGE (V)
+2
0
-2
+5
OUT
0
+5
A0
0
+100m
OUT_
0
+5
ENABLE
A0
MAX498/499 TOC-24
TIME (10ns/div)
MAX498/499 TOC-23
TIME (10ns/div)
MAX498/499 TOC-22
TIME (10ns/div)
+2
-100m
0
0
TIME (10ns/div)
TIME (10ns/div)
TIME (50ns/div)
IN_A = -1V
IN_B = +1V
ENABLE/DISABLE
SWITCHING TRANSIENT
0
+100m
0
OUT_
-100m
MAX498/499-26
300
280
260
BANDWIDTH (MHz)
ENABLE
BANDWIDTH
vs. INPUT VOLTAGE
MAX498/499 TOC-25
+5
VOLTAGE (V)
VOLTAGE (V)
MAX498/499 TOC-20
-100
-200
OUT_
0
VOLTAGE (V)
OUT
+100
IN
VOLTAGE (mV)
VOLTAGE (mV)
0
VOLTAGE (mV)
MAX498/499 TOC-19
+100
IN
SMALL-SIGNAL
PULSE RESPONSE (CL = 100pF)
SMALL-SIGNAL
PULSE RESPONSE (CL = 47pF)
240
220
200
180
160
TIME 50ns/div
140
120
0.01
0.1
1
INPUT VOLTAGE (Vp-p)
6
_______________________________________________________________________________________
10
Quad/Triple, SPDT, RGB Switches
with 250MHz Video Buffer Amplifiers
PIN
NAME
FUNCTION
2, 4, 9,
11, 24
GND
Analog Ground. All ground pins are internally connected. Connect all ground pins externally to
ground to minimize impedance.
2
1
IN1A
Signal Input 1, Channel A
4
3
IN2A
Signal Input 2, Channel A
6
5
IN3A
Signal Input 3, Channel A
7, 22
6, 18
VCC
Positive Power-Supply Voltage. Connect VCC to +5V. VCC pins are internally connected.
Connect both pins externally to +5V to minimize supply impedance. Bypass each pin to
ground with a 0.1µF ceramic capacitor.
8
—
IN0B
Signal Input 0, Channel B
9, 21
7, 17
VEE
Negative Power-Supply Voltage. Connect VEE to -5V. VEE pins are internally connected.
Connect both pins to -5V externally to minimize supply impedance. Bypass each pin to
ground with a 0.1µF ceramic capacitor.
10
8
IN1B
Signal Input 1, Channel B
12
10
IN2B
Signal Input 2, Channel B
14
12
IN3B
Signal Input 3, Channel B
15, 17
13, 15
N.C.
No Connect. Not internally connected; connect to GND.
16
14
OUT3
Output 3
18
16
OUT2
Output 2
20
19
OUT1
Output 1
23
—
OUT0
Output 0
24
20
CS
Chip-Select Input. When CS is low, the A0 and EN latches are transparent. The data present at A0
is latched when CS goes high. LE’s status determines whether EN is latched along with A0, or if the
EN latch remains transparent independently of CS.
25
21
A0
Address Input. A0 = 0 selects channel A, and A0 = 1 selects channel B if CS is low. A0 is
latched on CS’s low-to-high transition.
26
22
EN
Output Buffer-Enable Input. EN = 0 enables the output buffer amplifiers, and EN = 1 disables
the output buffers if CS is low. EN is latched during CS’s low-to-high transition if LE is high. EN
is not latched if LE is low.
27
23
LE
Latch-Enable Input. With LE = 1, EN is latched along with A0 when CS goes high. When LE = 0,
the EN latch is transparent independently of CS’s state.
28
—
IN0A
MAX498
MAX499
1, 3, 5,
11, 13,
19
Signal Input 0, Channel A
_______________________________________________________________________________________
7
MAX498/MAX499
______________________________________________________________Pin Description
MAX498/MAX499
Quad/Triple, SPDT, RGB Switches
with 250MHz Video Buffer Amplifiers
1
2
3
4
5
6
7
+5VDC
10µF
GND
IN0A
IN1A
LE
GND
EN
IN2A
A0
GND
CS
IN3A
MAX498
OUT0
VCC
VCC
28
27
26
25
24
23
22
+5VDC
0.1µF
0.1µF
8
IN0B
VEE
21
-5VDC
0.1µF
9
-5VDC
10µF
VEE
OUT1
IN1B
GND
GND
OUT2
IN2B
N.C.
GND
OUT3
IN3B
N.C.
20
0.1µF
10
11
12
13
14
EIGHT-IN/FOUR-OUT
VIDEO MUX AMP
19
18
17
16
15
NOTE: ALL RESISTORS ARE 50Ω OR 75Ω
Figure 1a. MAX498 Typical Application Circuit
8
_______________________________________________________________________________________
Quad/Triple, SPDT, RGB Switches
with 250MHz Video Buffer Amplifiers
2
3
4
5
6
+5VDC
10µF
IN1A
GND
GND
LE
IN2A
EN
GND
A0
IN3A
CS
VCC
MAX499
OUT1
MAX498/MAX499
1
24
23
22
21
20
19
0.1µF
7
+5VDC
10µF
VEE
VCC
18
0.1µF
+5VDC
0.1µF
8
IN1B
VEE
17
-5VDC
0.1µF
9
10
11
12
GND
OUT2
IN2B
N.C.
GND
OUT3
IN3B
N.C.
SIX-IN/THREE-OUT
VIDEO MUX AMP
16
15
14
13
NOTE: ALL RESISTORS ARE 50Ω OR 75Ω
Figure 1b. MAX499 Typical Application Circuit
_______________________________________________________________________________________
9
MAX498/MAX499
Quad/Triple, SPDT, RGB Switches
with 250MHz Video Buffer Amplifiers
______________ Detailed Description
The MAX498/MAX499 are quad/triple video switches
with high-speed, closed-loop, voltage-feedback amplifiers set to a 2V/V gain. Figure 1 shows typical application circuits. The amplifiers use a unique two-stage,
voltage-feedback architecture that combines the benefits of conventional voltage-feedback and currentfeedback topologies to achieve wide bandwidths and
high slew rates while maintaining precision.
Figure 2 is a simplified block diagram of the MAX498/
MAX499. All four amplifier/switch blocks are identical to
that shown for Ch_0. A common control logic block
accepts external logic inputs A0, EN, CS, and LE,
and controls the status of switches S1, S2, and S3 of
each amplifier in parallel, as described in the Digital
Interface section.
S3 is open in the enabled state, and if Ch_A is selected, S1 is connected to IN_A and S2 is connected to
GND. If Ch_B is selected, S1 is connected to GND and
S2 is connected to IN_B. Connecting the deselected
GM_ block to GND ensures minimum feedthrough.
S3 is closed in the disabled state, and both S1 and S2
are connected to GND. Disconnecting both inputs and
connecting the amplifier’s inputs to GND significantly
improves off-isolation.
__________Applications Information
Power Dissipation
The MAX498/MAX499’s maximum output current is limited by the package’s maximum allowable power dissipation. The maximum junction temperature should not
exceed +150°C. Power dissipation increases with load,
and this increase can be approximated by one of the
following equations:
For VOUT > 0V: |VCC - VOUT| ILOAD
OR
For VOUT < 0V: |VEE - VOUT| ILOAD.
These devices can drive 100Ω loads connected to
each of the outputs over the entire rated output swing
and temperature range. While the output is short-circuit
protected to 120mA, this does not necessarily guarantee that under all conditions, the maximum junction
temperature will not be exceeded. Do not exceed the
derating values given in the Absolute Maximum Ratings
section.
10
IN0A
MAX498
MAX499
GM_A
S1
CHANNEL 0
X1
CC
OUT0
R0
IN0B
GM_B
S2
X1
RFB
S3
RG
CHANNEL 1
CHANNEL 2
CHANNEL 3
S1
S2
S3
A0
EN
CONTROL LOGIC
CS
LE
Figure 2. Block Diagram
Total Noise
The MAX498/MAX499’s low 2.6pA/√Hz input current
noise and 7.8nV/√Hz voltage noise provide for lower
total noise compared to typical current-mode feedback
amplifiers, which usually have significantly higher input
current noise. The input current noise multiplied by the
feedback resistor is the dominant noise source of current-mode feedback amplifiers.
Differential Gain and Phase Errors
Differential gain and phase errors are critical specifications for a buffer in composite (NTSC, PAL, SECAM) video
applications, because these errors correspond directly to
color changes in the displayed picture of composite video
systems. The MAX498/MAX499’s low differential gain and
phase errors (0.03%/0.06°) make them ideal in broadcastquality, composite video applications.
______________________________________________________________________________________
Quad/Triple, SPDT, RGB Switches
with 250MHz Video Buffer Amplifiers
14
14
RISO = 0Ω
12
10
47pF
GAIN (dB)
8
6
0pF
4
2
6
0pF
4
2
0
0
-2
-2
-4
-4
-6
-6
1M
10M
100M
1M
1G
Figure 3a. Small-Signal Gain vs. Frequency and Load
Capacitor (RL = 100Ω, RISO = 0Ω)
100M
1G
Figure 3b. Small-Signal Gain vs. Frequency and Load
Capacitor (RL = 100Ω, RISO = 6.8Ω)
+1
+100
VIN
-100
-1
VOLTAGE (mV)
VOLTAGE (V)
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
VIN
100pF
150pF
10
47pF
8
GAIN (dB)
RISO = 6.8Ω
12
100pF
MAX498/MAX499
MAX186/MAX188
FULL POWER-DOWN
MAX186/MAX188
FULL POWER-DOWN
+2
VOUT
+200
VOUT
-200
-2
TIME (10ns/div)
Figure 4a. Large-Signal Pulse Response with CL = 100pF and
RISO = 5.1Ω
TIME (10ns/div)
Figure 4b. Small-Signal Pulse Response with CL = 100pF and
RISO = 5.1Ω
Coaxial Cable Drivers
Capacitive-Load Driving
High-speed performance, excellent output current
capability, and an internally fixed gain of +2 make the
MAX498/MAX499 ideal for driving back-terminated 50Ω
or 75Ω coaxial cables to ±2.5V.
In a typical application, the MAX498/MAX499 drive a
back-terminated cable (Figure 1). The back-termination
resistor, at the output, matches the impedance of the
cable’s driven end to the cable’s impedance, eliminating
signal reflections. This resistor, along with the loadtermination resistor, forms a voltage divider with the load
impedance, which attenuates the signal at the cable’s
output by one-half. The MAX498/MAX499 operate with
an internal +2V/V closed-loop gain to provide unity gain
at the cable’s output.
In most amplifier circuits, driving large capacitive loads
increases the likelihood of oscillation. This is especially
true for circuits with high loop gains, such as voltage
followers. The amplifier’s output resistance and the
capacitive load form an RC filter that adds a pole to the
loop response. If the pole frequency is low enough (as
when driving a large capacitive load), the circuit-phase
margin is degraded and oscillation may occur.
The MAX498/MAX499 drive capacitive loads up to
100pF without sustained oscillation, although some
peaking may occur (Figures 3a and 3b). When driving
larger capacitive loads, or to reduce peaking, add an
isolation resistor (RISO) between the output and the
capacitive load (Figures 4a, 4b, and 5).
______________________________________________________________________________________
11
Quad/Triple, SPDT, RGB Switches
with 250MHz Video Buffer Amplifiers
MAX498/MAX499
COMPARATOR INPUT BIAS CURRENT
vs. SUPPLY VOLTAGE
MAX186/MAX188
FULL POWER-DOWN
8
-82
-84
DISTORTION (dBc)
ISOLATION RESISTOR (Ω)
7
6
5
4
-88
-90
-92
-94
3
-96
2
-98
47
100
150
200
270
390
510
CAPACITANCE (pF)
Figure 5. Isolation Resistor vs. Capacitive Load
Switching Audio Signals
(Audio-Distortion Measurement)
When switching audio signals, distortion is the prime
consideration in performance. Figure 6 shows total
harmonic distortion vs. frequency, in the audio range,
for the MAX498/MAX499.
Large Switch Arrays
Large crosspoint switch arrays are possible with the
MAX498/MAX499 using the enable function EN. When
the amplifiers are disabled, output impedance is typically 1.2kΩ, due to the feedback and gain resistors.
This limits the number of outputs that can be paralleled
without a buffer. Since each output can drive 100Ω,
eight outputs can typically be connected together. If
additional outputs must be connected in parallel, a
MAX4178 (single), MAX496 (quad), or equivalent unitygain buffer can be used.
Whether enabled or disabled, each input represents
more than 200kΩ of resistance. Capacitance is the
prime consideration limiting the number of inputs that
can be connected to a single output. Since each output
can drive 100pF of capacitance without an isolation
resistor, 50 inputs (CIN = 2pF, typical) can be driven
by a single output. However, peaking will occur as
inputs are added (Figure 3), which reduces the 0.1dB
bandwidth.
12
-86
10
100
1k
10k
FREQUENCY (Hz)
Figure 6. Total Harmonic Distortion (Audio) vs. Frequency
Digital Interface
The MAX498/MAX499 multiplexer architecture ensures
that no input channels are ever connected together.
Select a channel by changing A0’s state (A0 = 0 for
channel A, and A0 = 1 for channel B) and pulsing CS low
(see Tables 1a and 1b). Figure 7 shows the logic timing
diagram.
—–
When the enable input (EN) is driven to a TTL low state,—–it
enables the MAX498/MAX499 amplifier outputs. When EN
is driven high, it disables the amplifier outputs. When
disabled, the MAX498/MAX499 exhibit a 1.2kΩ disabled output resistance due to their internal feedback
resistors.
—–
LE determines whether EN is latched by CS or operates
independently. When the latch-enable input (LE) is con—–
nected to V+, CS becomes the latch—control
for the EN
–
input register. If CS is low, both the EN and A0 latches
—–
are transparent; once CS returns high, both A0 and EN
are latched.
—–
When LE is connected to ground, the EN latch is transparent and independent of CS. This allows all
MAX498/MAX499 devices to be shut down simultaneously, regardless of CS’s input state.
—– Simply connect
LE to ground and connect all E N inputs together
(Figure 8a). Hard wire LE to V+ or ground (rather than
driving LE with a gate) to prevent crosstalk from the
digital inputs to IN0A.
______________________________________________________________________________________
Quad/Triple, SPDT, RGB Switches
with 250MHz Video Buffer Amplifiers
Grounding and Layout
The MAX498/MAX499 bandwidths are in the RF frequency range. Depending on the size of the PC board
used and the frequency of operation, it may be necessary to use Micro-strip or Stripline techniques.
To realize the full AC performance of these high-speed
buffers, pay careful attention to power-supply bypassing
and board layout. The PC board should have at least two
layers (wire-wrap boards are too inductive, and bread
boards are too capacitive), with one side a signal layer
and the other a large, low-impedance ground plane. With
multilayer boards, locate the ground plane on the layer
that is not dedicated to a specific signal trace. The ground
plane should be as free from voids as possible. Connect
all ground pins to the ground plane.
Connect both positive power-supply pins together and
bypass with a 0.10µF ceramic capacitor at each powersupply pin, as close to the device as possible. Repeat
for the negative power-supply pins. The capacitor lead
lengths should be as short as possible to minimize lead
inductance; surface-mount chip capacitors are ideal. A
large-value (10µF or greater) tantalum or electrolytic
bypass capacitor on each supply may be required for
high-current loads. The location of this capacitor is not
critical.
The MAX498/MAX499’s analog input pins are isolated
with ground pins to minimize parasitic coupling, which can
degrade crosstalk and/or amplifier stability. Keep signal
paths as short as possible to minimize inductance. Ensure
that all input channel traces are the same length, to maintain the phase relationship between the four channels. To
further reduce crosstalk, connect the coaxial-cable shield
to the ground side of the 75Ω terminating resistor at the
ground plane, and terminate all unused inputs to ground
and outputs with a 100Ω or 150Ω resistor to ground.
MAX498/MAX499
Another option for output disable is to connect LE to V+,
parallel
the outputs of several MAX498/MAX499s, and use
—–
EN to individually disable all devices but the one in use
(Figure 8b).
When the outputs are disabled, off-isolation from the
analog inputs to the amplifier outputs is typically 81dB
at 10MHz.
Table 1a. Amplifier and Channel
Selection with LE = V+
FUNCTION
CS EN A0
Enables amplifier outputs. Selects
channel A.
Enables amplifier outputs. Selects
channel B.
0
0
0
0
0
1
0
1
X
Disables amplifiers. Outputs high-Z.
1
X
X
Latches A0, EN. Outputs unchanged.
Table 1b. Amplifier and Channel
Selection with LE = GND
FUNCTION
CE EN A0
0
0
0
Enables amplifier outputs. Selects
channel A.
1
0
X
Enables amplifier outputs. Latches A0
to output A or B, according to A0’s
—–
state at CS’s last edge.
X
1
X
0
0
1
Disables amplifiers. Outputs high-Z.
A0 latch = channel A.
Enables amplifier outputs. Selects
channel B.
______________________________________________________________________________________
13
MAX498/MAX499
Quad/Triple, SPDT, RGB Switches
with 250MHz Video Buffer Amplifiers
tCS
CS
tSU
tH
A0
tSU
tH
EN
tON
tOFF
tPD
OUTPUTS
tSW
LE = V+
Figure 7. Logic Timing Diagram
EN
AO
LE
SHUTDOWN
EN
CS
MAX498
MAX499
+5V
LE
MAX498
MAX499
EN
AO
LE
CS
MAX498
MAX499
EN
NOTE: ISOLATION RESISTORS
(IF REQUIRED) NOT SHOWN.
(a)
+5V
LE
MAX498
MAX499
(b)
–—–
–—–
Figure 8. (a) Simultaneous Shutdown of all MAX498/MAX499s; (b) Enable (EN) Register Latched by CS
14
______________________________________________________________________________________
Quad/Triple, SPDT, RGB Switches
with 250MHz Video Buffer Amplifiers
50Ω
VIN = 4Vp-p,
f = 10MHz,
RS = 75Ω
MAX498/MAX499
MAX498/MAX499
MAX498/MAX499
50Ω
100Ω
100Ω
50Ω
100Ω
50Ω
100Ω
50Ω
100Ω
50Ω
100Ω
50Ω
100Ω
VIN = 4Vp-p,
f = 10MHz,
RS = 75Ω
a) ADJACENT CHANNEL
50Ω
100Ω
b) ALL HOSTILE
Figure 9. Test Circuits for Measuring Crosstalk: a) Adjacent Channel; b) All Hostile
75Ω CABLE
75Ω
75Ω
MAX499
75Ω CABLE
75Ω CABLE
DUT
SOURCE:
TEKTRONIX
1910 DIGITAL GENERATOR
75Ω
75Ω
MEASUREMENT:
TEKTRONIX VM700
VIDEO MEASUREMENT
SET
Figure 10. Differential Phase and Gain Error Test Circuit
______________________________________________________________________________________
15
MAX498/MAX499
Quad/Triple, SPDT, RGB Switches
with 250MHz Video Buffer Amplifiers
____Pin Configurations (continued)
___________________Chip Information
SUBSTRATE CONNECTED TO: VEE
TRANSISTOR COUNT: 813
TOP VIEW
GND 1
28 IN0A
IN1A 2
27 LE
GND 3
26 EN
IN2A 4
25 A0
GND 5
MAX498
24 CS
IN3A 6
23 OUT0
VCC 7
22 VCC
IN0B 8
21 VEE
20 OUT1
VEE 9
IN1B 10
19 GND
GND 11
18 OUT2
IN2B 12
17 N.C.
GND 13
16 OUT3
IN3B 14
15 N.C.
SO
________________________________________________________Package Information
DIM
D
0°- 8°
A
e
B
0.101mm
0.004in.
A1
C
L
A
A1
B
C
E
e
H
L
INCHES
MAX
MIN
0.104
0.093
0.012
0.004
0.019
0.014
0.013
0.009
0.299
0.291
0.050
0.419
0.394
0.050
0.016
DIM PINS
E
H
Wide SO
SMALL-OUTLINE
PACKAGE
(0.300 in.)
D
D
D
D
D
16
18
20
24
28
INCHES
MIN MAX
0.398 0.413
0.447 0.463
0.496 0.512
0.598 0.614
0.697 0.713
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.30
0.35
0.49
0.23
0.32
7.40
7.60
1.27
10.00
10.65
0.40
1.27
MILLIMETERS
MIN
MAX
10.10 10.50
11.35 11.75
12.60 13.00
15.20 15.60
17.70 18.10
21-0042A
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 1996 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.