SPICE Device Model SUD25N15-52 www.vishay.com Vishay Siliconix N-Channel 150 V (D-S) 175 °C MOSFET DESCRIPTION CHARACTERISTICS The attached SPICE model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the - 55 °C to 125 °C temperature ranges under the pulsed 0 V to 10 V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. • N-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the - 55 °C to + 125 °C Temperature Range • Model the Gate Charge SUBCIRCUIT MODEL SCHEMATIC D 4 R1 3 M2 G 1 DBD 2 CGS M1 S Note • This document is intended as a SPICE modeling guideline and does not constitute a commercial product datasheet. Designers should refer to the appropriate datasheet of the same number for guaranteed specification limits. S13-0485-Rev. C, 11-Mar-13 1 Document Number: 70553 THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SPICE Device Model SUD25N15-52 www.vishay.com Vishay Siliconix SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SIMULATED MEASURED DATA DATA UNIT SYMBOL TEST CONDITIONS Gate Threshold Voltage VGS(th) VDS = VGS, ID = 250 μA 3 - V On-State Drain Currenta ID(on) VDS = 5 V, VGS = 10 V 124 - A Static Drain-Source On-State Resistancea Diode Forward Voltage RDS(on) VSD VGS = 10 V, ID = 5 A 0.040 0.042 VGS = 10 V, ID = 5 A, TJ = 125 °C 0.070 - VGS = 10 V, ID = 5 A, TJ = 175 °C 0.086 - VGS = 6 V, ID = 5 A 0.047 0.047 IS = 15 A, VGS = 0 V 0.89 0.90 1695 1725 V Dynamicb Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Total Gate Charge 231 216 Crss 101 100 Qg 34 33 Gate-Source Charge Qgs Gate-Drain Charge Qgd Turn-On Delay Time td(on) Rise Time Turn-Off Delay Time VDS = 25 V, VGS = 0 V, f = 1 MHz tr td(off) Fall Time tf Source-Drain Reverse Recovery Time trr VDS = 75 V, VGS = 10 V, ID = 25 A VDD = 50 V, RL = 3 ID = 25 A, VGEN = 10 V, Rg = 2.5 IF = 25 A, dI/dt = 100 A/μs 9 9 12 12 33 15 40 70 55 25 60 60 69 95 pF nC ns Notes a. Pulse test; pulse width 300 μs, duty cycle 2 %. b. Guaranteed by design, not subject to production testing. S13-0485-Rev. C, 11-Mar-13 2 Document Number: 70553 THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SPICE Device Model SUD25N15-52 www.vishay.com Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ = 25 °C, unless otherwise noted) Note • Dots and squares represent measured data. S13-0485-Rev. C, 11-Mar-13 3 Document Number: 70553 THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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