APPLICATION NOTES AN001 INTERFACING ICM7363/43/23 TO MCS-51 MICROCONTROLLERS Sairan Sakrani ICM7363/43/23 3-Wire & Serial Interface -' / ( * ! ' 3 * $ 4 $ * # " " * '' $ * ' " $ 5 ' * * ! * # * * & + ,+ $ %& '' & ( 012 + ,+ ) * * & $ & 3 & 6 ' ! ) * + ,+ " & )* 012 7 012 * * * $ 012 $ + ,+/! & & &* # 2 012 ! * ' * ' ! & ) . + ,+/! " * ! ) $ * * * CS SDI SCK 1st bit (msb) 2nd bit … 16th bit … Figure 1.1: Serial Interface Signals AN001 Page 1 Devices ICM7363 ICM7343 ICM7323 Command Bits Bit 15 C3 C3 C3 Bit 14 C2 C2 C2 Bit 13 C1 C1 C1 Bit 12 C0 C0 C0 Data Bits Bit Bit 11 10 D11 D10 D9 D8 D7 D6 Bit 9 D9 D7 D5 Bit 8 D8 D6 D4 Bit 7 D7 D5 D3 Bit 6 D6 D4 D2 Bit 5 D5 D3 D1 Bit 4 D4 D2 D0 Bit 3 D3 D1 X Bit 2 D2 D0 X Bit 1 D1 X X Bit 0 D0 X X Table 1.1: 16-Bit Command and Data Format Command Bits C3 C2 C1 C0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Data Bits Data X Data Data X Data Data X Data Data X Data Data X Data X Target DAC A A A B B B C C C D D D A-D A-D A-D X Functions Load data into input buffer Update DAC (assert data on input buffer) Load data and update DAC simultaneously Load data into input buffer Update DAC (assert data on input buffer) Load data and update DAC simultaneously Load data into input buffer Update DAC (assert data on input buffer) Load data and update DAC simultaneously Load data into input buffer Update DAC (assert data on input buffer) Load data and update DAC simultaneously Load data into input buffer Update DAC (assert data on input buffer) Load data and update DAC simultaneously No Operation Table 1.2: ICM7363/43/23 Control Commands Interface Example using MCS-51 Microcontroller %& * ' # 3 < 9 " # %& & & & & 89:' 89:' * *) ) 5 ( ;3 < AN001 %& ' ! & 9 9=: < Page 2 8051-Based MCU VDD ICM7363/43/23 P2.3 CS CLRB P2.2 SDI SDO P2.0 SCK Circuit details omitted for clarity Figure 2.1: ICM7363/43/23 Communication Interface Example Figure 2.2: Sample assembly code for hardware in Figure 2.1 ;============================================================================ ; Description: ; Sample codes for interfacing MCS-51 MCU to ICM7363/43/23 DAC. ; This example uses Port 2 to communicate with the DAC. ; ; MCS-51 pins ICM7363/43/23 pins ; P2.0 SCK ; P2.1 CLRB (optional) ; P2.2 SDI ; P2.3 CSB ; ; P2.7 - used to generate pulse for oscilloscope triggering. ; ; Author: ; Sairan Sakrani ; 21 Feb 2003 ;============================================================================ ;Assembler-specific directives $MOD51 ;Hardware addresses P_SCK EQU P2.0 P_CLRB EQU P2.1 P_SDI EQU P2.2 P_CSB EQU P2.3 ;P2.0 ;P2.1 ;P2.2 ;P2.3 ;Variables – DAC code DACCL EQU 024H DACCH EQU 025H ;DAC code LOW byte ;DAC code HIGH byte – - SCK CLRB SDI CSB ;============================================================================ ;Interrupt Vectors ORG 0000H LJMP BEGIN ;0000H - RESET vector ORG 0003H LJMP ISEXT0 ;0003H - External 0 ORG 000BH LJMP ISTMR0 ;000BH - Timer/Counter 0 ORG 0013H LJMP ISEXT1 ;0013H – External 1 ORG 001BH LJMP ISTMR1 ;001BH – Timer/Counter 1 ORG 0023H LJMP ISSER ;0023H – Serial Port ISEXT0: AN001 Page 3 ISTMR0: ISEXT1: ISTMR1: ISSER: RETI ;Empty interrupt services ;============================================================================ ;Beginning of Main Routine ;============================================================================ ORG 0100H BEGIN: MOV MOV SP,#007H IE,#000H ;Init stack pointer ;Disable interrupts ;----- Initialize interface to DACs CLR P_CLRB ;CLRB=LOW, reset DAC SETB P_CSB ;CSB(P2.3)=HIGH CLR P_SCK ;SCK(P2.0)=LOW CLR P_SDI ;SDI(P2.2)=LOW SETB P_CLRB ;CLRB=HIGH ;----- Send code to all DACs and update simultaneously ;----- Bits to sent: 1110 bbbb bbbb bbbb MOV DACCL,#000H ;Init DAC codes MOV DACCH,#0E0H ILOOP: LCALL SNDDAC ;----- Increment DAC code MOV A, DACCL ADD A, #001H MOV DACCL, A ;Send the high and low bytes to DAC ;Increment low byte ;Save incremented low byte MOV ADDC A, DACCH A, #000H ;Increment high byte if necessary ORL ANL MOV A, #0E0H A, #0EFH DACCH, A ;Force Bit15,14,13 = 1 ;Force Bit12=0 ;Save incremented high byte ;----- Create CHKTR2: CJNE MOV CJNE CLR SETB LJMP SKPTR1: NOP NOP NOP NOP NOP SKPTR2: NOP NOP LJMP pulse#1 for oscilloscope triggering; when DAC data = 0000H A,#0E0H,SKPTR1 ;[24cyc] Check if DAC data high byte = 000H A, DACCL ;[12cyc] A,#000H,SKPTR2 ;[24cyc] Check if DAC data low byte = 000H P2.7 ;[12cyc] Generate scope trigger pulse P2.7 ;[12cyc] ILOOP ;[24cyc] Repeat; send next DAC code ILOOP ;[12cyc] NOPs for fix time interval ;[12cyc] ;[12cyc] ;[12cyc] ;[12cyc] ;[12cyc] ;[12cyc] ;[24cyc] Repeat; send next DAC code ;============================================================================ ;End of Main Routine ;============================================================================ ;============================================================================ ;Subroutine: SNDDAC ;Description: Send 16 bits of data to DAC. ; First, CSB is set to LOW, then 16 bits are sent, ; then, CSB is brought back HIGH. ;Arguments: DACCH = Data high byte (Bit15 thru Bit8) ; DACCL = Data low byte (Bit7 thru Bit0) ;Trashed: Whatever trashed by subr SN8BIT ;****************************** SNDDAC: SETB P_CSB ;CSB should already HIGH initially, do it anyhow CLR P_CSB ;CSB=LOW, initiate the data transfer MOV A,DACCH LCALL SN8BIT ;Send high byte MOV A,DACCL LCALL SN8BIT ;Send low byte AN001 Page 4 SETB P_CSB ;CSB=HIGH, end the data transfer RET ;Done ;============================================================================ ;============================================================================ ;Subroutine: SN8BIT ;Description: Send 8 bits of data on P2.2 (SDI) ; Clock the P2.0 (SCK) as needed. ;Arguments: A = data to be sent ;Trashed: C,R0 ;****************************** SN8BIT: MOV R0, #8 ;Init loop counter SN8LUP: CLR P_SCK ;CLK=L RLC A ;Set C=bit to be sent MOV P_SDI,C ;Set SDI=bit to be sent SETB P_SCK ;CLK=H, ICM7363 latches data on SDI at +ve edge DJNZ R0, SN8LUP ;Decrement counter, loop if more bits to sent CLR P_SCK ;CLK=L RET ;Done ;============================================================================ END AN001 Page 5