HD74HC174 Hex D-type Flip-Flops (with Clear) REJ03D0584-0300 Rev.3.00 Jan 31, 2006 Description This device contains 6 master-slave flip-flops with a common clock and common clear. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the clock input. The clear input when low, sets all outputs to a low state. Features • • • • • • High Speed Operation: tpd (Clock to Q) = 15 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Ordering Information Part Name HD74HC174P Package Code (Previous Code) Package Type PRDP0016AE-B (DP-16FV) DILP-16 pin Package Abbreviation P — PRSP0016DH-B FP (FP-16DAV) PTSP0016JB-A HD74HC174TELL TSSOP-16 pin T (TTP-16DAV) Note: Please consult the sales office for the above package availability. HD74HC174FPEL Taping Abbreviation (Quantity) SOP-16 pin (JEITA) EL (2,000 pcs/reel) ELL (2,000 pcs/reel) Function Table H: L: X: Clear L H H H H High level Low level Irrelevant Rev.3.00, Jan 31, 2006 page 1 of 7 Inputs Clock X L D X H L X X Output Q L H L no change no change HD74HC174 Pin Arrangement 16 VCC Clear 1 1Q 2 1D 3 2D 4 2Q 5 3D 6 3Q 7 Q CLR D CK Q CLR CK D D CK CLR Q CK D CLR Q D CK CLR Q CK D CLR Q 15 6Q 14 6D 13 5D 12 5Q 11 4D 10 4Q 9 Clock GND 8 (Top view) Logic Diagram Clock CK 1D D CL Q 1Q Q 2Q Q 3Q Q 4Q Q 5Q Q 6Q Clear CK 2D D CL CK 3D D CL 4D D CL CK CK 5D D CL CK 6D Rev.3.00, Jan 31, 2006 page 2 of 7 D CL HD74HC174 Absolute Maximum Ratings Item Supply voltage range Input / Output voltage Input / Output diode current Output current VCC, GND current Power dissipation Storage temperature Symbol VCC Vin, Vout IIK, IOK IO ICC or IGND PT Tstg Ratings –0.5 to 7.0 –0.5 to VCC +0.5 ±20 ±25 ±50 500 –65 to +150 Unit V V mA mA mA mW °C Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. Recommended Operating Conditions Item Supply voltage Input / Output voltage Operating temperature Symbol VCC VIN, VOUT Ta Input rise / fall time*1 Ratings 2 to 6 0 to VCC –40 to 85 0 to 1000 0 to 500 tr, tf Unit V V °C ns 0 to 400 Note: Conditions VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics. Electrical Characteristics Item Input voltage Symbol VCC (V) VIH VIL Output voltage VOH VOL Input current Quiescent supply current Iin ICC 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 6.0 6.0 Rev.3.00, Jan 31, 2006 page 3 of 7 Min 1.5 3.15 4.2 — — — 1.9 4.4 5.9 4.18 5.68 — — — — — — — Ta = 25°C Typ Max — — — — — — 2.0 4.5 6.0 — — 0.0 0.0 0.0 — — — — — — — 0.5 1.35 1.8 — — — — — 0.1 0.1 0.1 0.26 0.26 ±0.1 4.0 Ta = –40 to+85°C Unit Min Max 1.5 3.15 4.2 — — — 1.9 4.4 5.9 4.13 5.63 — — — — — — — — — — 0.5 1.35 1.8 — — — — — 0.1 0.1 0.1 0.33 0.33 ±1.0 40 Test Conditions V V V V Vin = VIH or VIL IOH = –20 µA Vin = VIH or VIL IOH = –4 mA IOH = –5.2 mA IOL = 20 µA IOL = 4 mA IOL = 5.2 mA µA Vin = VCC or GND µA Vin = VCC or GND, Iout = 0 µA HD74HC174 Switching Characteristics (CL = 50 pF, Input tr = tf = 6 ns) Item Maximum clock frequency Propagation delay time Symbol VCC (V) fmax tPLH, tPHL Setup time tsu Hold time th Removal time Pulse width Output rise/fall time Input capacitance trem tw tTLH, tTHL Cin 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 — Ta = 25°C Ta = –40 to +85°C Unit Min Typ Max Min Max — — — — — — — — — 100 20 17 5 5 5 25 5 4 80 16 14 — — — — — — — — 15 — — 17 — — 3 – — 0 — — –1 — — 6 — — 5 — 5 6 30 35 160 32 27 160 32 27 — — — — — — — — — — — — 75 15 13 10 — — — — — — — — — 125 25 21 5 5 5 31 6 5 100 20 17 — — — — 5 24 28 200 40 34 200 40 34 — — — — — — — — — — — — 95 19 16 10 ns Clock to Q ns Clear to Q ns Data to Clock ns Clock to Data ns Clear to Clock ns Clock, Clear ns pF Test Circuit Measurement point CL* Note: CL includes the probe and fig capacitance. Rev.3.00, Jan 31, 2006 page 4 of 7 Test Conditions MHz HD74HC174 Waveforms • Waveform – 1 tr tf 90 % Data VCC 90 % 50 % 50 % 50 % 10 % 10 % t su th 0V t su th tf tr VCC 90 % Clock 50 % 50 % 10 % 50 % 10 % tw 0V tw t PHL t PLH Q 50 % 10 % 50 % 10 % t TLH • Waveform – 2 Clear tf VOH 90 % 90 % VOL t THL tr VCC 90 % 50 % 10 % 90 % 50 % 10 % tw 0V t rem t w(clock) 90 % 90 % Clock 50 % 50 % 10 % t PHL tf 0V t r t PLH 90 % 90 % Q 50 % 10 % 50 % 10 % t THL Note : Clock Input : PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns Data Input : PRR ≤ 500 kHz Rev.3.00, Jan 31, 2006 page 5 of 7 VCC t TLH VOH VOL HD74HC174 Package Dimensions JEITA Package Code P-DIP16-6.3x19.2-2.54 RENESAS Code PRDP0016AE-B MASS[Typ.] 1.05g Previous Code DP-16FV D 9 E 16 1 8 b3 0.89 Z A1 A Reference Symbol L e Nom θ c e1 D 19.2 E 6.3 JEITA Package Code P-SOP16-5.5x10.06-1.27 RENESAS Code PRSP0016DH-B *1 Previous Code FP-16DAV 7.4 A1 0.51 b p 0.40 b 3 0.48 0.56 1.30 c 0.19 θ 0° e 2.29 0.25 0.31 2.54 2.79 15° 1.12 L 2.54 MASS[Typ.] 0.24g NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. D F 16 20.32 5.06 Z ( Ni/Pd/Au plating ) Max 7.62 1 A bp e Dimension in Millimeters Min 9 c HE *2 E bp Index mark Reference Symbol Terminal cross section ( Ni/Pd/Au plating ) 1 Z *3 bp Nom D 10.06 E 5.50 Max 10.5 A2 8 e Dimension in Millimeters Min x A1 M 0.00 0.10 0.20 0.34 0.40 0.46 0.15 0.20 0.25 7.80 8.00 A L1 2.20 bp b1 c A c A1 θ y L Detail F 1 θ 0° HE 7.50 e 1.27 x 0.12 y 0.15 0.80 Z L L Rev.3.00, Jan 31, 2006 page 6 of 7 8° 0.50 1 0.70 1.15 0.90 HD74HC174 JEITA Package Code P-TSSOP16-4.4x5-0.65 RENESAS Code PTSP0016JB-A *1 Previous Code TTP-16DAV MASS[Typ.] 0.05g NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. D F 16 9 *2 E HE c bp Reference Symbol Terminal cross section ( Ni/Pd/Au plating ) Index mark Dimension in Millimeters Min Nom Max D 5.0 5.3 E 4.40 A2 A1 Z e *3 bp L1 x 0.07 0.10 0.15 0.20 0.25 0.10 0.15 0.20 6.40 6.60 1.10 bp M b1 c A c A1 θ L y Detail F 1 θ 0° HE 6.20 8° 0.65 e x 0.13 y 0.10 0.65 Z 0.4 L L Rev.3.00, Jan 31, 2006 page 7 of 7 0.03 A 8 1 1 0.5 1.0 0.6 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. 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