RENESAS HD74HC1G08CME

HD74HC1G08
2–input AND Gate
REJ03D0185–0500Z
(Previous ADE-205-312C (Z))
Rev.5.00
Jan.27.2004
Description
The HD74HC1G08 is high speed CMOS two input AND gate using silicon gate CMOS process. With
CMOS low power dissipation, it provides high-speed equivalent to LS–TTL series. The internal circuit of
three stages construction with buffer provides wide noise margin and stable output.
Features
• The basic gate function is lined up as Renesas uni logic series.
• Supplied on emboss taping for high-speed automatic mounting.
• Electrical characteristics equivalent to the HD74HC08
Supply voltage range : 2 to 6 V
Operating temperature range : –40 to +85°C
• |IOH| = IOL = 2 mA (min)
• Ordering Information
Part Name
Package Type
Package Code
Package
Abbreviation
Taping Abbreviation
(Quantity)
HD74HC1G08CME
CMPAK-5 pin
CMPAK-5V
CM
E (3,000 pcs/reel)
Rev.5.00, Jan.27.2004, page 1 of 7
HD74HC1G08
Outline and Article Indication
• HD74HC1G08
Index band
Marking
H
= Control code
CMPAK–5
Function Table
Inputs
A
B
Output Y
L
L
L
H
L
L
L
H
L
H
H
H
H : High level
L : Low level
Pin Arrangement
IN B
1
IN A
2
GND
3
(Top view)
Rev.5.00, Jan.27.2004, page 2 of 7
2
5
VCC
4
OUT Y
HD74HC1G08
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit
Supply voltage range
VCC
–0.5 to 7.0
V
Input voltage range *1
VI
–0.5 to VCC + 0.5
V
Output voltage range *1, 2
VO
–0.5 to VCC + 0.5
V
Output : H or L
Input clamp current
IIK
±20
mA
VI < 0 or VI > VCC
Output clamp current
IOK
±20
mA
VO < 0 or VO >VCC
Continuous output current
IO
VO = 0 to VCC
±25
mA
Continuous current through ICC or IGND
VCC or GND
±25
mA
Maximum power dissipation PT
*3
at Ta = 25°C (in still air)
200
mW
Storage temperature
–65 to 150
°C
Notes:
Tstg
Test Conditions
The absolute maximum ratings are values, which must not individually be exceeded, and
furthermore, no two of which may be realized at the same time.
1. The input and output voltage ratings may be exceeded if the input and output clamp-current
ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The maximum package power dissipation was calculated using a junction temperature of 150°C.
Recommended Operating Conditions
Item
Symbol
Min
Max
Unit
Supply voltage range
VCC
2
6
V
Input voltage range
VI
0
VCC
V
Output voltage range
VO
0
VCC
V
Output current
IOL
—
2.0
mA
—
2.6
—
–2.0
—
–2.6
0
1000
0
500
VCC = 4.5 V
0
400
VCC = 6.0 V
–40
85
IOH
Input rise / fall time
tr, tf
(10% to 90%)
Operating temperature
Ta
Note: Unused or floating inputs must be held high or low.
Rev.5.00, Jan.27.2004, page 3 of 7
Test Conditions
VCC = 4.5 V
VCC = 6.0 V
mA
VCC = 4.5 V
VCC = 6.0 V
ns
°C
VCC = 2.0 V
HD74HC1G08
Electrical Characteristics
VCC
Item
Symbol (V)
Input voltage
VIH
VIL
Output voltage
VOH
VOL
Ta = 25°C
Ta = –40 to 85°C
Max
Unit Test Conditions
1.5
—
V
3.15
—
—
4.2
—
—
0.5
—
0.5
—
1.35
—
1.35
Min
Typ
Max
Min
2.0
1.5
—
—
4.5
3.15
—
—
6.0
4.2
—
2.0
—
4.5
—
6.0
—
—
1.8
—
1.8
2.0
1.9
2.0
—
1.9
—
4.5
4.4
4.5
—
4.4
—
6.0
5.9
6.0
—
5.9
—
4.5
4.18
4.31
—
4.13
—
IOH = –2 mA
6.0
5.68
5.80
—
5.63
—
IOH = –2.6 mA
2.0
—
0.0
0.1
—
0.1
IOL = 20 µA
4.5
—
0.0
0.1
—
0.1
6.0
—
0.0
0.1
—
0.1
4.5
—
0.17
0.26
—
0.33
IOL = 2 mA
6.0
—
0.18
0.26
—
0.33
IOL = 2.6 mA
V
VIN =
IOH = –20 µA
VIH or VIL
Input current
IIN
6.0
—
—
±0.1
—
±1.0
µA
VIN = VCC or GND
Operating current
ICC
6.0
—
—
1.0
—
10.0
µA
VIN = VCC or GND
Rev.5.00, Jan.27.2004, page 4 of 7
HD74HC1G08
Switching Characteristics
Ta = 25°C
Item
Symbol Min
Typ
Max
Unit
Test Conditions
Output rise / fall time
tTLH
tTHL
—
5
10
ns
Test circuit
Propagation delay time
tPLH
tPHL
—
7
15
ns
Test circuit
(CL = 15 pF, tr = tf = 6 ns, VCC = 5 V)
VCC
Ta = 25°C
Ta = –40 to 85°C
Item
Symbol (V)
Min
Typ
Max
Min
Max
Unit Test Conditions
Output rise / fall time
tTLH
2.0
—
50
125
—
155
ns
Test circuit
tTHL
4.5
—
14
25
—
31
6.0
—
12
21
—
26
tPLH
2.0
—
48
100
—
125
ns
Test circuit
tPHL
4.5
—
12
20
—
25
6.0
—
9
17
—
21
Propagation delay time
Input capacitance
CIN
—
—
2.5
5
—
5
pF
Equivalent capacitance
CPD
—
—
10
—
—
—
pF
(CL = 50 pF, tr = tf = 6 ns)
Note: CPD is equivalent capacitance inside of the IC calculated from the operating current without load (see
test circuit). The average operating current without load is calculated according to the expression
below.
ICC (opr) = CPD • VCC • fIN + ICC
Rev.5.00, Jan.27.2004, page 5 of 7
HD74HC1G08
Test Circuit
VCC
Output
Input
Pulse
generator
50 Ω
CL
Note: 1. C L includes probe and jig capacitance.
• Waveforms
t r = 6 ns
t f = 6 ns
90%
Input
VCC
90%
50%
50%
10%
10%
GND
t THL
t TLH
90%
Output
50%
50%
10%
t PLH
Rev.5.00, Jan.27.2004, page 6 of 7
VOH
90%
10%
t PHL
VOL
HD74HC1G08
Package Dimensions
(0.65)
1.25 ± 0.1
(0.65)
0 – 0.1
(0.2)
2.0 ± 0.2
0.9 ± 0.1
(0.425)
5 – 0.2 ± 0.05
+ 0.1
0.15– 0.05
2.1 ± 0.3
1.3 ± 0.2
(0.425)
Unit: mm
Package Code
JEDEC
JEITA
Mass (reference value)
Rev.5.00, Jan.27.2004, page 7 of 7
CMPAK–5V
—
Conforms
0.006 g
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Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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