TECHNICAL DATA
IN1363
CMOS LIS of Real Time Watch with Serial Interface
FEATURES
Count of seconds, minutes, hours, week days, date, months and
years with consideration of leap years (until 2100);
400 kHz, double wire serial interface;
Programmed orthogonal output signal;
Function programming of alarm, timer and interruption;
Automatic determination of the supply voltage drop;
Consumption current of less, than 450 nA with supply of 2V with the
operating oscillator;
Operating temperature range: -40С – 85С.
SOP- 8
MSOP-8
ТА = - 40 ... + 85 С
for all packages
ORDERING INFORMATION
Device
Operating
Temperature Range
Package
IN1363DT
IN1363D
IN1363MDT
ТА = - 40 ... + 85 С
IN1363MD
Shipping
SOP-8
Tape & Reel
SOP-8
Tube
MSOP-8
Tape & Reel
MSOP-8
Tube
DESCRIPTION
Microcircuit IN1363 is essentially the complete binary-decimal digital watch with calendar, alarm, timer and
possesses low power consumption. Addresses and data are transferred in series via the double wire bidirectional bus. The microcircuit is intended for count of real time in hours, minutes and seconds, count of
week days, date, month and year. The last day of the month is automatically adjusted for the months with
fewer, than 31 days, including correction for the leap year. The watch functions in the 24 hour mode. The
microcircuit IN1363 has the built-in power control circuit, which determines the power level < 1V and forms
the bit, signaling, that information about the real time may not be correct.
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Aug 2012, ver.05
IN1363
PINS DESCRIPTION
Pin Number
Symbol
Description
01
OSCI
Pin for connection of the quartz resonator
02
OSCO
Pin for connection of the quartz resonator
03
INT
Interruption output
04
VSS
Common pin
05
SDA
Input / Output of data
06
SCL
Synchrosignal input
07
CLKOUT
Frequency divider output
08
VDD
Supply source pin
BLOCK DIAGRAM
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Aug 2012, ver.05
IN1363
ASOLUTE MAXIMUM RATING
Limit and limit permissible operating modes of the microcircuit IN1363 are listed in the table
Characteristics
Limit Permissible
Symbol
Limit
Unit
Min
Max
Min
Max
Supply voltage
VDD
1.0
5.5
–0.5
6.5
V
Dissipated power
Ptot
-
-
-
300
mWt
Input voltage SCL, SDA, OSCI
VI
0
5.5
–0.5
6.5
V
Output voltage CLKOUT,INT
VO
0
5.5
–0.5
6.5
V
Direct input or output current via any
pin
IIO
-
-
–10
10
mА
All voltages are listed relative to ground. Under influence of the limit mode serviceability of the microcircuits
is not guaranteed. After plotting the limit mode serviceability is guaranteed in the limit permissible mode.
* Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the
device.
These are stress ratings only and functional operation of the device at these or any other conditions beyond
those indicated under “recommended operating conditions” is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Application
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Aug 2012, ver.05
IN1363
ELECTRICAL CHARACTERISTICS
(ТА = –40...+ 85С, VCC = 4,5 – 5,5 V)
Characteristics
Symbol
Test Condition
Min
Max
VDD
I2C bus –active;
FSCL = 400 kHz
1.8
5.5
in the non-active mode
1.0
5.5
Supply voltage
Note
Unit
V
1,2
Input leakage current
ILI
VIN =VDD; VIN =VSS
-
1
uА
Output leakage current
ILO
VOUT =VDD; VOUT =VSS
-
1
uА
Consumption current
IDD1
CLKOUT–off, FSCL =400
kHz
-
800
uА
CLKOUT–off, FSCL =100
kHz
-
200
CLKOUT–off, FSCL =0
kHz, VDD=5V
-
0.55
1,2
CLKOUT–off, FSCL =0
kHz, VDD=2V
-
0.45
1,2
Low level input voltage
VIL
VSS
0.3VDD
V
High level input voltage
VIH
0.7VDD
VDD
V
Low level output current at pin
CLKOUT
IOL1
VOL = 0.4 V, VDD =5 V
1
-
High level output current at pin
CLKOUT
IOH1
VOH = 4.6 V, VDD =5 V
1
-
Low level output current at pin
INT
IOL2
VOL = 0.4 V, VDD =5 V
1
-
Low level output current at pin
SDA
IOL3
VOL = 0.4 V, VDD =5 V
3
-
Supply low level, detected by
the circuit
VLOW
1
mА
mА
mА
mА
1
Note
o
1 Ta=(25 ± 5) C
2 Parameters of the quartz oscillator: fOSC=32.768 kHz, RS≤40 kOhm, CL=8 пF
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Aug 2012, ver.05
V
IN1363
DYNAMIC CHARACTERISTICS
(ТА = –40...+ 85С, VCC = 4,5 – 5,5 V are listed in the table)
Characteristics
Symbol
Test Condition
Min
Max
Unit
Cycle frequency SCL
fSCL
–
0
400
kHz
Time of bus vacant condition between the
conditions STOP and START
tBUF
–
4,7
–
us
1)
Hold time (repeated) of the condition START
tHD:STA
–
0,6
–
us
Low condition duration of the cycle pulse SCL
tLOW
–
1,3
–
us
High condition duration of the cycle pulse SCL
tHIGH
–
0,6
–
us
Presetting time for the repeated condition
START
tSU:STA
–
0,6
–
us
tHD:DAT
–
0
–
us
tSU:DAT
–
100
–
ns
Rise time for signals SDA and SCL
tR
–
–
300
ns
Drop time for signals SDA and SCL
tF
–
–
300
ns
tSU:STO
–
0,6
–
us
Total capacitance load on each bus line
CB
–
–
400
pF
Capacity input/output
CI/O
–
10
10
pF
Load capacitance of the quartz resonator
СLX
–
12,5
12,5
pF
2)
Data hold time
Data presetting time
Presetting time for the condition
STOP
1) After this time interval the first cycle signal is formed;
2) The device should internally ensure the hold time, at least, 300 nsec for the signal SDA (relative to VIHMIN
of the signal SCL) in order to overlap the indeterminacy area of the signal SCL drop front
Maximum value tHD:DAT should be definite in that case, if the device does not increase duration of the
low condition (tLOW ) of the signal SCL
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IN1363
TIMING DIAGRAMM
OPERATION DESCRIPTION
IN1363 operates as the «slave» device on the serial bus. For access to it expedient to set the condition
START and transfer after the register address the device identification code.
The next registers can be address in series till the condition STOP is preset. With V CC below 1,8 V, access
granting to the device by the serial interface is not guaranteed.
The current time is counted with the supply voltage 1 ÷ 5,5 V. When the supply level becomes lower, than 1V,
the bit VL=1 is formed, signaling, that the information about the current time may be incorrect.
DESCRIPTION OF SIGNALS
VDD– Positive supply. VDD – input from +1 till +5 V. With supply < 1,8 V access to the interface circuit is not
guaranteed.
INT – interrupt output. Interruption condition is formed with coincidence of the current time with the alarm
settings, or with attainment of the condition «0» of the timer countdown. Interruption, formed from the alarm,
forms the continuous signal, and from the timer can be both continuous and pulse one.
SCL (Serial Clock Input ) – SCL is used for synchronization of the data transfer by the serial interface.
SDA (Serial Data I/O) – SDA is input/output for the double wire serial interface. Output SDA is the open drain,
for which the external load resistor is required to be connected.
CLKOUT (Former output of the orthogonal signal) – For output activation the bit FE is preset to “1”. CLKOUT
generates the orthogonal signal of four different frequencies (1 Hz, 32 Hz, 1 kHz, 32 kHz). Output CLKOUT
is essentially the open drain, for which the external load resistor is required to be connected.
OSCI, OSCO – connection of the standard quartz resonator for the frequency 32,768 kHz. Capacitance load
of the internal oscillator for the quartz resonator is equal to 12pF. IN1363 can operate from the external
oscillator with the frequency 32,768 kHz. With this configuration the output OSCI is connected to the signal
external oscillator, and OSCO is left unconnected.
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IN1363
WATCH AND CALENDAR
Acquisition of information on time and date is performed by means of reading the appropriate register bytes.
Presetting and time and calendar initialization is performed by means of the appropriate bytes. Information,
contained in the time, calendar and alarm registers, is essentially the binary-decimal code. Bit 7 of register 2
is essentially the indication bit of the supply level decrease. < 1V (VL). When this bit = “1” , this signifies, that
the supply voltage was below the norm, and the information on the current time may be unreliable.
When switching power supply on, all register bits are preset to "0", with the exception of bits FE, VL, TD1,
TD0, TESTC and AE, which are preset to "1".
When applying the signal “START” on the double wire bus, the current time transfer occurs from the counters
to the auxiliary set of registers. The data on time are read out from these auxiliary registers, while the watch
continue to operate. This eliminates the necessity in the repeated reading in case of updating the basic
registers in the access process.
REGISTERS RTC IN1363
Data
Address
Registers / Range
D7
D6
D5
D4
D3
D2
D1
D0
00H
TEST1
0
STOP
0
TESTC
0
0
0
Control 1
01H
0
0
0
TI/TP
AF
TF
AIE
TIE
Control 2
02H
VL
Tens of seconds
Units of seconds
Seconds
00 – 59
03H
х
Tens of minutes
Units of minutes
Minutes
00 – 59
04H
х
х
Tens of hours
Units of hours
Hours
00 – 23
05H
х
х
Tens of date
Units of date
Dates
01 – 31
06H
х
х
х
х
Day of week
0–6
07H
С
х
х
10 М.
Units of month
Century / month
0-1/01-12
Units of years
Year
00 – 99
Units of minutes
Minute alarm
00 – 59
08H
х
Tens of years
09H
AE
0AH
AE
х
Tens of hours
Units of hours
Hour alarm
00 – 23
0BH
AE
х
Tens of date
Units of date
Date alarm
01 – 31
0CH
AE
х
х
х
х
Weekday alarm
0–6
0DH
FE
х
х
х
х
х
FD1
FD0
Control of CLKOUT
0EH
TE
х
х
х
х
х
TD1
TD0
Control of timer
0FH
Tens of minutes
Day of week
Day of week
Value of timer
Timer
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IN1363
CONTROL REGISTERS
Control Register 1
Address 00H : Control / Status 1 register bits
Bit
Symbol
7
TEST1
6
0
5
STOP
4
0
3
TESTC
2
0
1
0
0
0
TEST1 (activation of test mode) – This bit, preset to logic “1”, activates the test mode, with logic “0” normal
functioning of the circuit.
STOP – This bit, preset to logic “1” in the test mode perform the zero setting of all dividers, with logic “0” –
normal functioning of the circuit.
TESTC (activation of the test mode) – This bit, preset to logic “1”, activates the test mode, with logic “0”
normal functioning of the circuit.
When the control register1 is programmed, The OSC generates.
Control Register 2
Address 01H : Control / Status 2 register bits
Bit
Symbol
7
0
6
0
5
0
4
TI/TP
3
AF
2
TF
1
AIE
0
TIE
TI/TP (formation of the pulse interruption signal at output INT) – This bit, preset to logic “0”, with appearance
of the timer flag TF at output INT forms the constant interruption signal of the low level. The bit, preset to
logic “1” at output INT, forms the interruption pulse signal (signal frequencies are listed in the table).
[1]
Period INT (sec).
Timer Input Frequency
(Hz)
N =1
[2]
N>1
4096
1/8192
1/4096
64
1/128
1/64
1
1/64
1/64
1/60
1/64
1/64
[1] TF and INT become active simultaneously.
[2] N – value, loaded to the timer register. Timer is stopped with N = 0.
AF (alarm flag) - bit, in logic “1” informs about interruption by actuation of the alarm, by means of software
the bit AF can be reset only.
TF (timer flag) - bit, in logic “1” informs about interruption by actuation of the timer, by the software means
the bit TF can be reset only.
AIE (activation of alarm) - bit, preset to logic “1”, activates operation of the alarm.
TIE (activation of timer) - bit, preset to logic “1”, activates operation of the alarm.
Read
Write
0
1
0
1
Alarm
Alarm
Alarm
Alarm
AF
flag inactive
flag inactive
flag inactive
flag inactive
0
1
0
1
8
TF
Timer flag inactive
Timer flag active
Timer flag is cleared
Timere flag remains unchanged
Aug 2012, ver.05
IN1363
Control Register CLKOUT.
Address 0DH : CLKOUT frequency register bits
Bit
Symbol
7
FE
6
х
5
х
4
х
3
х
2
х
1
FD1
0
FD0
FE (output activation CLKOUT) - This bit, preset to logic “1”, activates output CLKOUT. Frequency of the
output orthogonal signal is determined by the bits FD0 and FD1. The source clock for the timer is also
selected by the Timer Control register.
Other timer properties,e.g interrupt generation are controlled via the Control./ststus 2 register. For accurate
read back of the countdown value, the I2C- bus clock SCL must be operating at a frequency of at least twice
the selected timer clock.
FD1
FD0
Frequency CLKOUT
0
0
32,768 kHz
0
1
8,192 kHz
1
0
4,096 kHz
1
1
1 Hz
Timer Control Register
The Timer register is an 8 –bit binary countdown timer . It is enabled and disabled via the Timer control
register bit TE .
The source clock for the timer is also selected by theTimer control register. Other timer properties, e.g. interru
pt generation, are controlled via the Control/status 2 register. For accurate read back of the countdown value,
the i2c bus clock SCL must be operating at a frequency of at least twice the selected timer clock.
Address 0EH : Timer control register bits
Bit
Symbol
7
TE
6
х
5
х
4
х
3
х
2
х
1
TD1
0
TD0
TE (timer activation) - This bit, preset to logic “1”, activates the frequency application to the timer input from
the oscillator. The signal frequency is determined by bits TD0 and TD1.
ТD1
ТD0
Timer Input Frequency
0
0
4096 Hz
0
1
64 Hz
1
0
1 Hz
1
1
1 / 60 Hz
Address 0FH : Timer countdown value register bits
Bit
Symbol
7
6
5
4
3
2
1
0
Timer countdown value - This register holds the loaded countdown value ‘n’
n
Countdown period = -----------------------------Source clock frequency
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IN1363
Seconds, Minutes and Hours Register
Address 02H : Seconds / VL register bits
Bit
Symbol
7
VL
6
5
4
3
seconds
2
1
0
VL = 0 : reliable clock/calendar information is guaranteed
VL = 1 : reliable clock/calendar information is no longer guaranteed.
<seconds> These bits represent the current seconds value coded in BCD format; value = 00 to 59.
Address 03H : Minutes register bits
Bit
Symbol
<minutes>
7
х
6
5
4
3
minutes
2
1
0
These bits represent the current minutes value coded in BCD format; value = 00 to 59.
Address 04H : Hours register bits
Bit
Symbol
<hours>
7
-
6
-
5
4
3
2
1
0
hours
These bits represent the current hours value coded in BCD format; value = 00 to 23.
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IN1363
Days, weekdays,Months/Century and Years Register
Address 05H : Dates register bits
Bit
Symbol
7
-
6
-
5
4
3
2
1
0
2
1
Week day
0
2
Months
1
0
days
<days> These bits represent the current day value coded in BCD format; value=01to 31
Address 06H : Weekdays register bits
Bit
Symbol
7
-
6
-
5
-
4
-
3
-
<week days> These bits represent the current week day value 0 to 6
Address 07H : Century / Months registers bits
Bit
Symbol
<C>
7
C
6
-
5
-
4
3
Century bit.
C = 0 ; indicates the century is 20xx.
C = 1 : indicates the century is 19xx. ‘xx’ indicates the value held in the Years register;
This bit is toggled when the years register overflow from 99 to 00.
<months> These bits represent the current month value coded in BCD format value 0 to12
January
February
March
April
May
June
July
August
September
October
November
December
B4
0
0
0
0
0
0
0
0
0
1
1
1
B3
0
0
0
0
0
0
0
1
1
0
0
0
B2
0
0
0
1
1
1
1
0
0
0
0
0
B1
0
1
1
0
0
1
1
0
0
0
0
1
B0
1
0
1
0
1
0
1
0
1
0
1
0
Address 08H : Years register bits
Bit
Symbol
7
6
5
4
3
2
1
0
years
<years> This register represent the current year value coded in BCD format :00 to 99
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IN1363
Alarm Registers
Address 09H : Minute alarm register bits
Bit
Symbol
7
AE
6
5
4
3
Minute alarm
2
1
0
AE - AE = 0; minute alarm is enabled.
AE = 1; minute alarm is disabled.
<minute alarm>
These bits represents the Minute alarm information coded in BCD format;
value = 00 to 59.
Address 0AH : Hour alarm register bits
Bit
Symbol
7
AE
6
-
5
4
3
2
1
0
hour alarm
AE - AE = 0; hour alarm is enabled.
AE = 1; hour alarm is disabled.
<hour alarm>
These bits represents the hour alarm information coded in BCD format; value = 00 to 23.
Address 0BH : Day alarm register bits
Bit
Symbol
7
AE
6
-
5
4
3
2
1
0
day alarm
AE - AE = 0; day alarm is enabled.
AE = 1; day alarm is disabled.
<day alarm>
These bits represents the day alarm information coded in BCD format; value = 01 to 31
Address 0CH : Weekday alarm register bits
Bit
Symbol
7
AE
6
-
5
-
4
-
3
-
2
1
weekday alarm
0
AE - AE = 0; weekday alarm is enabled.
AE = 1; weekday alarm is disabled.
< weekday alarm>
These bits represents the weekday alarm information coded in BCD format;
value = 0 to 6
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IN1363
2-WIRE SERIAL DATA BUS
IN1363 supports the bi-directional double wire bus and the data transfer protocol. The bus can be controlled
by the “master” device, which generates the cycle signal (SCL), controls access to the bus, generates the
conditions START and STOP. Typical bus configuration with the double wire is indicated in the Figure.
Data transfer can be started only when the bus is not busy. In the process of the data transfer, the data line
should remain stable, while the cycle signal line is in the HIGH condition. Alterations of the data line
conditions at that moment, when the cycle line is in the high condition, will be regarded as the control signals.
In compliance with this the following conditions are determined:
Bus is not busy: both lines of data and cycle signal are in the HIGH condition.
Data transfer start: Alteration of the data line condition during transition from HIGH to LOW, while the cycle
line is in the HIGH condition, is determined as the status START.
Data transfer stop: Alteration of the data line condition during transition from LOW to HIGH, while the cycle
line is in the HIGH condition, is determined as status STOP.
Valid data: Condition of the data line corresponds to the valid data, when after the condition START the data
line is stable at the time of the HIGH status of the cycle signal. The data on the line should be altered at the
time of the LOW condition of the cycle signal. One cycle pulse per one data bit.
Each data transfer starts with arrival of the status START and ceases with arrival of the status STOP.
Number of data bytes, transferred between the statuses START and STOP, is not limited and is determined
by the «master» device. Information is transferred byte by byte, and each reception is confirmed by the ninth
bit.
Reception confirmation: Each receiving device, when being addressed, generates the reception confirmation
bit after reception of each byte. The «master» device should generate the additional cycle pulses, which are
set in compliance with the confirmation bits.
If the reception confirmation signal is in the high condition, then upon arrival of the confirmation cycle signal,
confirming reception, the device should switch the SDA line to the low condition. Of course, the presetting
time and the hold time should be taken into consideration.
The «master» device should signal about termination of the data transfer to the «slave» device, stopping
generation of the confirmation bit, while receiving from the «slave» cycle pulse of the reception confirmation.
In this case, the «slave» cycle pulse should switch the data line to the low condition for the «master» cycle
pulse to generate the condition STOP.
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IN1363
Data transfer by the serial double wire bus
Depending on the status of the bit
R / W , two types of transfer are possible:
1. Data are transferred from the «master» transmitter to the «slave» receiver. The first byte, transferred by
the «master» one, is the address of the «slave» one. Then follows sequence of the data bytes. The «slave»
one returns the reception confirmation bits after each received byte. Order of the data transfer: the first one
is the most senior digit (MSB).
2. Data are transferred from the «slave» transmitter to the «master» receiver. The first byte (address of
«slave») is transferred to the «master» one. Then the «master» returns the confirmation bit. This follows after
the «slave» one of the data sequence. The «master» one returns the reception confirmation bit after each
received byte, with exception of the last byte. After reception of the last byte the reception confirmation bit
does not return.
The «master» device generates all cycle pulse and the conditions START and STOP. Transmission
completes with emergence of the condition STOP or the repeated emergence of the condition START. As
the repeated condition START is the beginning of the next serial transmission, then the bus is not vacated.
Data transfer order: the first one is the most senior digit (MSB).
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IN1363
IC IN1363 CAN WORK IN 2 NEXT MODE
Mode of the «slave» receiver (writing mode of IN1363)
Serial data and cycles are received via SDA and SCL appropriately. After transfer of each byte the
confirming bit is transferred.
Conditions START and STOP are understood as the start and end of the serial transmission. Address
recognition is performed by the hardware means after reception of the address of the «slave» one and the
direction bit.
The address byte is the first byte, received after emergence of the condition START, generated by the
«master» one. Address byte contains seven address bits IN1363, equal to 1010001, accompanied by the
direction bit ( R / W ), which is equal to 0 for writing. After reception and decoding the address IN1363
provides confirmation on the line SDA. After confirmation by IN1363 of the «slave» address and the write bit,
the «master» one transmits the register address of IN1363.
Thus, the register indicator will be set in IN1363. Then the «master» one will start to transfer each data byte
with the subsequent confirmation reception of each byte receipt. Upon completion of writing the «master»
one will form the condition STOP, for termination of the data transfer.
Data writing – mode of the «slave» receiver
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IN1363
Mode of the «slave» transmitter (read-out mode from IN1363)
The first byte is accepted and is processed as in the mode of the «slave» receiver. But in this mode the
direction bit will indicate, that the transmission direction is altered. The serial data are transferred by IN1363
by means of SDA, the cycle pulses – by means of SCL. The statuses of START and STOP are recognized
as the start and end of transmission in series. The address byte is the first byte, received after emergence of
the status START, generated by the «slave» one.
The address byte contains the seven address bits DS1363, equal to 1010001, accompanied with the
direction bit ( R / W ), which is equal to 1 for reading. After reception and decoding the address byte IN1363
accepts confirmation from the line SDA.
Then IN1363 starts to transmit the data from the address, to which the register indicator indicates. If the
register indicator is not written prior to initialization of the writing mode, then the first read address will be the
last address, stored in the register indicator. IN1363 should transmit the bit of «non-confirmation», in order to
complete reading.
acknowledgement
from slave
S
SLAVE_ADDRESS
0 A
acknowledgement
from slave
WORD_ADDRESS
A
S
acknowledgement
from slave
SLAVE_ADDRESS 1 A
at this moment mastertransmitter becomes
master receiver and
IN1363 slave-receiver
becomes slave-transmitter
R/W
acknowledgement
from master
A
DATA
n byte
R/W
auto increment
memory word address
no acknowledgement
from master
1
DATA
last byte
auto increment
memory word
address
Master reads after setting word address (write word address ; read data )
acknowledgement
from slave
S
SLAVE_ADDRESS
DATA
R/W
no acknowledgement
from master
acknowledgement
from master
A
n byte
S:START
A:ACKNOWLEDGED RECEIVING
P:STOP
A:RECEIVING IS NOT ACKNOWLEDGED
DATA
1
P
last byte
auto increment
word address
auto increment
word address
Master reads slave immediately after first byte ( read mode )
Data reading – mode of «slave» transmitter
16
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Aug 2012, ver.05
IN1363
PACKAGE DIMENSION
SOP 8 (MS-012AA)
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IN1363
MSOP-8
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Aug 2012, ver.05
IN1363
TEST FIXTURE
for IN1363 & IN1307
Application Note
IK SEMICON
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Aug 2012, ver.05
IN1363
1. TEST FIXTURE OVERVIEW
In order to supply convenient method for RTC Test, IK-SEMICON prepared test fixture. It’s controlled
by Silabs MCU C8051F410, user can RTC test by using this fixture.
1.1. Installing the hardware
IN1363/IN1307 is an IC compatible real time clock (RTC).
As an application example, it demonstrates how to setup the RTC.
This application note explain how to set the register value into a date and time value that can be put
in the following form [YY]:[MM]:[DD]:[HH]:[MM]:[SS].
1.2. Major Components
Fig 1. Test board Schematic
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IN1363
Polarity +
Adapter (Main Power DC12V)
Polarity -
IL1307 Backup
Battery
DC3V 2400mA
Socket
IN1363 Backup
Battery
initial switch
Socket and
PCB should be
aligned in the
same direction.
Programming
writing Connector
IL1307 zone
RS232C
Fig 2 Top view of test fixture
F
H
IN1307
A
B
C
I
IN1363
32.768KHz
LED
TP11
TP12
TP13
TP14
TP15
TP16
TP10
TP9
D
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
SiLabs
C8051F410
E
IN1363
IN1363 SOCKET
SOCKET
32.768KHz
IN1307
IN1307 SOCKET
SOCKET
MAX3223E
F
RS232C
Fig 3 Layout of test fixture.
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IN1363
1.3. Basic Specification
A. 12V DC-JACK : Power Terminal
This power terminal normally is connected to the 12V power supply.
B. Init Switch
This switch initialize time to 23
July 2012, current time to 14:03:02(IN1363).
C. LED
This LED blinking every 1 seconds. if there is a power on the test fixture.
D. Test Point
In/Output pin of the MCU is connected.
If need the user, use as the test pin.
E. Debugger Connector
This test program exchanges with PC(Personal Computer) through this debugger connector.
F. RS232C Female Connector
User can see the test time through this connector.
G. 32.768KHz
Connection of the standard quartz resonator for the frequency 32.768KHz. IN1363 can operate from
external oscillator with the frequency 32.768KHz
Note : To oscillation the 32.768KHz , Reset to the bit TEST1
H. IN1307_BAT
If you test the IN1307,Connect Battery on the IN1307_BAT.
I. IN1363_BAT
If you test the IN1363, Connect Battery on the IN1363_BAT
Note: Although the power eliminate, the Real Time Clock is working if the battery is connected on the
IN1307/IN1363_BAT
J. IN1363_SOCKET
To test of IN1363 RTC, it should select IN1363_SOCKET.
K. IN1307_SOCKET
To test of IN1307 RTC, it should select IN1307_SOCKET.
Note: To avoid any confusion by program selector, only one IC should be selected by socket.
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2. REAL TIME CLOCK PROGRAM
2.1. Flow Chart
Power ON : IN1363
Read data
: Address 0x00
No
(READ data & 0x80) == 0
Yes
DTE : Initialize by Memory Nodata
DTE : Continue Start at 1363
Yes
IN1363 Initialize
Write Data
* Bit TEST1 = 0
ACK received
No
12[YY]:07[MM]:23[DD]:14[HH]:03[MM]:02[SS]
Yes
DTE : I2C Error No Ack
Read data
:Address
from 0x02 to 0x8
IN1363 Initialize
Write Data
ACK received
No
TEST1 bit = 0;
Yes
No
DTE : 9600bps
RTC DISPLAY
Address, Data
0x02, 0x02
DTE : RTC No ACK in READ
Address, Data
0x03, 0x03
Address, Data
0x04, 0x14
SW Press
Yes
Address, Data
0x05, 0x23
DTE : Initialize by SW press
Address, Data
0x07, 0x07
Yes
IN1363 Initialize
Write Data
Address, Data
0x08, 0x12
Fig3. Flow Chart for IN1363
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IN1363
Power ON : IN1307
Read data
: Address 0x00
No
(READ data & 0x80) == 0
Yes
DTE : Initialize by Memory Nodata
DTE : Continue Start at 1307
Yes
IN1307 Initialize
Write Data
* Bit CH = 0
12[YY]:06[MM]:15[DD]:5[DAY]:13[HH]:10[MM]:5[SS]
ACK received
No
Yes
DTE : I2C Error No Ack
Read data
:Address
from 0x00 to 0x06
IN1307 Initialize Write Data
ACK received
No
CH bit = 0;
Yes
No
DTE : 9600bps
RTC DISPLAY
Address, Data
0x00, 0x05
DTE : RTC No ACK in READ
Address, Data
0x01, 0x10
Address, Data
0x02, 0x13
SW Press
Address, Data
0x03, 0x05
Yes
Address, Data
0x04, 0x15
DTE : Initialize by SW press
Yes
IN1307 Initialize
Write Data
Address, Data
0x05, 0x06
Address, Data
0x06, 0x12
Address, Data
0x07, 0x00
Fig4. Flow Chart for IN1307
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IN1363
2.2. Register Set Up for IN1363
2.2.1. Initialization Register Setting Up
It is necessary to enable the generation (bit TEST1 = 0) when setting the initial configurations..
Register Address
Register Name
Initialize Write Data
0x00H
Control/Status 1
0x00
0x01H
Control/Status 2
0x00
0x0DH
CLKPUT control
-
0x0EH
Timer Control
-
0x0FH
Timer
-
Contents
TEST1 bit = 0 (normal mode)
STOP bit = 0 (RTC source clock)
TESTC bit = 0 (normal op)
AIE bit = 0 (Alarm int disabled)
TIE bit = 0 (Timer int disabled)
2.2.2 Timer Register Setting Up
Register Address
Register Name
Initialize Write Data
0x02H
Seconds
0x02
0x03H
Minutes
0x03
0x04H
Hours
0x14
0x05H
Dates
0x23
0x06H
Day of week
-
0x07H
Century/month
0x07
0x08H
Year
0x12
0x09H
Minute alarm
-
0x0AH
Hour alarm
-
0x0BH
Date alarm
-
0x0CH
Weekday alarm
Contents
Sunday=0,Monday=1,Tuesday=2,
Wednesday=3,..., Saturday=6
Bit7 ‘C’ of the months/century register
indicates century
for year 19xx (bit7=1), and year 20xx
(bit7=0).
For example, we want to set the date for 23 July 2012, current time to 12:03:02, and then we need to
call.
1.
2.
3.
4.
5.
6.
Seconds setup
Minutes setup :
Hours setup :
Dates setup :
Month setup :
Year setup
:
: rtc_write( SECONDS, 0x02);
rtc_write( MINUTES, 0x03);
rtc_write( HOURS,
0x14);
rtc_write( DATES,
0x23);
rtc_write( MONTH, 0x07);
rtc_write( YEAR,
0x12);
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IN1363
2.3 Register Set Up for IN1307
2.3.1. Initialization Register Setting Up
It is necessary to enable the generation (bit CH = 0) when setting the initial configurations..
Register
Address
0x00H.Bit8
Register Name
Initialize Write Data
Contents
Control/Status 1
0x00
CH bit = 0 (normal mode)
Initialize Write Data
Contents
2.3.2 Timer Register Setting Up
Register
Address
0x00H
Register Name
Seconds
0x05
0x01H
Minutes
0x10
0x02H
Hours
0x13
0x03H
Day
0x05
0x04H
Date
0x15
0x05H
Month
0x06
0x06H
Year
0x12
0x07H
Control
Range 1-7
For example, we want to set the date for 23 June 2012, current time to 13:10:05, and then we need
to call.
1.
2.
3.
4.
5.
6.
7.
Seconds setup
Minutes setup :
Hours setup :
Day setup
:
Dates setup :
Month setup :
Year setup
:
: rtc_write( 0x00, 0x05);
rtc_write( 0x01, 0x10);
rtc_write( 0x02, 0x13);
rtc_write( 0x03, 0x05);
rtc_write( 0x04, 0x15);
rtc_write( 0x05, 0x06);
rtc_write (0x06 , 0x12);
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IN1363
2.4 Hyper Terminal Configuration
1.
2.
3.
4.
5.
Bits per second : 9600 BPS
Data bit : 8 bit
Parity bit : None
Stop bits : 1 bit
Flow Control : None
Fig5. Example test program for IN1363
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IN1363
Run the Serial terminal and make sure the baud rate is set correctly at 9600bps
Fig6. IN1363 RTC Data on Serial Terminal
Fig7. IN1307 RTC Data on Serial Terminal
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IN1363
3.Example Source for RTC
This documentation shows an example of a main function to setup and read/write data.
If you request example source code, we can provide source codes.
3.1. Read Current Time from IN1363 & IN1307
Slave Address of IN1363 = 0xA2
Slave Address of IN1307 = 0xD0;
3.2.Write Set Time for IN1363 & IN1307
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IN1363
3.3. I2C Example Source for IN1363 & IN1307
#ifdef IN1363
sbit SCL
sbit SDA
#endif
= P1^7;
= P1^6; //
#ifdef IN1307
sbit SDA
sbit SCL
#endif
= P0^2;
= P0^1;
void i2c_start(void)
// START condition
{
SDA = HIGH;
DelayTimeLoop();
SCL = HIGH;
DelayTimeLoop();
SDA = LOW;
DelayTimeLoop();
SCL = LOW;
DelayTimeLoop();
}
void i2c_stop(void)
// STOP condition
{
SCL = HIGH;
DelayTimeLoop();
SDA = HIGH;
DelayTimeLoop();
}
/* Clock pulse generation. The function returns data or acknowledgment
unsigned char i2c_clock(void)//bit i2c_clock(void)
{
bit level;
// state of SDA line
SCL = 1;
DelayTimeLoop();
while (!SCL);
// if a pulse was stretched
DelayTimeLoop();
level = SDA;
DelayTimeLoop();
SCL = 0;
return (level);
}
bit */
/* Writing a byte to a slave, with most significant bit first. The function returns acknowledgment
bit.*/
unsigned char i2c_write(unsigned char byte)
{
unsigned char mask = 0x80;
unsigned char aaa;
while (mask) {
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IN1363
if (byte & mask)
SDA = 1;
else
SDA = 0;
i2c_clock();
mask >>= 1;
}
aaa = i2c_clock();
return (aaa);
}
/* Reading byte from a slave, with most significant bit first. The parameter indicates, whether to
acknowledge (1) or not (0) */
unsigned char i2c_read(unsigned char acknowledgment)
{
uchar mask = 0x80, byte = 0x00;
while (mask) {
if (i2c_clock())
byte |= mask;
mask >>= 1; /* next bit to receive */
}
if (acknowledgment) {
SDA = 0;
i2c_clock();
SDA = 1;
}
else {
SDA = 1;
i2c_clock();
}
return (byte);
}
unsigned char rtc_read_7_byte(unsigned char addr)
{
unsigned char status , i;
i2c_start();
if (!i2c_write(0xA2 )){//0xA2 is Slave Address for IN1363, 0xD2 is for IN1307
DelayTimeLoop();
if (!i2c_write(addr)){
i2c_start();
if (!i2c_write(0xA2 | 0x01)){ IN1307’s slave address is 0xD2
for(i=0;i<6;i++){
Receive_Data[i] = i2c_read(1);
}
Receive_Data[6] = i2c_read(0);
}
else {
status = 1;
}
}
else{
status = 1;
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}
}
else
status = 1;
i2c_stop();
return(status);
}
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IN1363
4. Test Procedure for RTC
4.1. Test Procedure for IN1363
1.
2.
3.
4.
5.
6.
7.
8.
9.
Make sure that test fixture is power off.
Place IN1363 on IN1363_SOCKET of test fixture.
Connect the Battery on IN1363_BAT.
Run the Serial terminal and make sure the baud rate is set correctly at 9600bps
After turning on the power of test fixture, identify whether Green LED of Status Indic
ator is flickering. If that’s flickering every 1S, it indicates IN1363 working . Method fo
r the program is refer to the Chapter 2.
Data is displayed in Serial Terminal window like to Fig6. refer to Fig6
And then test fixture is power off.
Wait for a period of time ( two hours, 10 minutes, etc .).
Turn the test fixture on again, and check the time. the amount time as power off is p
assed .
4.2. Test Procedure for IN1307
1.
2.
3.
4.
5.
6.
7.
8.
9.
Make sure that test fixture is power off.
Place IN1363 on IN1307_SOCKET of test fixture.
Connect the Battery on IN1307_BAT.
Run the Serial terminal and make sure the baud rate is set correctly at 9600bps
After turning on the power of test fixture, identify whether Green LED of Status Indic
ator is flickering. If that’s flickering every 1S, it indicates IN1307 working . Method fo
r the program is refer to the Chapter 2.
Data is displayed in Serial Terminal window like to Fig7. refer to Fig7
And then test fixture is power off.
Wait for a period of time ( two hours, 10 minutes, etc .).
Turn the test fixture on again, and check the time. the amount time as power off is p
assed .
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