bq24070
bq24071
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SLUS694B – MARCH 2006 – REVISED AUGUST 2006
SINGLE-CHIP LI-ION CHARGE AND SYSTEM POWER-PATH MANAGEMENT IC
FEATURES
•
•
•
•
•
•
•
•
•
•
•
DESCRIPTION
Small 3,5 mm × 4,5 mm QFN Package
Designed for Single-Cell Li-Ion- or
Li-Polymer-Based Portable Applications
Integrated Dynamic Power-Path Management
(DPPM) Feature Allowing the AC Adapter to
Simultaneously Power the System and
Charge the Battery
Power Supplement Mode Allows Battery to
Supplement the AC Input Current
Autonomous Power Source Selection (AC
Adapter or BAT)
Supports Up to 2-A Total Current
Thermal Regulation for Charge Control
Charge Status Outputs for LED or System
Interface Indicates Charge and Fault
Conditions
Reverse Current, Short-Circuit, and Thermal
Protection
Power Good Status Outputs
4.4-V and 6.0-V Options for System Output
Regulation Voltage
The bq24070 and bq24071 are highly integrated
Li-ion linear charger and system power-path
management devices targeted at space-limited
portable applications. The bq24070/1 offer DC
supply (AC adapter) power-path management with
autonomous power-source selection, power FETs
and current sensors, high-accuracy current and
voltage regulation, charge status, and charge
termination, in a single monolithic device.
The
bq24070/1
power
the
system
while
independently charging the battery. This feature
reduces the charge and discharge cycles on the
battery, allows for proper charge termination and
allows the system to run with an absent or defective
battery pack. This feature also allows for the system
to instantaneously turn on from an external power
source in the case of a deeply discharged battery
pack. The IC design is focused on supplying
continuous power to the system when available from
the AC adapter or battery sources.
APPLICATIONS
•
•
•
•
Smart Phones and PDA
MP3 Players
Digital Cameras and Handheld Devices
Internet Appliances
POWER FLOW DIAGRAM (1)
AC Adapter
(2)
IN
OUT
VDC
GND
System
Q1
40 mΩ
BAT
PACK+
+
PACK−
bq24070/1
Q2
UDG−04082
(1)
See Figure 2 and functional block diagram for more detailed feature information.
(2)
P-FET back gate body diodes are disconnected to prevent body diode conduction.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated
bq24070
bq24071
www.ti.com
SLUS694B – MARCH 2006 – REVISED AUGUST 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOSFET gates.
DESCRIPTION (CONTINUED)
The MODE pin selects the priority of the input sources. If an input source is not available, then the battery is
selected as the source. With the MODE pin high, the bq24070/1 attempts to charge from the input at the charge
rate set by ISET1 pin. With the MODE pin low, the bq24070/1 defaults to USB charging at the charge rate. This
feature allows the use of a single connector (mini-USB cable), where the host programs the MODE pin
according to the source that is connected (AC adaptor or USB port). Table 1 summarizes the MODE pin
function.
Table 1. Power Source Selection Function Summary
MODE STATE
AC
ADAPTER
MAXIMUM
CHARGE RATE (1)
Low
Present
ISET2
USB
Enabled
Absent
N/A
Battery
Disabled
Present
ISET1
AC
Disabled
Absent
N/A
Battery
Disabled
High
(1)
SYSTEM
POWER
SOURCE
USB BOOT-UP
FEATURE
Battery charge rate is always set by ISET1, but may be reduced by a limited input source (ISET2 USB mode) and IOUT system load.
ORDERING INFORMATION (1)
TA
–40°C to 125°C
(1)
(2)
(3)
(4)
2
BATTERY
VOLTAGE (V)
OUT PIN
PART
NUMBER (2) (3)
STATUS
PACKAGE
MARKING
4.2
Regulated to 4.4 V (4)
bq24070RHLR
Production
BRQ
4.2
Regulated to 4.4 V (4)
bq24070RHLT
Production
BRQ
4.2
Regulated to 6.0 V
bq24071RHLR
Production
BTR
4.2
Regulated to 6.0 V
bq24071RHLT
Production
BTR
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
The RHL package is available in the following options:
R - taped and reeled in quantities of 3,000 devices per reel.
T - taped and reeled in quantities of 250 devices per reel.
This product is RoHS compatible, including a lead concentration that does not exceed 0.1% of total product weight, and is suitable for
use in specified lead-free soldering processes. In addition, this product uses package materials that do not contain halogens, including
bromine (Br) or antimony (Sb) above 0.1% of total product weight.
If AC < VO(OUT-REG), the AC is connected to the OUT pin by a P-FET, (Q1).
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ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range (unless otherwise noted)
bq24070/1
Input voltage
Input voltage
IN (DC voltage wrt (with respect to) VSS)
–0.3 V to 18 V
BAT, CE, DPPM, PG, Mode, OUT, ISET1, ISET2, STAT1,
STAT2, TS, (all DC voltages wrt VSS)
–0.3 V to 7 V
VREF (DC voltage wrt VSS)
–0.3 V to VO(OUT) + 0.3 V
TMR
–0.3 V to VO + 0.3 V
Input current
3.5 A
OUT
Output current
4A
BAT (2)
Output sink current
–4 A to 3.5 A
PG, STAT1, STAT2,
1.5 mA
Storage temperature range, Tstg
–65°C to 150°C
Junction temperature range, TJ
–40°C to 150°C
Lead temperature (soldering, 10 seconds)
(1)
(2)
300°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to the network ground terminal unless otherwise noted.
Negative current is defined as current flowing into the BAT pin.
RECOMMENDED OPERATING CONDITIONS
(1)
VCC
Supply voltage (VIN)
IAC
Input current
TJ
Operating junction temperature range
(1)
MIN
MAX
4.35
16
UNIT
2
A
–40
125
°C
V
Verify that power dissipation and junction temperatures are within limits at maximum VCC .
DISSIPATION RATINGS
(1)
PACKAGE
TA ≤ 40°C
POWER RATING
DERATING FACTOR
TA > 40°C
θJA
20-pin RHL (1)
1.81 W
21 mW/°C
46.87 °C/W
This data is based on using the JEDEC High-K board and the exposed die pad is connected to a Cu pad on the board. This is
connected to the ground plane by a 2×3 via matrix.
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SLUS694B – MARCH 2006 – REVISED AUGUST 2006
ELECTRICAL CHARACTERISTICS
over junction temperature range (0°C ≤ TJ ≤ 125°C) and the recommended supply voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT BIAS CURRENTS
ICC(SPLY)
Active supply current, VCC
VVCC > VVCC(min)
1
2
ICC(SLP)
Sleep current (current into BAT
pin)
VIN < V(BAT)
2.6 V ≤ VI(BAT)≤ VO(BAT-REG),
Excludes load on OUT pin
2
5
ICC(IN-STDBY)
Input standby current
VI(AC) ≤ 6V, Total current into IN pin with
chip disabled, Excludes all loads,
CE=LOW, after t(CE-HOLDOFF) delay
ICC(BAT-STDBY)
BAT standby current
Total current into BAT pin with input
present and chip disabled;
Excludes all loads, CE=LOW,
after t(CE-HOLDOFF) delay,
0°C ≤ TJ≤ 85°C
IIB(BAT)
Charge done current, BAT
Charge DONE, input supplying the load
mA
200
µA
45
65
1
5
OUT PIN-VOLTAGE REGULATION
VO(OUT-REG)
Output regulation
voltage
bq24070
VI(AC)≥ 4.4 V+VDO
4.4
4.5
bq24071
VI(AC)≥ 6.0 V+VDO
6.0
6.3
V
OUT PIN – DPPM REGULATION
V(DPPM-SET)
DPPM set point (1)
VDPPM-SET < VOUT
2.6
3.8
V
I(DPPM-SET)
DPPM current source
Input present
95
100
105
µA
SF
DPPM scale factor
V(DPPM-REG)= V(DPPM-SET) × SF
1.139
1.150
1.162
300
475
40
100
OUT PIN – FET (Q1, Q2) DROP-OUT VOLTAGE ®DS(on))
V(ACDO)
AC to OUT dropout voltage (2)
VI(AC)≥ VCC(min), Mode = High,
II(AC) = 1 A, (IO(OUT)+ IO(BAT)), or no input
V(BATDO)
BAT to OUT dropout voltage
(discharging)
VI
(BAT)≥
mV
3 V, Ii(BAT)= 1.0 A, VCC < Vi(BAT)
OUT PIN - BATTERY SUPPLEMENT MODE
VBSUP1
VBSUP2
Enter battery supplement mode
(battery supplements OUT
current in the presence of input
source
Exit battery supplement mode
VI(BAT)> 2 V
VI(OUT)
≤ VI(BAT)
– 60 mV
V
VI(OUT)
≥ VI(BAT)
– 20 mV
VI(BAT)> 2 V
OUT PIN - SHORT CIRCUIT
IOSH1
BAT to OUT short-circuit
recovery
Current source between BAT to OUT for
short-circuit recovery to
VI(OUT)≤ VI(BAT) –200 mV
RSHAC
AC to OUT short-circuit limit
VI(OUT) ≤ 1 V
10
mA
500
Ω
BAT PIN CHARGING – PRECHARGE
V(LOWV)
Precharge to fast-charge
transition threshold
Voltage on BAT
TDGL(F)
Deglitch time for fast-charge to
precharge transition (3)
tFALL = 100 ns, 10 mV overdrive,
VI(BAT) decreasing below threshold
IO(PRECHG)
Precharge range
1 V < VI(BAT) < V(LOWV), t < t(PRECHG),
IO(PRECHG) = (K(SET) × V(PRECHG))/ RSET
V(PRECHG)
Precharge set voltage
1 V < VI(BAT) < V(LOWV), t < t(PRECHG)
225
Vi (BAT) > V(LOWV), Mode = High
IOUT(BAT) = (K(SET) × V(SET) / RSET),
VI(OUT) > VO(OUT-REG) + V(DO-MAX)
100
2.9
3
3.1
22.5
10
V
ms
150
mA
250
275
mV
1000
1500
mA
BAT PIN CHARGING - CURRENT REGULATION
IO(BAT)
Battery charge current range
RPBAT
BAT to OUT pullup
(1)
(2)
(3)
(4)
4
(4)
Vi
(BAT)<
1V
1000
Ω
V(DPPM-SET) is scaled up by the scale factor for controlling the output voltage V(DPPM-REG).
VDO(max), dropout voltage is a function of the FET, RDS(on), and drain current. The dropout voltage increases proportionally to the
increase in current.
All deglitch periods are a function of the timer setting and is modified in DPPM or thermal regulation modes by the percentages that the
program current is reduced.
When input current remains below 2 A, the battery charging current may be raised until the thermal regulation limits the charge current.
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ELECTRICAL CHARACTERISTICS (continued)
over junction temperature range (0°C ≤ TJ ≤ 125°C) and the recommended supply voltage range (unless otherwise noted)
PARAMETER
V(SET)
Battery charge current set
voltage (5)
K(SET)
Charge current set factor, BAT
MIN
TYP
MAX
UNIT
Voltage on ISET1, VVCC≥ 4.35 V,
VI(OUT)- VI(BAT) > V(DO-MAX),
VI(BAT) > V(LOWV)
TEST CONDITIONS
2.47
2.50
2.53
V
100 mA ≤ IO(BAT) ≤ 1.5 A
375
425
450
10 mA ≤ IO(BAT) ≤ 100 mA (6)
300
450
600
USB MODE INPUT CURRENT LIMIT
I(USB)
USB input port current range
ISET2 = Low
80
ISET2 = High
400
90
100
mA
500
BAT PIN CHARGING VOLTAGE REGULATION, VO (BAT-REG) + V (DO-MAX) < VCC, ITERM < IBAT(OUT) ≤ 1 A
Battery charge voltage
VO(BAT-REG)
Battery charge voltage regulation
accuracy
4.2
TA = 25°C
V
–0.5%
0.5%
–1%
1%
10
150
CHARGE TERMINATION DETECTION
I(TERM)
Charge termination detection
range
VI(BAT) > V(RCH),
I(TERM) = (K(SET) × V(TERM))/ RSET
V(TERM)
Charge termination set voltage,
measured on ISET1
VI(BAT) > V(RCH) , Mode = High
230
250
270
VI(BAT) > V(RCH) , Mode = Low
95
100
130
TDGL(TERM)
Deglitch time for termination
detection
tFALL = 100 ns, 10 mV overdrive,
ICHG increasing above or decreasing
below threshold
22.5
mA
mV
ms
TEMPERATURE SENSE COMPARATORS
VLTF
High voltage threshold
Temp fault at V(TS) > VLTF
2.465
2.500
2.535
V
VHTF
Low voltage threshold
Temp fault at V(TS) < VHTF
0.485
0.500
0.515
V
ITS
Temperature sense current
source
94
100
106
µA
TDGL(TF)
Deglitch time for temperature
fault detection (7)
R(TMR) = 50 kΩ, VI(BAT) increasing or
decreasing above and below;
100-ns fall time, 10-mv overdrive
22.5
ms
BATTERY RECHARGE THRESHOLD
VRCH
Recharge threshold voltage
TDGL(RCH)
Deglitch time for recharge
detection (7)
VO(BAT-REG)
–0.075
R(TMR) = 50 kΩ, VI(BAT) increasing
or decreasing below threshold,
100-ns fall time, 10-mv overdrive
VO(BAT-REG)
–0.100
VO(BAT-REG)
–0.125
22.5
V
ms
STAT1, STAT2, AND PG, OPEN DRAIN (OD) OUTPUTS (8)
VOL
Low-level output saturation
voltage
ILKG
Input leakage current
IOL = 5 mA, An external pullup
resistor ≥ 1 K required.
1
0.25
V
5
µA
ISET2, CE INPUTS
VIL
Low-level input voltage
0
VIH
High-level input voltage
1.4
IIL
Low-level input current, CE
–1
IIH
High-level input current, CE
IIL
Low-level input current, ISET2
VISET2 = 0.4 V
IIH
High-level input current, ISET2
VISET2 = VCC
t(CE-HLDOFF)
Holdoff time, CE
CE going low only
VIL
Low-level input voltage
Falling Hi→Low; 280 K ± 10% applied
when low.
VIH
High-level input voltage
Input RMode sets external hysteresis
0.4
1
–20
V
µA
40
4
6
ms
MODE INPUT
(5)
(6)
(7)
(8)
0.975
VIL + .01
1
1.025
V
VIL + .024
V
For half-charge rate, V(SET) is 1.25 V ± 25 mV.
Specification is for monitoring charge current via the ISET1 pin during voltage regulation mode, not for a reduced fast-charge level.
All deglitch periods are a function of the timer setting and is modified in DPPM or thermal regulation modes by the percentages that the
program current is reduced.
See Charger Sleep mode for PG (VCC = VIN) specifications.
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ELECTRICAL CHARACTERISTICS (continued)
over junction temperature range (0°C ≤ TJ ≤ 125°C) and the recommended supply voltage range (unless otherwise noted)
PARAMETER
IIL
TEST CONDITIONS
Low-level input current, Mode
MIN
TYP
MAX
–1
UNIT
µA
TIMERS
K(TMR)
Timer set factor
R(TMR) (9)
External resistor limits
t(PRECHG)
Precharge timer
I(FAULT)
Timer fault recovery pullup from
OUT to BAT
t(CHG) = K(TMR) × R(TMR)
0.313
0.414
s/Ω
30
0.360
100
kΩ
0.09 × t(CHG)
0.10 × t(CHG) 0.11 × t(CHG)
1
s
kΩ
CHARGER SLEEP THRESHOLDS (PG THRESHOLDS, LOW → POWER GOOD)
V(SLPENT) (10)
V(SLPEXIT)
(10)
t(DEGL)
Sleep-mode entry threshold
V(UVLO)≤ VI(BAT)≤ VO(BAT-REG),
No t(BOOT-UP) delay
Sleep-mode exit threshold
V(UVLO)≤ VI(BAT)≤ VO(BAT-REG),
No t(BOOT-UP) delay
Deglitch time for sleep mode (11)
R(TMR) = 50 kΩ,
V(IN) decreasing below threshold, 100-ns
fall time, 10-mv overdrive
VVCC ≤
VI(BAT)
+125 mV
VVCC ≥
VI(BAT)
+190 mV
22.5
V
ms
START-UP CONTROL BOOT-UP
t(BOOT-UP)
Boot-up time
On the first application of input with
Mode Low
120
150
180
ms
50
µs
SWITCHING POWER SOURCE TIMING
tSW-BAT
Switching power source from
input to battery
When input applied. Measure from:
[PG: Lo → Hi to I(IN) > 5 mA],
I(OUT) = 100 mA,
RTRM = 50 K
THERMAL SHUTDOWN REGULATION (12)
T(SHTDWN)
TJ(REG)
Temperature trip
TJ (Q1 and Q3 only)
Thermal hysteresis
TJ (Q1 and Q3 only)
155
Temperature regulation limit
TJ (Q2)
115
Undervoltage lockout
Decreasing VCC
2.45
30
°C
135
UVLO
V(UVLO)
Hysteresis
2.50
27
2.65
V
mV
(9) To disable the safety timer and charge termination, tie TMR to the VREF pin.
(10) The IC is considered in sleep mode when IN is absent (PG = OPEN DRAIN).
(11) Does not declare sleep mode until after the deglitch time and implement the needed power transfer immediately according to the
switching specification.
(12) Reaching thermal regulation reduces the charging current. Battery supplement current is not restricted by either thermal regulation or
shutdown. Input power FETs turn off during thermal shutdown. The battery FET is only protected by a short-circuit limit which typically
does not cause a thermal shutdown (input FETs turning off) by itself.
6
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DEVICE INFORMATION
GND
VREF
bq24070/1RHL
RHL PACKAGE
(TOP VIEW)
GND
STAT1
2
STAT2
3
18
PG
IN
4
17
OUT
BA T
5
16
OUT
BA T
6
15
OUT
ISET2
7
14
TMR
MODE
8
13
DPPM
9 10
ISET1
CE
20 19
11 12
TS
VSS
1
TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
I/O
DESCRIPTION
IN
4
I
Charge input voltage
PG
18
O
Power-good status output (open-drain)
BAT
5, 6
I/O
Battery input and output.
CE
9
I
Chip enable input (active high)
DPPM
13
I
Dynamic power-path management set point (account for scale factor)
ISET1
10
I/O
ISET2
7
I
Charge current set point for USB port. (High = 500 mA, Low = 100 mA) See half-charge current mode
using ISET2.
OUT
Charge current set point and precharge and termination set point
15, 16, 17
O
Output terminal to the system
MODE
8
I
Power source selection input (Low for USB mode current limit)
STAT1
2
O
Charge status output 1 (open-drain)
STAT2
3
O
Charge status output 2 (open-drain)
TMR
14
I/O
Timer program input programmed by resistor. Disable safety timer and termination by tying TMR to VREF.
Temperature sense input
TS
12
I/O
GND
19, 20
I
Ground input
VREF
1
O
Internal reference signal
–
Ground input (the thermal pad on the underside of the package) There is an internal electrical connection
between the exposed thermal pad and VSS pin of the device. The exposed thermal pad must be
connected to the same potential as the VSS pin on the printed-circuit board. Do not use the thermal pad
as the primary ground input for the device. VSS pin must be connected to ground at all times.
VSS
11
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FUNCTIONAL BLOCK DIAGRAM
Short−Circuit Recovery
500 Ω
BAT
Short−Circuit
Recovery
100 mA /
500 mA
IN
VO(OUT)
OUT
Q1
1 kΩ
Fault
Recovery
3.3 V
VREF
10 mA
VSET
+
I(SNS)
VIO(AC)
AC Charge
Enable VI (SNS)
VO(OUT)
GND
Q2
VI(BAT)
BAT
+
VO(OUT−REG)
VI(ISET1)
ISET1
UVLO
VO(BAT−REG)
TMR
Oscillator
VI(BAT)
VI (OUT)
+
VO(BAT−REG)
VI(ISET1)
VO(OUT)
DPPM
+
DPPM
I(DPPM) Scaling
BAT
Charge
Enable
VSET
VDPPM
TJ
V(HTF)
+
Disable−
Sleep
+
200 mV
Suspend
Thermal
Shutdown
1V
+
I(TS)
TS
+
VO(OUT)
TJ(REG)
*
60 mV
VI(BAT)
+
+
1V
+
Fast Precharge
+
*
V(LTF)
280 kΩ
Power Source Selection
MODE
AC Charge Enable
CE
BAT Charge Enable
VO(BAT−REG)
Recharge
VBAT
*
Charge
Control
Timer
and
Display
Logic
Precharge
VBAT
500 mA/ 100 mA
Fast Precharge
1C − 500 mA
C/S − 100 mA
ISET2
*
PG
V(SET)
VI(ISET1)
Term
GND
*
STAT1
Sleep
VBAT
VIN
*
STAT2
VSS
*
8
Signal Deglitched
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FUNCTIONAL DESCRIPTIONS
CHARGE CONTROL
The bq24070/1 supports a precision Li-ion or Li-polymer charging system suitable for single-cell portable
devices. See a typical charge profile, application circuit, and an operational flow chart in Figure 1 through
Figure 3, respectively.
Pre-Conditioning
Phase
Current Regulation Phase
Voltage Regulation and Charge Termination Phase
Regulation
Voltage
Regulation
Current
Minimum
Charge
Voltage
Pre−
Conditioning
and Term
Detect
Charge
Voltage
Charge
Complete
Charge
Current
UDG−04087
Figure 1. Charge Profile
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FUNCTIONAL DESCRIPTIONS (continued)
bq24070/1
AC Adapter
VDC
GND
4
IN
VREF
1
OUT 15
10 µF
OUT 16
20 GND
14 TMR
RTMR
OUT 17
BAT
5
BAT
6
PACK+
STAT1
3
STAT2
19 GND
+
PACK −
TS 12
18 PG
DPPM 13
9
CE
ISET1 10
8
MODE
TEMP
RSET
RDPPM
VSS 11
Control and
Status Signals
UDG−04083
Figure 2. Typical Application Circuit
10
Battery P ack
1 µF
7 ISET2
2
System
10 µF
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FUNCTIONAL DESCRIPTIONS (continued)
POR
SLEEP MODE
Vcc > VI(BAT)
checked at all
times?
No
Indicate SLEEP
MODE
Yes
V I(BAT) < V(LOWV)
Yes
Regulate
I O(PRECHG)
Reset and Start
t(PRECHG) timer
Indicate Charge−
In−Progress
?
No
Reset all timers,
Start t (CHG) timer
Regulate Current
or V oltage
Indicate Charge−
In−Progress
No
V I(BAT)
<V(LOWV)
Yes
Yes
No
t(PRECHG)
Expired?
t (CHG)
Expired?
Yes
No
Yes
Yes
Fault Condition
V I(BAT)
<V(LOWV)
?
Indicate Fault
No
V I(BAT) > V(RCH)
?
I (TERM)
No
detection?
No
Enable I
(F AUL T)
current
Yes
No
Yes
V I(BAT) > V(RCH)
?
T urn off charge
Yes
Yes
Indicate DONE
Disable I (F AUL T)
No
current
V I(BAT) < V(RCH)
?
Figure 3. Charge Control Operational Flow Chart
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FUNCTIONAL DESCRIPTIONS (continued)
Autonomous Power Source Selection, Mode Control Pin
With the MODE input low, the bq24070/1 defaults to USB-mode charging, and the supply current is limited by
the ISET2 pin (100 mA for ISET2 = Low, 500 mA for ISET2 = High). If an input source is not available, then the
battery is selected as the source.
Boot-Up Sequence
In order to facilitate the system start-up and USB enumeration, the bq24070/1 offers a proprietary boot-up
sequence. On the first application of power to the bq24070/1, this feature enables the 100-mA USB charge rate
for a period of approximately 150 ms, (t(BOOT-UP)), ignoring the ISET2 and CE inputs setting. At the end of this
period, the bq24070/1 implement CE and ISET2 input settings. Table 1 indicates when this feature is enabled.
See Figure 8.
Power-Path Management
The bq24070/1 powers the system while independently charging the battery. This feature reduces the charge
and discharge cycles on the battery, allows for proper charge termination, and allows the system to run with an
absent or defective battery pack. This feature gives the system priority on input power, allowing the system to
power up with a deeply discharged battery pack. This feature works as follows:
AC Adapter
(2)
IN
OUT
VDC
GND
System
Q1
40 mΩ
BAT
PACK+
+
PACK−
bq24070/1
Q2
UDG−04082
Figure 4. Power-Path Management
Case 1: AC Mode (Mode = High)
System Power
In this case, the system load is powered directly from the AC adapter through the internal transistor Q1 (see
Figure 4). The output is regulated at 4.4 V (bq24070). If the system load exceeds the capacity of the supply, the
output voltage drops down to the battery's voltage.
Charge Control
When in AC mode the battery is charged through switch Q2 based on the charge rate set on the ISET1 input.
Dynamic Power-Path Management (DPPM)
This feature monitors the output voltage (system voltage) for input power loss due to brown outs, current limiting,
or removal of the input supply. If the voltage on the OUT pin drops to a preset value, V(DPPM) × SF, due to a
limited amount of input current, then the battery charging current is reduced until the output voltage stops
dropping. The DPPM control tries to reach a steady-state condition where the system gets its needed current
and the battery is charged with the remaining current. No active control limits the current to the system;
therefore, if the system demands more current than the input can provide, the output voltage drops just below
the battery voltage and Q2 turns on which supplements the input current to the system. DPPM has three main
advantages.
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FUNCTIONAL DESCRIPTIONS (continued)
1. This feature allows the designer to select a lower power wall adapter, if the average system load is
moderate compared to its peak power. For example, if the peak system load is 1.75 A, average system load
is 0.5 A and battery fast-charge current is 1.25 A, the total peak demand could be 3 A. With DPPM, a 2-A
adaptor could be selected instead of a 3.25-A supply. During the system peak load of 1.75 A and charge
load of 1.25 A, the smaller adaptor’s voltage drops until the output voltage reaches the DPPM regulation
voltage threshold. The charge current is reduced until there is no further drop on the output voltage. The
system gets its 1.75-A charge and the battery charge current is reduced from 1.25 A to 0.25 A. When the
peak system load drops to 0.5 A, the charge current returns to 1 A and the output voltage returns to its
normal value.
2. Using DPPM provides a power savings compared to configurations without DPPM. Without DPPM, if the
system current plus charge current exceed the supply’s current limit, then the output is pulled down to the
battery. Linear chargers dissipate the unused power (VIN-VOUT) × ILOAD. The current remains high (at current
limit) and the voltage drop is large for maximum power dissipation. With DPPM, the voltage drop is less
(VIN-V(DPPM-REG)) to the system which means better efficiency. The efficiency for charging the battery is the
same for both cases. The advantages include less power dissipation, lower system temperature, and better
overall efficiency.
3. The DPPM sustains the system voltage no matter what causes it to drop, if at all possible. It does this by
reducing the noncritical charging load while maintaining the maximum power output of the adaptor.
Note that the DPPM voltage, V(DPPM), is programmed as follows:
V (DPPM−REG) + I (DPPM) R(DPPM) SF
(1)
where
R(DPPM) is the external resistor connected between the DPPM and VSS pins.
I(DPPM) is the internal current source.
SF is the scale factor as specified in the specification table.
The safety timer is dynamically adjusted while in DPPM mode. The voltage on the ISET1 pin is directly
proportional to the programmed charging current. When the programmed charging current is reduced, due to
DPPM, the ISET1 and TMR voltages are reduced and the timer’s clock is proportionally slowed, extending the
safety time. In normal operation V(TMR) = 2.5 V; and, when the clock is slowed, V(TMR) is reduced. When
V(TMR) = 1.25 V, the safety timer has a value close to 2 times the normal operation timer value. See Figure 5
through Figure 6.
Case 2: USB Mode (Mode = L)
System Power
In this case, the system load is powered from a USB port through the internal switch Q1 (see Figure 4). Note
that in this case, Q1 regulates the total current to the 100-mA or 500-mA level, as selected on the ISET2 input.
The output, VOUT, is regulated to 4.4 V (bq24070). The system's power management is responsible for keeping
its system load below the USB current level selected (if the battery is critically low or missing). Otherwise, the
output drops to the battey voltage; therefore, the system should have a low-power mode for USB power
application. The DPPM feature keeps the output from dropping below its programmed threshold, due to the
battery charging current, by reducing the charging current.
Charge Control
When in USB mode, Q1 regulates the input current to the value selected by the ISET2 pin (0.1/0.5 A). The
charge current to the battery is set by the ISET1 resistor (typically > 0.5 A). Because the charge current typically
is programmed for more current than the USB current limit allows, the output voltage drops to the battery voltage
or DPPM voltage, whichever is higher. If the DPPM threshold is reached first, the charge current is reduced until
VOUT stops dropping. If VOUT drops to the battery voltage, the battery is able to supplement the input current to
the system.
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FUNCTIONAL DESCRIPTIONS (continued)
Dynamic Power-Path Management (DPPM)
The theory of operation is the same as described in CASE 1, except that Q1 is restricted to the USB current
level selected by the ISET2 pin.
Note that the DPPM voltage, V(DPPM), is programmed as follows:
V (DPPM−REG) + I (DPPM) R(DPPM) SF
(2)
where
R(DPPM) is the external resistor connected between the DPPM and VSS pins.
I(DPPM) is the internal current source.
SF is the scale factor as specified in the specification table.
Feature Plots
Figure 5 illustrates DPPM and battery supplement modes as the output current (IOUT) is increased; channel 1
(CH1) VAC = 5.4 V; channel 2 (CH2) VOUT; channel 3 (CH3) IOUT = 0 to 2.2 A to 0 A; channel 4 (CH4) VBAT =
3.5 V; I(PGM-CHG) = 1 A. In typical operation, bq24070/1 (VOUT = 4.4 Vreg), through an AC adaptor overload
condition and recovery. The AC input is set for ~5.1 V (1.5 A current limit), I(CHG) = 1 A, V(DPPM-SET) = 3.7 V,
V(DPPM-OUT) = 1.15 × V(DPPM-SET) = 4.26 V, VBAT = 3.5 V, Mode = H, and USB input is not connected. The output
load is increased from 0 A to ~2.2 A and back to 0 A as shown in the bottom waveform. As the IOUT load
reaches 0.5 A, along with the 1-A charge current, the adaptor starts to current limit, the output voltage drops to
the DPPM-OUT threshold of 4.26 V. This is DPPM mode. The AC input tracks the output voltage by the dropout
voltage of the AC FET. The battery charge current is then adjusted back as necessary to keep the output
voltage from falling any further. Once the output load current exceeds the input current, the battery has to
supplement the excess current and the output voltage falls just below the battery voltage by the dropout voltage
of the battery FET. This is the battery supplement mode. When the output load current is reduced, the operation
described is reversed as shown. If the DPPM-OUT voltage was set below the battery voltage, during input
current limiting, the output falls directly to the battery's voltage.
Under USB operation, when the loads exceeds the programmed input current thresholds a similar pattern is
observed. If the output load exceeds the available USB current, the output instantly goes into the battery
supplement mode.
VAC
VOUT
VOUT Reg. @ 4.4 V (bq24070)
VDPPM − OUT = 4.26 V, DPPM Mode
VOUT ≈ VOUT, BAT Supplement Mode
ICHG
IOUT
Figure 5. DPPM and Battery Supplement Modes
Figure 6 illustrates when Mode is toggled low for 500 µs. Power transfers from AC to USB to AC; channel 1
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FUNCTIONAL DESCRIPTIONS (continued)
(CH1) VAC = 5.4 V; channel 2 (CH2) V(USB) = 5 V; channel 3 (CH3) VOUT; output current, IOUT = 0.25 A; channel
4 (CH4) VBAT = 3.5 V; and I(PGM-CHG) = 1 A. When the Mode went low (1st div), the AC FET opened, and the
output fell until the USB FET turned on. Turning off the active source before turning on the replacement source
is referred to as break-before-make switching. The rate of discharge on the output is a function of system
capacitance and load. Note the cable IR drop in the AC and USB inputs when they are under load. At the 4th
division, the output has reached steady-state operation at the DPPM voltage level (charge current has been
reduced due to the limited USB input current). At the 6th division, the Mode goes high and the USB FET turns off
followed by the AC FET turning on. The output returns to its regulated value, and the battery returns to its
programmed current level.
Break Before Make
VAC
VUSB
VOUT
System Capacitance
Powering System
VBAT
DPPM Mode
USB is Charging System Capacitance
Hi
PSEL
Low
Figure 6. Toggle Mode Low
Figure 7 illustrates when a battery is inserted for power up; channel 1 (CH1) VAC = 0 V; channel 2 (CH2) VUSB =
0 V; channel 3 (CH3) VOUT; output current, IOUT = 0.25 A for VOUT > 2 V; channel 4 (CH4) VBAT = 3.5 V; C(DPPM) =
0 pF. When there are no power sources and the battery is inserted, the output tracks the battery voltage if there
is no load (<10 mA of load) on the output, as shown. If a load is present that keeps the output more than 200
mV below the battery, a short-circuit condition is declared. At this time, the load has to be removed to recover. A
capacitor can be placed on the DPPM pin to delay implementing the short-circuit mode and get unrestricted (not
limited) current.
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FUNCTIONAL DESCRIPTIONS (continued)
VBAT
VOUT
Figure 7. Insert Battery – Power-Up Output via BAT
Figure 8 illustrates USB boot up and power-up via USB; channel 1 (CH1) V(USH) = 0 to 5 V; channel 2 (CH2)
USB input current (0.2 A/div); Mode = Low; CE = High; ISET2 = High; VBAT = 3.85 V; V(DPPM) = 3.0 V (V(DPPM) ×
1.15 < VBAT, otherwise DPPM mode increases time duration). When a USB source is applied (if AC is not
present), the CE pin and ISET2 pin are ignored during the boot-up time and a maximum input current of 100 mA
is made available to the OUT or BAT pins. After the boot-up time, the IC implements the CE and ISET2 pins as
programmed.
VAC
IUSB
Figure 8. USB Boot-Up Power-Up
Battery Temperature Monitoring
The bq24070/1 continuously monitors battery temperature by measuring the voltage between the TS and VSS
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FUNCTIONAL DESCRIPTIONS (continued)
pins. An internal current source provides the bias for most-common 10 kΩ negative-temperature coefficient
thermistors (NTC) (see Figure 9). The device compares the voltage on the TS pin against the internal V(LTF) and
V(HTF) thresholds to determine if charging is allowed. Once a temperature outside the V(LTF) and V(HTF) thresholds
is detected, the device immediately suspends the charge. The device suspends charge by turning off the power
FET and holding the timer value (i.e., timers are not reset). Charge is resumed when the temperature returns to
the normal range. The allowed temperature range for 103AT-type thermistor is 0°C to 45°C. However, the user
may increase the range by adding two external resistors. See Figure 10.
PACK+
bq24070/1
TS
HTF
+
PACK−
ITS
PACK−
ITS
LTF
PACK+
bq24070/1
+
TS
NTC
12
LTF
BATTERY
PACK
VLTF
RT1 TEMP
VLTF
RT2
HTF
VHTF
12
NTC
BATTERY
PACK
VHTF
UDG−04086
UDG−04085
Figure 9. TS Pin Configuration
Figure 10. TS Pin Thresholds
Battery Pre-Conditioning
During a charge cycle, if the battery voltage is below the V(LOWV) threshold, the bq24070/1 applies a precharge
current, IO(PRECHG), to the battery. This feature revives deeply discharged cells. The resistor connected between
the ISET1 and VSS, RSET, determines the precharge rate. The V(PRECHG) and K(SET) parameters are specified in
the specifications table. Note that this applies to both AC-mode and USB-mode charging.
V(PRECHG) K(SET)
I O (PRECHG) +
RSET
(3)
The bq24070/1 activates a safety timer, t(PRECHG), during the conditioning phase. If V(LOWV) threshold is not
reached within the timer period, the bq24070/1 turns off the charger and enunciates FAULT on the STAT1 and
STAT2 pins. The timeout is extended if the charge current is reduced by DPPM or thermal regulation. See the
Timer Fault Recovery section for additional details.
Battery Charge Current
The bq24070/1 offers on-chip current regulation with programmable set point. The resistor connected between
the ISET1 and VSS, RSET, determines the charge level. The charge level may be reduced to give the system
priority on input current (see DPPM). The V(SET) and K(SET) parameters are specified in the specifications table.
V(SET) K(SET)
I O (OUT) +
RSET
(4)
When powered from a USB port, the input current available (0.1 A/0.5 A) is typically less than the programmed
(ISET1) charging current, and therefore, the DPPM feature attempts to keep the output from being pulled down
by reducing the charging current.
The charge level, during AC mode operation only (Mode = High), can be changed by a factor of 2 by setting the
ISET2 pin high (full charge) or low (half charge). The voltage on the ISET1 pin, VSET1, is divided by 2 when in
the half constant current charge mode. Note that with Mode low, the ISET2 pin controls only the 0.1 A/0.5 A
USB current level.
See the section titled Power-Path Management for additional details.
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FUNCTIONAL DESCRIPTIONS (continued)
Battery Voltage Regulation
The voltage regulation feedback is through the BAT pin. This input is tied directly to the positive side of the
battery pack. The bq24070/1 monitors the battery-pack voltage between the BAT and VSS pins. When the
battery voltage rises to the VO(REG) threshold, the voltage regulation phase begins and the charging current
begins to taper down.
If the battery is absent, the BAT pin cycles between charge done (VO(REG)) and charging (battery recharge
threshold, ~4.1 V).
See Figure 7 for power up by battery insertion.
As a safety backup, the bq24070/1 also monitors the charge time in the charge mode. If charge is not
terminated within this time period, t(CHG), the bq24070/1 turns off the charger and enunciates FAULT on the
STAT1 and STAT2 pins. See the DPPM operation under Case 1 for information on extending the safety timer
during DPPM operation. See theTimer Fault Recovery section for additional details.
Temperature Regulation and Thermal Protection
In order to maximize charge rate, the bq24070/1 features a junction temperature regulation loop. If the power
dissipation of the IC results in a junction temperature greater than the TJ(REG) threshold, the bq24070/1 throttles
back on the charge current in order to maintain a junction temperature around the TJ(REG) threshold. To avoid
false termination, the termination detect function is disabled while in this mode.
The bq24070/1 also monitors the junction temperature, TJ, of the die and disconnects the OUT pin from the IN
input if TJ exceeds T(SHTDWN). This operation continues until TJ falls below T(SHTDWN) by the hysteresis level
specified in the specification table.
The battery supplement mode has no thermal protection. The Q2 FET continues to connect the battery to the
output (system), if input power is not sufficient; however, a short-circuit protection circuit limits the battery
discharge current such that the maximum power dissipation of the part is not exceeded under typical design
conditions.
Charge Timer Operation
As a safety backup, the bq24070/1 monitors the charge time in the charge mode. If the termination threshold is
not detected within the time period, t(CHG), the bq24070/1 turns off the charger and enunciates FAULT on the
STAT1 and STAT2 pins. The resistor connected between the TMR and VSS, RTMR, determines the timer period.
The K(TMR) parameter is specified in the specifications table. In order to disable the charge timer, eliminate RTMR,
connect the TMR pin directly to the VREF pin. Note that this action eliminates all safety timers, and also clears
any timer fault. TMR pin should not be left floating.
t (CHG) + K(TMR) R(TMR)
(5)
While in the thermal regulation mode or DPPM mode, the bq24070/1 dynamically adjusts the timer period in
order to provide the additional time needed to fully charge the battery. This proprietary feature is designed to
prevent against early or false termination. The maximum charge time in this mode, t(CHG-TREG), is calculated by
Equation 6.
t (CHG) V(SET)
t (CHG−TREG) +
V (SET*REG)
(6)
Note that because this adjustment is dynamic and changes as the ambient temperature changes and the charge
level changes, the timer clock is adjusted. It is difficult to estimate a total safety time without integrating the
above equation over the charge cycle. Therefore, understanding the theory that the safety time is adjusted
inversely proportionately with the charge current and the battery is a current-hour rating, the safety time
dynamically adjusts appropriately.
The V(SET) parameter is specified in the specifications table. V(SET-TREG) is the voltage on the ISET pin during the
thermal regulation or DPPM mode and is a function of charge current. (Note that charge current is dynamically
adjusted during the thermal regulation or DPPM mode.)
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FUNCTIONAL DESCRIPTIONS (continued)
V (SET−TREG) +
I (OUT)
R(SET)
K(SET)
(7)
All deglitch times also adjusted proportionally to t(CHG-TREG).
Charge Termination and Recharge
The bq24070/1 monitors the voltage on the ISET1 pin, during voltage regulation, to determine when termination
should occur (C/10 – 250 mV). Once the termination threshold, I(TERM), is detected the bq24070/1 terminates
charge. The resistor connected between the ISET1 and VSS, RSET, programs the fast charge current level (C
level, VISET1 = 2.5 V) and thus the C/10 and C/25 current termination threshold level. The V(TERM) and
K(SET) parameters are specified in the specifications table. Note that this applies to both AC and USB charging.
V(TERM) K(SET)
I (TERM) +
R SET
(8)
After charge termination, the bq24070/1 re-starts the charge once the voltage on the BAT pin falls below the
V(RCH) threshold. This feature keeps the battery at full capacity at all times.
Sleep and Standby Modes
The bq24070/1 charger circuitry enters the low-power sleep mode if the input is removed from the circuit. This
feature prevents draining the battery into the bq24070/1 during the absence of input supply. Note that in sleep
mode, Q2 remains on (i.e., battery connected to the OUT pin) in order for the battery to continue supplying
power to the system.
The bq24070/1 enters the low-power standby mode if while input power is present, the CE input is low. In this
suspend mode, internal power FET Q1 (see Figure 4) is turned off, the BAT input is used to power the system
through the OUT pin. This feature is designed to limit the power drawn from the input supply (such as USB
suspend mode).
Charge Status Outputs
The open-drain (OD) STAT1 and STAT2 outputs indicate various charger operations as shown in Table 2.
These status pins can be used to drive LEDs or communicate to the host processor. Note that OFF indicates the
open-drain transistor is turned off. Note that this assumes CE = High.
Table 2. Status Pins Summary
CHARGE STATE
STAT1
Precharge in progress
ON
STAT2
ON
Fast charge in progress
ON
OFF
Charge done
OFF
ON
Charge suspend (temperature), timer fault, and sleep mode
OFF
OFF
PG, Outputs (Power Good)
The open-drain pin, PG, indicates when input power is present, and above the battery voltage. The
corresponding output turns ON (low) when exiting sleep mode (input voltage above battery voltage). This output
is turned off in the sleep mode (open drain). The PG pin can be used to drive an LED or communicate to the
host processor. Note that OFF indicates the open-drain transistor is turned off.
CE Input (Chip Enable)
The CE (chip enable) digital input is used to disable or enable the IC. A high-level signal on this pin enables the
chip, and a low-level signal disables the device and initiates the standby mode. The bq24070/1 enters the
low-power standby mode when the CE input is low with input present. In this suspend mode, internal power FET
Q1 (see block diagram) is turned off; the battery (BAT pin) is used to power the system via Q2 and the OUT pin.
This feature is designed to limit the power drawn from the input supply (such as USB suspend mode).
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Charge Disable Functions
The DPPM input can be used to disable the charge process. This can be accomplished by floating the DPPM
pin.
Timer Fault Recovery
As shown in Figure 3, bq24070/1 provides a recovery method to deal with timer fault conditions. The following
summarizes this method:
Condition 1: Charge voltage above recharge threshold (V(RCH)) and timeout fault occurs.
Recovery Method: bq24070/1 waits for the battery voltage to fall below the recharge threshold. This could
happen as a result of a load on the battery, self-discharge, or battery removal. Once the battery falls below the
recharge threshold, the bq24070/1 clears the fault and starts a new charge cycle. A POR or CE toggle also
clears the fault.
Condition 2: Charge voltage below recharge threshold (V(RCH)) and timeout fault occurs.
Recovery Method: Under this scenario, the bq24070/1 applies the I(FAULT) current. This small current is used to
detect a battery removal condition and remains on as long as the battery voltage stays below the recharge
threshold. If the battery voltage goes above the recharge threshold, then the bq24070/1 disables the I(FAULT)
current and executes the recovery method described for condition 1. Once the battery falls below the recharge
threshold, the bq24070/1 clears the fault and starts a new charge cycle. A POR or CE toggle also clears the
fault.
Short-Circuit Recovery
The output can experience two types of short-circuit protection, one associated with the input and one with the
battery.
If the output drops below ~1 V, an input short-circuit condition is declared and the input FET, Q1 is turned off. To
recover from this state, a 500-Ω pullup resistor from the input is applied (switched) to the output. To recover, the
load on the output has to be reduced {Rload > 1 V × 500 Ω/ (Vin–Vout)} such that the pullup resistor is able to
lift the output voltage above 1 V, for the input FET to be turned back on.
If the output drops 200 mV below the battery voltage, the battery FET, Q2 is considered in short circuit and the
battery FET turns off. To recover from this state, there is a 10-mA current source from the battery to the output.
Once the output load is reduced, such that the 10-mA current source can pick up the output within 200 mV of
the battery, the FET turns back on.
If the short is removed, and the minimum system load is still too large [R<(VBat-200 mV) / 10 mA], the
short-circuit protection can be temporarily defeated. The battery short-circuit protection can be disabled
(recommended only for a short time) if the voltage on the DPPM pin is less than 1 V. Pulsing this pin below 1 V,
for a few microseconds, should be enough to recover.
This short-circuit disable feature was implemented mainly for power up when inserting a battery. Because the
BAT input voltage rises much faster than the OUT voltage (Vout<Vbat-200 mV), with most any capacitive load
on the output, the part can get stuck in short-circuit mode. Placing a capacitor between the DPPM pin and
ground slows the VDPPM rise time, during power up, and delays the short-circuit protection. Too large a
capacitance on this pin (too much of a delay) could allow too-high currents if the output was shorted to ground.
The recommended capacitance is 1 nF to 10 nF. The VDPPM rise time is a function of the 100-µA DPPM current
source, the DPPM resistor, and the capacitor added.
VREF
The VREF is used for internal reference and compensation (3.3 V typ). Additionally, it can be used to disable the
safety timer and termination by connecting the TMR to the VREF pin. For internal compensation, the VREF pin
requires a minimum 0.1-µF ceramic capacitor. The VREF capacitor should not exceed 1 µF.
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APPLICATION INFORMATION
Selecting the Input and Output Capacitors
In most applications, all that is needed is a high-frequency decoupling capacitor on the input. A 0.1-µF ceramic
capacitor, placed in close proximity to IN to VSS pins, works well. In some applications depending on the power
supply characteristics and cable length, it may be necessary to add an additional 10-µF ceramic capacitor to the
input.
The bq24070/1 only requires a small output capacitor for loop stability. A 0.1-µF ceramic capacitor placed
between the OUT and VSS pin is typically sufficient.
It is recommended to install a minimum of 33-µF capacitor between the BAT pin and VSS (in parallel with the
battery). This ensures proper hot plug power up with a no-load condition (no system load or battery attached).
Thermal Considerations
The bq24070/1 is packaged in a thermally enhanced MLP package. The package includes a QFN thermal pad
to provide an effective thermal contact between the device and the printed-circuit board (PCB). Full PCB design
guidelines for this package are provided in the application note entitled QFN/SON PCB Attachment (SLUA271).
The power pad should be tied to the VSS plane. The most common measure of package thermal performance is
thermal impedance (θJA) measured (or modeled) from the chip junction to the air surrounding the package
surface (ambient).
The mathematical expression for θJA is:
T * TA
q JA + J
P
(9)
where
TJ = chip junction temperature
TA = ambient temperature
P = device power dissipation
Factors that can greatly influence the measurement and calculation of θJA include:
• whether or not the device is board mounted
• trace size, composition, thickness, and geometry
• orientation of the device (horizontal or vertical)
• volume of the ambient air surrounding the device under test and airflow
• whether other surfaces are in close proximity to the device being tested
The device power dissipation, P, is a function of the charge rate and the voltage drop across the internal power
FET. It can be calculated from Equation 10:
P + ƪǒV IN * V OUTǓ
ǒI OUT ) I BATǓƫ ) ƪǒV OUT * VBATǓ
ǒIBATǓƫ
(10)
Due to the charge profile of Li-xx batteries, the maximum power dissipation is typically seen at the beginning of
the charge cycle when the battery voltage is at its lowest. See Figure 1. Typically the Li-ion battery's voltage
quickly (< 2 V minutes) ramps to approximately 3.5 V, when entering fast charge (1-C charge rate and battery
above 3 V). Therefore, it is customary to perform the steady-state thermal design using 3.5 V as the minimum
battery voltage because the system board and charging device does not have time to reach a maximum
temperature due to the thermal mass of the assembly during the early stages of fast charge. This theory is
easily verified by performing a charge cycle on a discharged battery while monitoring the battery voltage and
chargers power pad temperature.
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21
bq24070
bq24071
www.ti.com
SLUS694B – MARCH 2006 – REVISED AUGUST 2006
APPLICATION INFORMATION (continued)
PCB Layout Considerations
It is important to pay special attention to the PCB layout. The following provides some guidelines:
• To obtain optimal performance, the decoupling capacitor from the input terminal to VSS and the output filter
capacitor from OUT to VSS should be placed as close as possible to the bq24070/1, with short trace runs to
both signal and VSS pins.
• All low-current VSS connections should be kept separate from the high-current charge or discharge paths
from the battery. Use a single-point ground technique incorporating both the small signal ground path and
the power ground path.
• The high-current charge paths into IN and from the BAT and OUT pins must be sized appropriately for the
maximum charge current in order to avoid voltage drops in these traces.
• The bq24070/1 is packaged in a thermally enhanced MLP package. The package includes a QFN thermal
pad to provide an effective thermal contact between the device and the printed-circuit board. Full PCB
design guidelines for this package are provided in the application note entitled QFN/SON PCB Attachment
(SLUA271).
22
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