TIGER ELECTRONIC CO.,LTD Real-time Clock/Calendar PCF8563 DESCRIPTION The PCF8563 is a CMOS real-time clock/calendar optimized for low power consumption. A programmable clock output, interrupt output and voltage-low detector are also provided. All address DIP8 and data are transferred serially via a two-line bidirectional I 2 C-bus. Maximu m bus speed is 400 kbits/s. The built-in word address register is incremented automatically after each written or read SOP8 data byte. FEATURES TSSOP8 Provides year, month, day, weekday, hours, minutes and seconds based on32.768 kHz quartz crystal Century flag Wide operating supply voltage range: 1.0 to 5.0 V Low back-up current; typical 0.25 µA at V D D = 3.0 V and Tamb = 25 °C 400 kHz two-wire I 2 C-bus interface (at V D D = 1.8 to 5.0 V) Programmable clock output for peripheral devices: 32.768 kHz, 1024 Hz, 32 Hz and 1 Hz Alarm and timer functions Voltage-low detector Integrated oscillator capacitor Internal power-on reset I 2 C-bus slave address: read A3H; write A2H Open drain interrupt pin. 1/23 PCF8563 APPLICATIONS Mobile telephones Portable instruments Fax machines Battery powered products BLOCK DIAGRAM 2/23 PCF8563 PIN CONFIGURATION Symbol OSC1 OSCO INT Vss SDA CLK CLKOUT V DD Pin 1 2 3 4 5 6 7 8 Description Oscillator input Oscillator output Interrupt output(open-drain; active LOW) Ground Serial data I/O Serial clock input Clock output (open-drain) Positive supply A B S O L U T E M A X I M U M R AT I N G （ Tamb =2 5℃ ） Characteristics Supply Vo ltage Input Vo ltage on Inputs SCL and SDA Input Voltage on Input OSCI Output Vo ltage on Outputs CLKOUT and INT DC Input Current at Any Input DC Output Current at Any Output Total Power Dissipation Operating Temp erature Range Storage Temp erature Range Symbo l V DD Min -0.5 -0.5 -0.5 Max +5.5 +5.5 V D D +0.5 Unit V V V Vo -0.5 +5.5 V II Io Ptot Topr Tstg -10 -10 +10 +10 300 +85 +150 mA mA mW ℃ ℃ VI -40 -65 3/23 PCF8563 STATIC ELECTRICAL CHARACTERISTICS （ Unless otherwise specified， V D D = 1.8 to 5.0 V; Vss = 0 V; Tamb =- 40 to 85° C; f O S C = 32.768 kHz; quartz Rs = 40 kΩ; C L = 8 pF; ） Characteristics Supplies Symbol Test conditions V DD I 2 C-bus inactive Ta=25° C I 2 C-bus active f S C L =400kHz Supply voltage Supply voltage fo Reliable clock/calen dar information Supply current CLKOUT disabled (FE=0) Supply current CLKOUT enabled (f C L K O U T =32kHz;FE=1) Ta=25° C I DD1 I DD2 Min Max Unit 1.0*1 5 .0 V 1.8*1 5.0 V V LOW 5.0 V 800 200 µA µA 275 250 225 550 500 450 nA nA nA 500 400 400 750 650 600 nA nA nA 825 550 425 1600 1000 800 nA nA nA 950 650 500 1700 1100 900 nA nA nA f S C L =400kHz *2 f S C L =400kHz f S C L =0Hz; Ta=25° C *2 V D D =5V V D D =3V V D D =2V f S C L =0 Hz *2 V D D =5V V D D =3V V D D =2V f S C L =0Hz; Ta=25° C *2 V D D =5V V D D =3V V D D =2V f S C L =0 Hz *2 V D D =5V V D D =3V V D D =2V Typ . Inputs Low-level input voltage High-level input voltage Input leakage current Input capacitance Outputs Low-level output current;pin SDA V IL V SS 0.7V D V IH I LI Ci I OL(SDA) D V I =V D D or V S S *3 V O L =0.4V; V D D =5V -1 -3 0.3V D D V V DD V +1 7 µA pF mA 4/23 PCF8563 Characteristics Low-level outpu t current;pin INT Low-level output current;pin CLKOUT High-level output current;pin CLKOUT Output leakage current Vo ltage Detector Voltage-low detection level Symbol Test conditions I OL(INT) I OL(CLKO UT) I OH(CLKO UT) I LO V LOW V O H =4.6V; V D D =5V V O =V D D or V S S Min Typ . Max Unit -1 mA -1 mA 1 mA -1 Ta=25° C 0.9 +1 µA 1.0 V *1 For reliable oscillator start-up at power-up: V D D (min)power-up = V D D (min) + 0.3 V. *2 Timer source clock = 1¤60 Hz; SCL and SDA = V D D . *3 Tested on samp le basis. DYNAMIC ELECTRICAL CHARACTERISTICS （ Unless otherwise specified， V D D = 1.8 to 5.0 V; Vss = 0 V; Tamb =- 40 to 85° C; f O S C = 32.768 kHz; quartz Rs = 40 kΩ; C L = 8 pF; ） Characteristics Oscillator Integrated load capacitance Symbol Test conditions C L(integrat ed) Typ. Max Unit 15 25 35 pF 40 kΩ ∆f O S C /f O ∆V D D =200mV Ta=25° C SC Quartz crystal parameters (f O S C =32.768kHz) Series resistance RS Parallel load CL capacitance Trimmer capacitance CT CLKOUT output CLKOUT duty factor δ C L K O U T *1 2 I C-bus timing characteristics * 2 SCL clock frequency *3 f SCL START co ndition hold t H D ; S TA time Set-up time for a repeated START t S U ; S TA condition SCL low time t LOW SCL high time t HIGH Oscillator stability Min 2×10 -7 10 5 pF 25 50 pF % 400 kHz 0.6 µs 0.6 µs 1.3 0.6 µs µs 5/23 PCF8563 Characteristics SCL and SDA rise time SCL and SDA fall time Capacitive bus line load Data set-up time Data hold time Set-up time for STOP condition To lerable spike width on bus Symbol tr tf Cb Test conditions Min Typ . t S U ; D AT t H D ; D AT 100 0 Unit µs µs pF ns ns t SU;STO 4.0 µs t SW Max 0.3 0.3 400 50 µs *1 Unspecified for f C L K O U T = 32.768 kHz. *2 All timing values are valid within the operating supply voltage range at Tamb and referenced to V I L and V I H with an input voltage swing of V S S to V D D . *3 I 2 C-bus access time between two STARTs or between a START and a STOP condition to this device mu st be less than one second. I2C-bus timing waveforms 6/23 PCF8563 APPLICATION CIRCUIT Method 1: Fixed OSCI capacitor — By evaluating the average capacitance necessary for the application layout a fixed capacitor can be used. The frequency is best measured via the 32.768 kHz signal available after power-on at the CLKOUT pin. The frequency tolerance depends on the quartz crystal tolerance, the capacitor tolerance and the device-to-device tolerance (on average ±5×10 - 6 ). Average deviations of ±5 minutes per year can be easily achieved. Method 2: OSCI trimmer — The oscillator is tuned to the required accuracy by adjusting a trimmer capacitor on pin OSCI and measuring the 32.768 kHz signal available after power-on at the CLKOUT pin. Method 3: OSCO output — Direct output measurement on pin OSCO (accounting for test probe capacitance). 7/23 PCF8563 APPLICATION SUMMARY The PCF8563 contains sixteen 8-bit registers with an auto-incrementing address register, an on-chip 32.768 kHz oscillator with an integrated capacitor, a frequency divider which provides the source clock for the Real-Time Clock (RTC), a programmable clock output, a timer, an alarm, a voltage-low detector and a 400 kHz I 2 C-bus interface. All 16 registers are designed as addressable 8-bit parallel registers although not all bits are implemented. The first two registers (memory address 00H and 01H) are used as control and/or status registers. The memo ry addresses 02H through 08H are used as counters for the clock function (seconds up to year counters). Address locations 09H through 0CH contain alarm registers which define the conditions for an alarm. Address 0DH controls the CLKOUT output frequency. 0EH and 0FH are the timer control and timer registers, respectively. The Seconds, Minutes, Hours, Days, Months, Years as well as the Minute alarm, Hour alarm and Day alarm registers are all coded in BCD format. The Weekdays and Weekday alarm register are not coded in BCD format. When one of the RTC registers is read the contents of all counters are frozen. Therefore, faulty reading of the clock/calendar during a carry condition is prevented. Alarm function modes By clearing the MSB (bit AE = Alarm Enable) of one or more of the alarm registers, the corresponding alarm condition(s) will be active. In this way an alarm can be generated from once per minute up to once per week. The alarm condition sets the alarm flag, AF (bit 3 of Control/Status 2 register). The asserted AF can be used to generate an interrupt (INT). Bit AF can only be cleared by software. Timer The 8-bit countdown timer (address 0FH) is controlled by the Timer Control register (address 0EH). The Timer Control register selects one of 4 source clock frequencies for the timer (4096, 64, 1, or 1/60 Hz), and enables/disables the timer. The timer counts down from a software-loaded 8-bit binary value. At the end of every countdown, the timer sets the timer flag TF. The timer flag TF can only be cleared by software. The asserted timer flag TF can be used to generate an interrupt (INT). The interrupt may be generated as a pulsed signal every countdown period or as a permanently active signal which follows the condition of TF. TI/TP is used to control this mode selection. When reading the timer, the current countdown value is returned. 8/23 PCF8563 CLKOUT output A programmable square wave is available at the CLKOUT pin. Operation is controlled by the CLKOUT frequency register (address 0DH). Frequencies of32.768 kHz (default), 1024, 32 and 1 Hz can be generated for use as a system clock, microcontroller clock, input to a charge pump, or for calibration of the oscillator. CLKOUT is an open-drain output and enabled at power-on. If disabled it becomes high-impedance. Reset The PCF8563 includes an internal reset circuit which is active whenever the oscillator is stopped. In the reset state the I 2 C-bus logic is initialized and all registers, including the address pointer, are cleared with the exception of bits FE, VL, TD1, TD0, TESTC an d AE which are set to lo g ic 1 . Vo ltag e-lo w d etectio n Voltage-low detector and clock monitor The PCF8563 has an on-chip voltage-low detector. When V D D drops below V l o w the VL bit (Voltage Low, bit 7 in the Seconds register) is set to indicate that reliable clock/calendar information is no longer guaranteed. The VL flag can only be cleared by software. The VL bit is intended to detect the situation when V D D is decreasing slowly for example under battery operation. Should V D D reach V l o w before power is re-asserted then the VL bit will be set. This will indicate that the time may be corrupted. Registers Organization Table 1 registers overview Bit positions labelled as ‘- ’are not implemented; those labelled with ‘0’ should always be written with logic 0. 9/23 PCF8563 Table 2 BCD formatted registers overview Bit positions labelled as ‘- ’are not implemented *1 Not coded in BCD Control/Status 1 register Table 3 Control/Status 1 register bits description(address 00H) 10/23 PCF8563 Control/Status 2 register Table 4 Description of Control/Status 2 register bits description(address 01H) Table 5 INT operation(bit TI/TP=1) *1 TF and INT become active simu ltaneously. *2 n = loaded countdown timer value. Timer stopped when n = 0. Table 6 Value descriptions for bits AF and TF 11/23 PCF8563 Seconds,Minutes and Hours registers Table 7 Seconds/VL register bits description(address 02H) Table 8 Minutes register bits description(address 03H) Table 9 Hours register bits description(address 04H) Days,Weekdays,Months/Century and Years registers Table 10 Days register bits description(address 05H) Table 11 Weekdays register bits description(address 06H) 12/23 PCF8563 Table 12 Weekday assignments Table 13 Months/Century register bits description(address 07H) Table 14 Month assignments Table 15 Years register bits description(address 08H) 13/23 PCF8563 Alarm registers When one or mo re of the alarm registers are loaded with a valid minute, hour, day or weekday and its corresponding AE (Alarm Enable) bit is a logic 0, then that information will be comp ared with the current minute, hour, day and weekday. When all enabled comparisons first match, the bit AF (Alarm Flag) is set. AF will remain set until cleared by software. Once AF has been cleared it will only be set again when the time increments to match the alarm condition once mo re. Alarm registers which have their AE bit set at logic 1 will be ignored. Table 16 Minute alarm register bits description(address 09H) Table 17 Hour alarm register bits description(address 0AH) Table 18 Day alarm register bits description(address 0BH) Table 19 Weekday alarm register bits description(address 0CH) 14/23 PCF8563 CLKOUT frequency register Table 20 CLKOUT frequency register bits description(address 0DH) Table 21 CLKOUT frequency selection Countdown timer registers The Timer register is an 8-bit binary countdown timer. It is enabled and disabled via the Timer control register bit TE. The source clock for the timer is also selected by the Timer control register. Other timer properties, e.g. interrupt generation, are controlled via the Control/status 2 register. For accurate read back of the countdown value, the I 2 C-bus clock SCL mu st be operating at a frequency of at least twice the selected timer clock. Table 22 Timer control register bits description (address 0EH) Table 23 Timer source clock frequency selection 15/23 PCF8563 Table 24 Timer countdown value register bits description(address 0FH) EX T_CLK test mode A test mode is available which allows for on-board testing. In this mode it is possible to set up test conditions and control the operation of the RTC. The test mode is entered by setting bit TEST1 in the Control/Status1 register. The CLKOUT pin then becomes an input. The test mode replaces the internal 64 Hz signal with the signal that is applied to the CLKOUT pin. Every 64 positive edges applied to CLKOUT will then generate an increment of one second. The signal applied to the CLKOUT pin should have a minimu m pulse width of 300 ns and a minimum period of 1000 ns. The internal 64 Hz clock, now sourced from CLKOUT, is divided down to 1 Hz by a 2 6 divide chain called a pre-scaler. The pre-scaler can be set into a known state by using the STOP bit. When the STOP bit is set, the pre-scaler is reset to 0. STOP must be cleared before the pre-scaler can operate again. From a STOP condition, the first 1 s increment will take place after32 positive edges on CLKOUT. Thereafter, every 64 positive edges will cause a 1 s increment. Remark: Entry into EXT_CLK test mode is not synchronized to the internal 64 Hz clock. When entering the test mode, no assump tion as to the state of the pre-scaler can be made. Operation example 1. Enter the EXT_CLK test mode; set bit 7 of Control/Status 1 register (TEST = 1) 2. Set bit 5 of Control/Status 1 register (STOP = 1) 3. Clear bit 5 of Control/Status 1 register (STOP = 0) 4. Set time registers (Seconds, Minutes, Hours, Days, Weekdays, Months/Century and Years) to desired value 5. Apply 32 clock pulses to CLKOUT 6. Read time registers to see the first change 7. Apply 64 clock pulses to CLKOUT 8. Read time registers to see the second change. Repeat steps 7 and 8 for additional increments. Power-On Reset (POR) override mode The POR duration is directly related to the crystal oscillator start-up time. Due to the long 16/23 PCF8563 start-up times experienced by these types of circuits, a mechanism has been built in to disable the POR and hence speed up on-board test of the device. The setting of this mode requires that the I 2 C-bus pins, SDA and SCL, be toggled in a specific order as shown in Figure 5. All timing values are required minimu m. Once the override mode has been entered, the chip immediately stops being reset and normal operation starts i.e. entry into the EXT_CLK test mode via I 2 C-bus access. The override mode is cleared by writing a logic 0 to bit TESTC. Re-entry into the override mode is only possible after TESTC is set to logi c 1. Setting TESTC to logic 0 during normal operation has no effect except to prevent entry into the POR override mode. POR override sequence Serial interface The serial interface of the PCF8563 is the I 2 C-bus. A detailed description of the I 2 C-bus specification, including applications, is given in the brochure: The I 2 C-bus and how to use it, order no. 9398 393 40011 or I 2 C Peripherals Data Handbook IC12. Characteristics of the I 2 C-bus The I 2 C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines mu st be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy. The I 2 C-bus system configuration is shown in Figure below. A device generating a message is a ‘transmitter’, a device receiving a message is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’. I 2 C-bus system configuration 17/23 PCF8563 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P); see Figure below. START an d STOP con d itio n s I 2 C-bus Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line mu st remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal; see Figure below.. Bit tran sfer on th e I 2 C-bus Acknowledge The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH level signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. 18/23 PCF8563 The device that acknowledges mu st pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times mu st be taken into consideration). A master receiver mu st signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. Acknowledge on the I 2 C-bus I 2 C-bus protocol Addressing: Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. The addressing is always carried out with the first byte transmitted after the start procedure. The PCF8563 acts as a slave receiver or slave transmitter. Therefore the clock signal SCL is only an input signal, but the data signal SDA is a bidirectional line. The PCF8563 slave address is shown in Figure below. Slave address Clock/calendar read/write cycles: The I 2 C-bus configuration for the different PCF8563 read and write cycles are shown in Figure 11, 12 and 13. The word address is a four bit value that defines which register is to be accessed next. The upper four bits of the word address are not used. 19/23 PCF8563 Master transmits to slave receiver(write mode) Master read s affer settin g word address(write word address;read data) Master reads slave immediately after first byte (read mode) 20/23 PCF8563 CHARACTERISTICS CURVES 21/23 PCF8563P / PCF8563T OUTLINE DRAWING Unit:mm DIP8 PCF8563P Unit:mm SOP8 PCF8563T 22/23 PCF8563TS Unit:mm TSSOP8 PCF8563TS 23/23