NSC NM29N16

NM29N16
16 MBit (2M x 8 Bit) CMOS NAND FLASH E2PROM
General Description
Features
The NM29N16 is a 16 Mbit (2 Mbyte) NAND FLASH. The
device is organized as an array of 512 blocks, each consisting of 16 pages. Each page contains 264 bytes. All commands and data are sent through eight I/O pins. To read
data, a page is first transferred out of the array to an on-chip
buffer. Sending successive read pulses (RE low) reads out
successive bytes of data. The erase operation is implemented in either a single block (4 kbytes) or on multiple blocks at
the same time. Programming the device requires sending
address and data information to the on-board buffer and
then issuing the program command. Typical program time
for 264 bytes is 400 ms. All erase and program operations
are internally timed.
The NM29N16 incorporates a number of features that make
it ideal for portable applications requiring high density storage. These features include single 5V operation, high read/
write endurance (250k cycle), and low current operation
(15 mA during reads). The device comes in a TSOP Type II
package which meets the requirements of PCMCIA cards.
The NM29N16 is suited for numerous applications such as
Solid State Drives (SSD), Audio Recording, and Image Storage for digital cameras.
Y
Y
Y
Y
Y
Y
Y
Y
Y
Single 5V g 10% power supply
Write/Erase endurance of 250,000 cycles, target of
1,000,000 cycles
Fast Erase/Program Times
Ð Average Program Time of 400 ms/264 bytes
Ð Typical Block Erase Time of 6 ms
Organized as 512 blocks, each consisting of 16 pages
of 264 bytes
Ð Read/Program in pages of 264 bytes
Ð Erase in Blocks of 4 kbytes
High Performance Read Access times
Ð Initial 25 ms page transfer
Ð Sequential 80 ns access
Low Operating Current (typical)
Ð Typical Read current of 15 mA
Ð Typical Program current of 40 mA
Ð Typical Erase current of 20 mA
Ð Standby current less than 100 mA (CMOS)
Command Register for Mode Control:
Ð Read
ÐReset
Ð Auto Page Program
ÐSuspend/Resume
Ð Auto Block Erase
ÐStatus Read
400 mil TSOP Type II Package
JEDEC standard pinout
Block Diagram
TL/D/11915 – 1
C1996 National Semiconductor Corporation
TL/D/11915
RRD-B30M56/Printed in U. S. A.
NM29N16 16 MBit (2M x 8 Bit) CMOS NAND FLASH E2PROM
February 1996
Pin Connection (Top View)
NM29N16R
NM29N16S
TL/D/11915–2
Pin Assignment
I/OI – 8
I/O Port
CE
Chip Enable
WE
Write Enable
RE
Read Enable
CLE
Command Latch Enable
ALE
Address Latch Enable
WP
Write Protect
R/B
Ready/Busy
VCC/VSS
Power Supply/Ground
TL/D/11915 – 3
TL/D/11915 – 85
Number of Valid Blocks (1)
Symbol
NVB
NM29N16
Parameter
Valid Block Number
Units
Min
Typ
Max
502
508
512
Blocks
Note 1: The NM29N16S/R may include unusable blocks. Refer to notification (17) toward the end of this document.
Capacitance* (TA e a 25§ C, f e 1 MHz)
Symbol
Parameter
Condition
Type
Max
CIN
Input
VIN e 0V
Min
5
10
pF
COUT
Output
VOUT e 0V
5
10
pF
*This parameter is periodically sampled and is not 100% tested
http://www.national.com
2
Units
Absolute Maximum Ratings
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Min Typ
Max
Power Supply (VCC)
4.5 5.0
5.5
High Level Input Voltage (VIH) 2.4
VCC a 0.5
0.8
Low Level Input Voltage (VIL) b0.3*
b 0.6V to 7.0V
Power Supply (VCC)
b 0.6V to 7.0V
Input Voltage (VIN)
b 0.6V to VCC g 0.5V ( s 7V)
Input/Output Voltage (VI/O)
Power Dissipation (PD)
0.5W
Soldering Temperature (Tsolder) (10 seconds)
260§ C
b 55§ C to 150§ C
Storage Temperature (Tstg)
0§ C to 70§ C
Operating Temperature (Topr)
Units
V
V
V
* b 2V (Pulse Width k 20 ns)
DC Operating Characteristics (TA e 0§ C to 70§ C, VCC e 5V g 10%)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
g 10
mA
g 10
mA
15
30
mA
ILI
Input Leakage Current
VIN e 0V to VCC
ILO
Output Leakage Current
VOUT e 0.4V to VCC
ICC01
Operating Current (Serial Read)
ICC02
Operating Current (Serial Read)
CE e VIL
IOUT e 0 mA
5
mA
ICC03
Operating Current (Command Input)
tCYCLE e 80 ns
15
30
mA
ICC04
Operating Current (Data Input)
tCYCLE e 80 ns
50
70
mA
ICC05
Operating Current (Address Input)
tCYCLE e 80 ns
15
30
mA
ICC06
Operating Current (Register Read)
tCYCLE e 80 ns
15
30
mA
ICC07
Programming Current
40
60
mA
ICC08
Erasing Current
20
40
mA
ICCS1
Standby Current
CE e VIH
1
mA
ICCS2
Standby Current
CE e VCC b 0.2V
100
mA
VOH
High Level Output Voltage
IOH e b400 mA
VOL
Low Level Output Voltage
IOL e 2.1 mA
IOL(R/B)
Output Current of (R/B) Pin
VOL e 0.4V
tCYCLE e 80 ns
tCYCLE e 1 ms
2.4
V
0.4
10
V
mA
Pin Functions
The NM29N16 is a sequential access memory which utilizes
time sharing input of address and data information.
Command Latch Enable: CLE The CLE input signal is
used to control the input of commands into the internal
command register. The command is latched into the command register from the I/O port at the rising edge of the WE
signal while CLE is high.
Address Latch Enable: ALE The ALE signal is used to
control the input of either address information or input data
into the internal address/data register. Address information
is latched at the rising edge of WE if ALE is high. Input data
is latched if ALE is low.
Chip Enable : CE The device goes into a low power standby mode during a read operation when CE goes high. The
CE signal is ignored when the device is in a busy state (R/B
e L) such as during a program or erase operation and will
not go into standby mode if a CE high signal is input.
Write Enable : WE The WE signal is used to strobe data
into the I/O port.
Read Enable: RE The RE signal strobes data output. Data
is available tREA after the falling edge of RE. The internal
column address counter is also incremented (Address a 1)
with this falling edge.
I/O Port: I/O 1 – 8 The I/O 1 – 8 pins are used as the port for
transferring address, command and input/output data information to or from the device.
Write Protect : WP The WP signal is used to protect the
device from inadvertent programming or erasing. The internal voltage regulator is reset when WP is low. This signal is
usually used for protecting the data during the power on/off
sequence when the input signals are invalid.
Ready/Busy: R/B The R/B output signal is used to indicate the operating condition of the device. The R/B signal is
in a busy state (R/B e L) during the program, erase or read
operations and will return to a ready state (R/B e H) after
completion. The output buffer of this signal is an open drain.
3
http://www.national.com
AC Test Conditions
Input Level
2.4V/0.4V
Input Comparison Level
2.2V/0.8V
Output Data Comparison Level
Output Load
2.0V/0.8V
1TTL & CL (100 pF)
AC Electrical Characteristics (TA e 0§ C to 70§ C, VCC e 5V g 10%)
Symbol
Parameter
Min
Max
CLE Setup Time
tCLH
CLE Hold Time
40
ns
tCS
CE Setup Time
20
ns
tCH
CE Hold Time
40
ns
tWP
Write Pulse Width
40
ns
tALS
ALE Setup Time
20
ns
tALH
ALE Hold Time
40
ns
tDS
Data Setup Time
30
ns
tDH
Data Hold Time
20
ns
tWC
Write Cycle Time
80
ns
tWH
WE High Hold Time
20
ns
tWW
WP High to WE Falling Edge
100
ns
tRR
Ready to RE Falling Edge
20
ns
tRC
Read Cycle Time
80
tREA
RE Access Time (Serial Data Access)
tCEH
CE High Time at the Last Address in Serial Read Cycle
tREAID
RE Access Time (ID Read)
tRHZ
RE High to Output High Impedance
tCHZ
CE High to Output High Impedance
tREH
RE High Hold Time
20
tIR
Output High Impedance to RE Rising Edge
0
tRSTO
RE Access Time (Status Read)
45
tCSTO
CE Access Time (Status Read)
55
tRHW
RE High to WE Low
tWHC
WE High to CE Low
50
ns
tWHR
WE High to RE Low
50
ns
tAR1
ALE Low to RE Low (Address Register Read, ID Read)
200
ns
tCR
CE Low to RE Low (Address Register Read, ID Read)
200
ns
tR
Memory Cell Array to Starting Address
25
tWB
WE High to Busy
200
tAR2
ALE Low to RE low (Read Cycle)
tRB
RE Last Clock Rising Edge to Busy (At Sequential Read)
tCRY
CE High to Ready (in case of interception by CE at Read Mode)
tRST
Device Reset Time (Read/Program/Erase/Suspend)
http://www.national.com
20
Unit
tCLS
250
ns
ns
90
ns
20
ns
30
(3)
ns
ns
ns
0
ns
ns
ns
150
4
(1)
ns
45
5
Notes
ns
ms
ns
ns
200
ns
100 a tr(R/B)
ns
10/20/1500/10
ms
(2)
AC Electrical Characteristics (TA e 0§ C to a 70§ C, VCC e 5V g 10%) (Continued)
Note 1: In case that CLE, ALE, CE are input with clock, tWC exceeds 80 ns. Transition time tT s 5 ns
set-up time
hold time
t
t
4tT
a
a WP a XX a
20 ns
40 ns
40 ns
20 ns
TL/D/11915 – 5
Note 2: CE high to Ready time depends on Pull up resister tied to R/B pin. (Refer to notification (10) toward the end of this document.)
Note 3: In the case that CE turns to a high level after accessing the last address (263) in read mode (1) or (2), CE high time must keep equal to or greater than
300 ns when the delay time of CE against RE is 0 to 200 ns as shown below.
In the second case, the device will not turn to a ‘‘Busy’’ state when the CE delay time is less than 30 ns.
TL/D/11915 – 6
Programming and Erasing Characteristic (TA e 0§ C to a 70§ C, VCC e 5V g 10%)
Symbol
Parameter
tPROG
Average Programming Time
N
Divided Number on Same Page
tBERASE
Block Erasing Time
tMBERASE
Multi-Block Erasing Time
tSR
Suspend Input to Ready
NW/E
Number Write/Erase Cycles
Min
Typ
Max
Unit
300 – 1000
5000
ms
10
Cycles
ms
6
6
100
6 – 12
6 – 12
130
ms
1.5
ms
2.5 x 105
Cycles
Notes
(1)
(2)
Note 1: Refer to the notification (16) toward the end of this document
Note 2: tMBERASE depends on the number of blocks to be erased (min 6 ms a 15 ms x Erase block number)
5
http://www.national.com
Schematic Cell Layout and Address Assignment
Programming is done in page units of 264 Bytes while the erase operation is carried out in blocks of 4 kBytes.
A page consists of 264 bytes in which 256 bytes are for main
memory and 8 bytes are for redundancy or other uses.
1 page e 264 bytes
1 Block e 264 bytes x 16 pages e (4k a 128) bytes
Total device density e (264 bytes) x (16 pages) x (512 block)
e 17.3 MBits (2.162 MBits)
The address is acquired through the I/O port using three consecutive cIock cycles as shown in Table I.
TL/D/11915 – 28
FIGURE 1. NM29N16 Schematic Cell Layout
TABLE I. Addressing
I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8
First Cycle
A0
A1
A2
A3
A4
A5
A6
A7
Second Cycle
A8
A9
A10
A11
A12
A13
A14
A15
Third Cycle
A16
A17
A18
A19
A20
*L
*L
*L
A0 –A7
A8 –A11
: Byte (Column) Address
: Page Address in Block
A12 –A20 : Block Address
* I/O 6–8 at the third cycle must be set low
Operation Mode: Logic and Command Tables
The operation modes such as Program, Erase, Read, Erase Suspend, and Reset are controlled by the twelve different command
operations shown in Table III. The Address, Command Input and Data Input/Output are controlled by the CLE, ALE, CE, WE, RE
and WP signals as shown in Table II.
TABLE II. Logic Table
CLE
ALE
CE
WE
RE
WP
Command Input
H
L
L
H
*
Data Input
L
L
L
H
*
Address Input
L
H
L
u
u
u
H
*
Address Output
L
H
L
H
*
Serial Data Output
L
L
L
H
v
v
During Programming (Busy)
*
*
*
*
*
H
During Erasing (Busy)
*
*
*
*
*
H
Program, Erase Inhibit
*
*
*
*
*
L
H: VIH, L: VIL
http://www.national.com
*: VIH or VIL
6
*
Operation Mode: Logic and Command Tables (Continued)
TABLE III. Command Table (HEX Data)
First Cycle
Sequential Data Input
80
Read Mode (1)
00
Read Mode (2)
50
Reset
FF
Auto Program
10
Auto Block Erase
60
Suspend in Erasing
B0
Resume
D0
Status Read
70
ID Read
90
Second Cycle
Acceptable Command
During Busy
Bit Assignment of HEX Data
(Example)
Yes
D0
TL/D/11915 – 84
Yes
Yes
Once the device is set into Read mode by ‘‘00H’’ or ‘‘50H’’ command, additional Read commands are not needed for sequential
page read operations. Table III shows the operation mode for Reads.
TABLE IV. Operation Mode for Reads
CLE ALE CE WE RE
I/O1 – I/O8
Power
Data Output
Active
Read Mode
L
L
L
H
L
Output Deselect
L
L
L
H
H High Impedance Active
Standby
L
L
H
H
* High Impedance Standby
Device Operation
READ MODE (1)
The Read mode (1) is set by issuing a ‘‘00H’’ command to the command register. Refer to Figure 2 below for timing details and
block diagram.
TL/D/11915 – 29
A data transfer operation from the cell array to the register starts at the rising
edge of WE in the third cycle (after latching the address information). The
device will be in a busy state during this transfer period.
After the transfer period the device returns to a ready state. Serial data can
be output synchronously with the RE clock from the designated starting
pointer indicated during the address input cycle.
TL/D/11915 – 30
FIGURE 2. Read Mode (1) Operation
7
http://www.national.com
Device Operation (Continued)
READ MODE (2)
The Read mode (2) is the same timing as Read mode (1) but it is used to access information in the extra 8 byte redundancy area
of the page. The starting pointer is therefore assigned between byte 256 and 263.
Address A0 –A2 are used to set the starting pointer for the redundant memory cell while A3 –A7 are ignored.
Once the ‘‘50H’’ command is set, the pointer moves to the redundant cell
locations and only those 8 cells can be addressed regardless of the A3 –A7
address.
(The ‘‘00H’’ command is necessary to move the pointer back to the
0–255, main memory cell locations.)
TL/D/11915 – 31
FIGURE 3. Read Mode (2) Operation
SEQUENTIAL READ (1) (2)
This mode allows sequential read without the additional address input
TL/D/11915 – 32
FIGURE 4. Sequential Read
Sequential Read mode (1) outputs the address 0 to 263 while Sequential Read mode (2) outputs the redundant address location
only. When the pointer reaches the last address, the device continues to output last data with each RE clcck signal.
http://www.national.com
8
Device Operation (Continued)
STATUS READ
The NM29N16S/R automatically implements the execution and verification of the program and erase operations. The status
read function is used to monitor the Ready/Busy status of the device, determines the pass/fail result of a program or erase
operation, and determines if the device is in a suspend or protect mode. The device status is output through the I/O port using
the RE clock after a ‘‘70H’’ command input. The resulting information is outlined in Table V.
TABLE V. Status Output Table
Status
Output
I/O 1
Pass/Fail
Pass: ‘‘0’’
I/O 2
Not Used
‘‘0’’
Fail : ‘‘1’’
I/O 3
Not Used
‘‘0’’
I/O 4
Not Used
‘‘0’’
I/O 5
Not Used
‘‘0’’
I/O 6
Suspend
Suspended: ‘‘1’’
I/O 7
Ready/Busy
Ready: ‘‘1’’
Busy: ‘‘0’’
I/O 8
Write Protect
Protect: ‘‘0’’
Not Protect: ‘‘l’’
Not suspended: ‘‘0’’
The Pass/Fail status in I/O 1 is only valid
when the device is in the Ready state.
The device will always indicate a Pass
status while in the Busy state at Read
mode.
Application example with multiple devices is shown in Figure 5 below.
TL/D/11915 – 33
FIGURE 5. Status Read Timing Application Example
Note: If the R/B pin signals of multiple devices are common-wired as shown in the diagram, the status Read function can be used to determine the status of each
individually selected device.
9
http://www.national.com
Device Operation (Continued)
AUTO PAGE PROGRAM
The NM29N16S/R implements the automatic page program operation by receiving a ‘‘10H’’ program command after the
address and data have been input. The sequence of command, address and data input is shown below. (Refer to the detail
timing chart).
TL/D/11915 – 34
The data is transferred (programmed) from the register to the selected page at the rising edge of WE
following the ‘‘10H’’ command input. The programmed data is transferred back to the register after programming to be automatically verified by the device. If the program does not succeed, the above program/
verify operation is repeated by the device until success or the maximum loop number set in the device.
TL/D/11915–35
FIGURE 6. Auto Page Program
AUTO BLOCK ERASE
The block erase operation starts with the rising edge of WE after the erase execution command ‘‘D0H’’ which follows the erase
setup command ‘‘60H’’. This two cycle process for erase operations acts as an extra layer protection from accidental erasure of
data due to possible external noise issues. The device automatically executes the erase and verify operations.
TL/D/11915 – 37
FIGURE 7. Auto Block Erase Operation
http://www.national.com
10
Device Operation (Continued)
SUSPEND/RESUME
Because an erase operation can keep the device in a busy state for an extended period of time, the NM29N16 has the ability to
suspend the erase operation to allow program or read operations to be performed on the device. The block diagram and
command sequence on this operation are shown as below. (Refer to the detail timing chart).
TL/D/11915 – 40
FIGURE 8. Suspend/Resume Erase Operation
The B0...D0 suspend/resume cycle can be repeated up to 20 times during an erase operation. After the resume command input,
the erase operation continues from the point at which it left off and does not have to restart.
11
http://www.national.com
Device Operation (Continued)
RESET
The reset mode compulsorily stops all operations. For example, in the case of a program or erase operation, the regulated
voltage is discharged to 0V and the device will go to a wait state. The address and data register are set as follows after a reset:
# Address Register:
# Data Register:
# Operation Mode:
All ‘‘0’’
All ‘‘1’’
Wait State
The response after ‘‘FFH’’ reset command input during each operation is as follows:
# In the case that reset (FFH) command is input during programming:
TL/D/11915 – 41
FIGURE 9. Reset During Programming
# In the case that reset (FFH) command is input during erasing:
TL/D/11915 – 42
FIGURE 10. Reset During Erasing
# In the case that reset (FFH) command is input during read operation:
TL/D/11915 – 43
FIGURE 11. Reset During Read
# In the case that reset (FFH) command is input during suspend:
TL/D/11915 – 44
FIGURE 12. Reset During Suspend
http://www.national.com
12
Device Operation (Continued)
# In the case that the status read command (70H) is input after reset:
TL/D/11915 – 45
FIGURE 13. Read After Reset
# However the following operation is prohibited. If the following operation is executed, set up for address and data register can
not be guaranteed.
TL/D/11915 – 46
FIGURE 14. Prohibited Reset
# In the case that the reset command is input in succession:
TL/D/11915 – 47
FIGURE 15. Consecutive Resets
ID READ
The NM29N16S/R contains an ID code to identify the device type and the manufacturer. The ID codes are read out using the
following timing conditions:
TL/D/11915 – 48
TABLE VI. Code Table
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
Hex Data
Maker Code
1
0
0
0
1
1
1
1
8FH
Device Code
0
1
1
0
0
1
0
0
64H
Refer to the timing specifications for the access time of tREAD, tCR, tAR2.
13
http://www.national.com
Timing Diagrams
Latch Timing Chart for Command/Address/Data
TL/D/11915 – 7
Command Input Cycle
TL/D/11915 – 8
Serial Read Cycle
TL/D/11915 – 26
http://www.national.com
14
Timing Diagrams (Continued)
Address Input Cycle
TL/D/11915 – 9
Data Input Cycle
TL/D/11915 – 10
15
http://www.national.com
Timing Diagrams (Continued)
Status Read Cycle
TL/D/11915 – 11
Read Cycle (1)
TL/D/11915 – 12
http://www.national.com
16
Timing Diagrams (Continued)
Read Cycle (1): Terminated by CE
TL/D/11915 – 13
Read Cycle (2)
TL/D/11915 – 14
17
http://www.national.com
Timing Diagrams (Continued)
Sequential Read Timing
TL/D/11915 – 15
Auto Program Timing Chart
TL/D/11915 – 16
http://www.national.com
18
Timing Diagrams (Continued)
Auto Program
TL/D/11915 – 17
Auto Block Erase Timing
TL/D/11915 – 19
19
http://www.national.com
Timing Diagrams (Continued)
ID Read Operation
TL/D/11915 – 24
Supplementary Device Operation
(1) PROHIBITION OF UNSPECIFIED COMMANDS
The operation commands are listed in Table III. Data input as a command other than the specified commands in Table III is
prohibited. Stored data may be corrupted if an unspeclfied command is entered during the command cycle.
(2) POINTER CONTROL FOR ‘‘00H’’, ‘‘50H’’
The NM29N16S/R has two read modes to set the destination of the pointer in either the maln memory area of a page or the
redundancy area. The pointer can be designated at any location between 0 and 255 in read mode (1) and between 256 and 263
in read mode (2). Figure 16 shows the block diagram of their operations.
TL/D/11915 – 49
FIGURE 16. Pointer Control
http://www.national.com
20
Supplementary Device Operation (Continued)
The pointer is set to region ‘‘A’’ by the ‘‘00H’’ command and to region ‘‘B’’ by the ‘‘50H’’ command.
(Example)
The ‘‘00H’’ command needs to be input to set the pointer back to region ‘‘A’’ when the pointer exists in region ‘‘B’’.
TL/D/11915 – 50
FIGURE 17. Example for Pointer Set
In case of programming into region ‘‘B’’ only by setting the start point in region ‘‘B’’ with ‘‘50H’’ command, it is necessary to reset
the content of data register to ‘‘1’’ by ‘‘FFH’’ command.
TL/D/11915 – 25
(3) ACCEPTABLE COMMANDS AFTER SERIAL INPUT COMMAND OF ‘‘80H’’
Once the serial input command (‘‘80H’’) is input, do not input any command other than the program execution command
(‘‘10H’’) or the reset command (‘‘FFH’’) during programming.
TL/D/11915 – 51
FIGURE 18. Reset After Serial Input
If a command other than ‘‘10H’’ or ‘‘FFH’’ is input, the program operation is not performed.
TL/D/11915 – 52
21
http://www.national.com
Supplementary Device Operation (Continued)
(4) STATUS READ DURING READ OPERATION
TL/D/11915 – 53
The device status can be read out by inputting the status read command ‘‘70H’’ during the read mode. Once the device is set to
the status read mode after the ‘‘70H’’ command input, the device does not return to the read mode. Therefore, the status read
during the read operation is prohibited. However, when the read command ‘‘00H’’ is input during [A], the status mode is reset,
then the device returns to the read mode. In this case, the data output starts from N address without address input.
(5) SUSPEND COMMAND ‘‘B0H’’
The following issues need to be observed when the device is interrupted by a ‘‘B0H’’ command during block erasing.
TL/D/11915 – 54
Although the device status changes from busy to ready after ‘‘B0H’’ is input, the following two cases cannot be recognized.
Ð After a ‘‘B0H’’ command input, Busy x Ready
Ð After an erase operation is finished with ‘‘D0H’’, Busy x Ready
Therefore, the device status needs to be checked to see whether or not the ‘‘B0H’’ command has been accepted by issuing a
‘‘70H’’ command after the device goes to ready.
The device responds as follows when a ‘‘D0H’’ command (Resume) is input instead of ‘‘70H’’.
Ð ‘‘B0H’’ has been accepted : Erase operation is executed. (The device is busy.)
Ð ‘‘B0H’’ has not been accepted. (Erase operation has been completed) : ‘‘D0H’’ command cannot be accepted. (The device
is in ready.)
Each case above is confirmed by monitoring the R/B signal.
(6) PROGRAM FAIL
TL/D/11915 – 55
FIGURE 19. Program Fail
When the programming result for the page address M is ‘‘Fail’’, do not try to program the page to address N in another block.
Because the previous input data is lost, the same sequence of ‘‘80H’’ command, address and data input is necessary.
http://www.national.com
22
Supplementary Device Operation (Continued)
(7) DATA TRANSFER
The data in page Address M cannot be automatically transferred to page address N. If the following sequence is executed, the
data will be inverted (i.e., ‘‘1’’ data will become ‘‘0’’ and ‘‘0’’ will become ‘‘1’’).
TL/D/11915 – 56
FIGURE 20. Page to Page Transfer
(8) BLOCK ERASE AFTER SUSPEND COMMAND ‘‘B0H’’
TL/D/11915 – 57
A block erase command is prohibited when the device has been suspended by inputting ‘‘B0H’’ during a block erase or multiblock erase operation. Only a program or read operation is allowed during this erase suspend interruption.
(9) INTERRUPTION OF AN ERASING BLOCK
After a ‘‘B0H’’ command input, neither a program nor a read operation is allowed for the accessed block which is currently in an
erase operation.
TL/D/11915 – 58
(10) R/B: TERMINATION FOR THE READY/BUSY PIN (R/B)
A pull-up resistor needs to be used for termination because the R/B buffer consists of an open drain circuit.
TL/D/11915 – 62
TL/D/11915 – 61
This data may vary by device. We recommend that you use this data as a
reference when selecting a resistor value.
TL/D/11915 – 63
FIGURE 21. Ready/Busy Pin Termination
23
http://www.national.com
Supplementary Device Operation (Continued)
(11) STATUS AFTER POWER ON
Although the device is set to read mode after power-up, the following sequence is recommended because each input signal may
not be stable at power on.
# Operation mode
# Address register
# Data register
# High voltage generation circuit
:
:
:
:
Read mode (1)
All ‘‘0’’
Indeterminacy
Off state
Recommended sequence
TL/D/11915 – 64
(12) POWER ON/OFF SEQUENCE
The WP signal is useful for protecting against data corruption at power on/off. The following timing is recommended:
TL/D/11915 – 65
FIGURE 22. NM29N16 Power On/Off Sequence
(13) NOTIFICATION FOR WP SIGNAL
The erase and program operations are reset when WP goes low. The WP signal must be kept at a high level before 80H/60H
commands may be input. If WP goes high after the 80H/60H commands are input, the program and erase operation cannot be
guaranteed.
Program
TL/D/11915 – 66
Erase
TL/D/11915 – 67
http://www.national.com
24
Supplementary Device Operation (Continued)
(14) IN THE CASE THAT 4 ADDRESS CYCLES ARE INPUT
Although the device may acquire the fourth address, it is ignored inside the chip.
At Read operation:
TL/D/11915 – 71
FIGURE 23
At programming operation:
TL/D/11915 – 72
FIGURE 24
(15) DIVIDED PROGRAM IN THE SAME PAGE (PARTIAL PAGE PROGRAM)
The device allows a page to be divided typically into 10 segments and to program each page segment selectively as follows:
TL/D/11915 – 73
FIGURE 25
Note: The input data of unprogrammed or previously programmed page segments must be ‘‘1’’. (i.e., Mask all page bytes outside the segment to be programmed
with ‘‘1’’ data.)
25
http://www.national.com
Supplementary Device Operation (Continued)
(16) UNUSABLE BLOCK IDENTIFICATION
The NM29N16 may contain unusable blocks. To simplify
identification, usable or good blocks leave the factory in the
erased state. On initial power up (after board assembly),
reading all the bytes in a usable block will result in FFH
being read out. Unusable or bad blocks will read out some
data other than FFH. These blocks should be mapped out
of the system and not used. The valid number of blocks is
as follows:
Number of good blocks
Min
Typ
Max
Unit
502
508
512
Block
TL/D/11915 – 83
C: Checkboard Pattern, AAH
C: Inverse Checkerboard Pattern, 55H
Blank Check: Usable blocks will read out ‘FFH’ for all bytes in block
TL/D/11915 – 4
FIGURE 26. Identification of Unusable Blocks at Initial Power Up
http://www.national.com
26
Supplementary Device Operation (Continued)
(17) ERROR IN PROGRAM OR ERASE OPERATION (FAIL AT STATUS READ)
The device may fail during a program or erase operation due to exceeding write/erase cycle limits, for example. The following
system architecture will enable high system reliability if a failure occurs:
Program
When the error happens in Block A, try to reprogram the data into another Block B by loading from an external buffer. Then,
prevent further system accesses to Block A (by creating a ‘‘bad block’’ table or other appropriate scheme).
TL/D/11915 – 75
Erase
When the error oocurs after an erase operation, prevent future accesses to this bad block (again by creating or updating a table
within the system or other appropriate scheme).
27
http://www.national.com
http://www.national.com
28
Physical Dimensions millimeters
Output Drawings
Plastic TSOP
Plastic Thin Small Outline Package (S)
Order Number NM29N16S
NS Package Number NMDA0044
29
http://www.national.com
NM29N16 16 MBit (2M x 8 Bit) CMOS NAND FLASH E2PROM
Physical Dimensions millimeters (Continued)
Output Drawings
Plastic TSOP
Reversed Plastic Thin Small Outline Package (R)
Order Number NM29N16R
NS Package Number NMDB0044
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
National Semiconductor
Corporation
1111 West Bardin Road
Arlington, TX 76017
Tel: 1(800) 272-9959
Fax: 1(800) 737-7018
http://www.national.com
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
National Semiconductor
Europe
Fax: a49 (0) 180-530 85 86
Email: europe.support @ nsc.com
Deutsch Tel: a49 (0) 180-530 85 85
English Tel: a49 (0) 180-532 78 32
Fran3ais Tel: a49 (0) 180-532 93 58
Italiano Tel: a49 (0) 180-534 16 80
National Semiconductor
Hong Kong Ltd.
13th Floor, Straight Block,
Ocean Centre, 5 Canton Rd.
Tsimshatsui, Kowloon
Hong Kong
Tel: (852) 2737-1600
Fax: (852) 2736-9960
National Semiconductor
Japan Ltd.
Tel: 81-043-299-2308
Fax: 81-043-299-2408
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.