M66257FP
5120 × 8-Bit × 2 Line Memory (FIFO)
REJ03F0251-0200
Rev.2.00
Sep 14, 2007
Description
The M66257FP is a high-speed line memory with a FIFO (First In First Out) structure of 5120-word × 8-bit double
configuration which uses high-performance silicon gate CMOS process technology.
It allows simultaneous output of 1-line delay data and 2-line delay data, and is most suitable for data correction over
multiple lines.
It has separate clock, enable and reset signals for write and read, and is most suitable as a buffer memory between
devices with different data processing throughput.
Features
•
•
•
•
•
•
•
•
Memory configuration:
5120 words × 8 bits × 2 (dynamic memory)
High-speed cycle:
25 ns (Min)
High-speed access:
18 ns (Max)
Output hold:
3 ns (Min)
Fully independent, asynchronous write and read operations
Output:
3 states
1-line delay
Q00 to Q07:
Q10 to Q17:
2-line delay
Application
Digital photocopiers, high-speed facsimile, laser beam printers.
Block Diagram
Data input
D0 to D7
Data output
Q00 to Q07
Data output
Q10 to Q17
27 26 25 24 23 22 21 20
2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17
WCK 30
Write
clock input
Memory array of
5120-word × 8-bit × 2 configuration
1-line delay data only memory/
2-line delay data only memory
(
)
Read control circuit
Write
reset input
Output buffer
Read address counter
WRES 31
Write address counter
WE 32
Write
enable input
Write control circuit
Input buffer
35 RE
Read
enable input
34 RRES
Read
reset input
33 RCK
Read
clock input
VCC 18
1 GND
VCC 28
19 GND
VCC 36
29 GND
REJ03F0251-0200 Rev.2.00 Sep 14, 2007
Page 1 of 12
M66257FP
Pin Arrangement
M66257FP
Data output
GND
Q00
Q01
Q02
Q03
Q04
Q05
Q06
Q07
Q10
Q11
Q12
Q13
Q14
Q15
Q16
Q17
VCC
1
36
2
35
3
34
4
33
5
32
6
31
7
30
8
29
9
28
10
27
11
26
12
25
13
24
14
23
15
22
16
21
17
20
18
19
VCC
RE
RRES
RCK
WE
WRES
WCK
GND
VCC
D0
D1
D2
D3
D4
D5
D6
D7
GND
(Top view)
Outline: PRSP0036GA-A (36P2R-A)
REJ03F0251-0200 Rev.2.00 Sep 14, 2007
Page 2 of 12
Read enable input
Read reset input
Read clock input
Write enable input
Write reset input
Write clock input
Data input
M66257FP
Absolute Maximum Ratings
(Ta = 0 to 70°C, unless otherwise noted)
Item
Supply voltage
Symbol
VCC
Input voltage
Output voltage
VI
VO
Power dissipation
Storage temperature
Pd
Tstg
Ratings
−0.5 to +7.0
Unit
V
−0.5 to VCC + 0.5
−0.5 to VCC + 0.5
V
V
660
−65 to 150
mW
°C
Conditions
A value based on
GND pin
Ta = 25°C
Recommended Operating Conditions
Supply voltage
Item
Symbol
VCC
Supply voltage
Operating ambient temperature
GND
Topr
Min
4.5
Typ
5
Max
5.5
Unit
V
0
0
70
V
°C
Electrical Characteristics
(Ta = 0 to 70°C, VCC = 5 V ± 10%, GND = 0 V, unless otherwise noted)
Item
"H" input voltage
Symbol
VIH
Min
2.0
Typ
Max
Unit
V
"L" input voltage
"H" output voltage
VIL
VOH
VCC − 0.8
0.8
V
V
"L" output voltage
"H" input current
VOL
IIH
0.55
1.0
V
µA
IOL = 4 mA
VI = VCC
WE, WRES, WCK,
RE, RRES, RCK,
D0 to D7
"L" input current
IIL
−1.0
µA
VI = GND
Off state "H" output current
IOZH
5.0
µA
VO = VCC
Off state "L" output current
Operating mean current dissipation
IOZL
ICC
−5.0
120
µA
mA
Input capacitance
CI
10
pF
VO = GND
VI = VCC, GND, Output open
tWCK, tRCK = 25 ns
f = 1 MHz
Off state output capacitance
CO
15
pF
f = 1 MHz
REJ03F0251-0200 Rev.2.00 Sep 14, 2007
Page 3 of 12
Test Conditions
IOH = −4 mA
WE, WRES, WCK,
RE, RRES, RCK,
D0 to D7
M66257FP
Function
When write enable input WE is "L", the contents of data inputs D0 to D7 are written into 1-line delay data only memory
in synchronization with rise edge of write clock input WCK. At this time, the write address counter of 1-line delay data
only memory is also incremented simultaneously.
The write functions given below are also performed in synchronization with rise edge of WCK.
When WE is "H", a write operation to 1-line delay data only memory is inhibited and the write address counter of 1-line
delay data only memory is stopped.
When write reset input WRES is "L", the write address counter of 1-line delay data only memory is initialized.
When read enable input RE is "L", the contents of 1-line delay data only memory are output to data outputs Q00 to Q07
and those of 2-line delay data only memory to data outputs Q10 to Q17 in synchronization with the rise of read clock
input RCK. At this time, the read address counters of 1-line and 2-line delay data only memories is also incremented
simultaneously.
Moreover, data of Q00 to Q07 are written into 2-line delay data only memory in synchronization with rise edge of RCK.
At this time, the write address of 2-line delay data only memory is incremented.
The read functions given below are also performed in synchronization with rise edge of RCK.
When RE is "H", a read operation from both of 1-line delay data only memory and 2-line delay data only memory is
inhibited and the read address counter of each memory is stopped. The outputs of Q00 to Q07 and Q10 to Q17 are in the
high impedance state.
Moreover, a write operation to 2-line delay data only memory is inhibited and the write address counter of 2-line delay
data only memory is stopped.
When read reset input RRES is "L", the read address counter of 1-line delay data only memory, and the write address
counter and read address counter of 2-line delay data only memory are initialized.
REJ03F0251-0200 Rev.2.00 Sep 14, 2007
Page 4 of 12
M66257FP
Switching Characteristics
(Ta = 0 to 70°C, VCC = 5 V ± 10%, GND = 0 V, unless otherwise noted)
Item
Symbol
Access time
tAC
Min
Typ
Max
18
Unit
ns
Output hold time
Output enable time
tOH
tOEN
3
3
18
ns
ns
Output disable time
tODIS
3
18
ns
Timing Conditions
(Ta = 0 to 70°C, VCC = 5 V ± 10%, GND = 0 V, unless otherwise noted)
Min
Typ
Max
Unit
Write clock (WCK) cycle
Write clock (WCK) "H" pulse width
Item
tWCK
tWCKH
Symbol
25
11
ns
ns
Write clock (WCK) "L" pulse width
Read clock (RCK) cycle
tWCKL
tRCK
11
25
ns
ns
Read clock (RCK) "H" pulse width
Read clock (RCK) "L" pulse width
tRCKH
tRCKL
11
11
ns
ns
Input data setup time to WCK
Input data hold time to WCK
tDS
tDH
7
3
ns
ns
Reset setup time to WCK or RCK
Reset hold time to WCK or RCK
tRESS
tRESH
7
3
ns
ns
Reset nonselect setup time to WCK or RCK
Reset nonselect hold time to WCK or RCK
tNRESS
tNRESH
7
3
ns
ns
WE setup time to WCK
WE hold time to WCK
tWES
tWEH
7
3
ns
ns
WE nonselect setup time to WCK
WE nonselect hold time to WCK
tNWES
tNWEH
7
3
ns
ns
RE setup time to RCK
RE hold time to RCK
tRES
tREH
7
3
ns
ns
RE nonselect setup time to RCK
RE nonselect hold time to RCK
tNRES
tNREH
7
3
ns
ns
Input pulse rise/fall time
Data hold time*
tr, tf
tH
20
20
ns
ms
Notes: Reset the IC after power is turned on.
* For 1-line access, the following should be satisfied:
WE "H" level period < 20 ms − 5120 tWCK − WRES "L" level period
RE "H" level period < 20 ms − 5120 tRCK − RRES "L" level period
REJ03F0251-0200 Rev.2.00 Sep 14, 2007
Page 5 of 12
M66257FP
Test Circuit
VCC
RL = 1 kΩ
Qn
SW1
CL = 30 pF: tAC, tOH
Qn
SW2
CL = 5 pF: tOEN, tODIS
RL = 1 kΩ
Input pulse level:
0 to 3 V
Input pulse rise/fall time: 3 ns
Decision voltage input:
1.3 V
Decision voltage output:
1.3 V (However, tODIS (LZ) is 10% of output amplitude and tODIS (HZ) is 90% of that for
decision)
The load capacitance CL includes the floating capacitance of connection and the input capacitance of probe.
Parameter
SW1
SW2
tODIS (LZ)
tODIS (HZ)
Closed
Open
Open
Closed
tOEN (ZL)
tOEN (ZH)
Closed
Open
Open
Closed
tODIS/tOEN Test Condition
3V
RCK
1.3 V
1.3 V
GND
3V
RE
GND
tODIS (HZ)
Q0n
Q1n
VOH
90%
1.3 V
tODIS (LZ)
Q0n
Q1n
tOEN (ZH)
tOEN (ZL)
1.3 V
10%
REJ03F0251-0200 Rev.2.00 Sep 14, 2007
Page 6 of 12
VOL
M66257FP
Operating Timing
Write Cycle
Cycle n
Cycle n + 1
Cycle n + 2
Disable cycle
Cycle n + 3
Cycle n + 4
WCK
tWCKH tWCKL tWEH tNWES
tWCK
tNWEH tWES
WE
tDS tDH
Dn
tDS tDH
(n)
(n + 1)
(n + 2)
(n + 4)
(n + 3)
WRES = "H"
Write Reset Cycle
Cycle n − 1
Cycle n
tWCK
tNRESH tRESS
Reset cycle
Cycle 0
Cycle 1
Cycle 2
WCK
tRESH tNRESS
WRES
Dn
tDS tDH
tDS tDH
(n − 1)
(n)
(0)
(1)
(2)
WE = "L"
REJ03F0251-0200 Rev.2.00 Sep 14, 2007
Page 7 of 12
M66257FP
Read Cycle
Cycle n
Cycle n + 1
Cycle n + 2
tRCK
tRCKH tRCKL
tREH tNRES
Disable cycle
Cycle n + 3
Cycle n + 4
RCK
tNREH
tRES
tAC
RE
tODIS
tOEN
Q0n
(n)
(n + 1)
HIGH-Z
(n + 2)
(n + 3)
(n + 4)
Q1n
tOH
RRES = "H"
Read Reset Cycle
Cycle n − 1
Cycle n
tRCK
tNRESH tRESS
Reset cycle
Cycle 0
Cycle 1
Cycle 2
RCK
tRESH tNRESS
RRES
tAC
Q0n
(n − 1)
(n)
(0)
(0)
(0)
(1)
Q1n
tON
tON
tON
RE = "L"
REJ03F0251-0200 Rev.2.00 Sep 14, 2007
Page 8 of 12
(2)
M66257FP
Note at WCK Stop
n cycle
n + 1 cycle
n cycle
Disable cycle
WCK
tWCK
tNWES
WE
Dn
tDS tDH
tDS tDH
(n)
(n)
Period of writing data (n)
into memory
Period of writing data (n)
into memory
WRES = "H"
Input data Dn of n cycle is read at the rising edge after WCK of n cycle. Writing operation starts in the "L" period of
WCK of n + 1 cycle and ends at the rising edge after n + 1 cycle.
To stop reading write data at n cycle, input WCK for up to the rising edge of n + 1 cycle.
When the cycle next to n cycle is a disable cycle, input of WCK for a cycle is required after a disable cycle as well.
REJ03F0251-0200 Rev.2.00 Sep 14, 2007
Page 9 of 12
M66257FP
Shortest Read of Data "n" Written in Cycle n
(Cycle n − 1 on read side should be started after end of cycle n + 1 on write side)
When the start of cycle n − 1 on read side is earlier than the end of cycle n + 1 on write side, output Qn of cycle n
becomes invalid. In the figure shown below, the read of cycle n − 1 is invalid.
Cycle n + 1
Cycle n
Cycle n + 2
Cycle n + 3
WCK
(n)
Dn
Cycle n − 2
(n + 1)
(n + 2)
Cycle n − 1
(n + 3)
Cycle n
RCK
Invalid
Qn
(n)
Longest Read of Data "n" Written in Cycle n: 1-line Delay
(Cycle n <1>* on read side should be started when cycle n <2>* on write is started)
Output Qn of n cycle <1>* can be read until the start of reading side n cycle <1> and the start of writing side n cycle
<2>* overlap each other.
Cycle n <1>*
Cycle 0 <2>*
Cycle n <2>*
WCK
Dn
(n − 1) <1>*
(n) <1>*
Cycle n <0>*
(0) <2>*
Cycle 0 <1>*
(n − 1) <2>*
(n) <2>*
Cycle n <1>*
RCK
Qn
(n − 1) <0>*
(n) <0>*
Note: <0>*, <1>* and <2>* indicates a line value.
REJ03F0251-0200 Rev.2.00 Sep 14, 2007
Page 10 of 12
(0) <1>*
(n − 1) <1>*
(n) <1>*
M66257FP
Application Example
Laplacian Filter Circuit for Correction of Resolution in the Secondary Scanning Direction
Q00
to
Q07
×2
1-line
delay
Subtractor
2N − (A + B)
B
Line (n + 1)
image data
D0
to
D7
Corrected
image data
×K
A
Line (n − 1)
image data
2-line
delay
Adder
A+B
Q10
to
Q17
Secondary scanning
direction
Adder
N + K {2N − (A + B) }
N
Line n image data
M66257
Primary scanning
direction
A
Line (n − 1)
N
Line n
B
Line (n + 1)
REJ03F0251-0200 Rev.2.00 Sep 14, 2007
Page 11 of 12
N' = N + K { (N − A) + (N − B) }
= N + K {2N − (A + B)}
K: Laplacian coefficient
M66257FP
Package Dimensions
JEITA Package Code
P-SSOP36-8.4x15-0.80
RENESAS Code
PRSP0036GA-A
Previous Code
36P2R-A
MASS[Typ.]
0.5g
E
19
*1
HE
36
F
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
1
18
Index mark
c
*2
D
A1
A
A2
*3
y
bp
L
e
Detail F
REJ03F0251-0200 Rev.2.00 Sep 14, 2007
Page 12 of 12
Reference
Symbol
D
E
A2
A
A1
bp
c
HE
e
y
L
Dimension in Millimeters
Min Nom Max
14.8 15.0 15.2
8.2 8.4 8.6
2.0
2.4
0.05
0.35 0.4 0.5
0.13 0.15 0.2
0°
10°
11.63 11.93 12.23
0.65 0.8 0.95
0.15
0.3 0.5 0.7
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