M62320P/FP 8-bit I/O Expander for I2C BUS REJ03D0863-0300 Rev.3.00 Mar 25, 2008 Description The M62320P/FP is a CMOS 8-bit I/O expander, which has serial to parallel and parallel to serial data converting functions. It can communicate with a microcontroller via few wiring thanks to the adoption of the two-line I2C BUS. Parallel data I/O terminal can be set to input or output mode alternatively in individual bits. Maximum 8 ICs can be connected to a bus by using three chip-select pins, so that it is possible to handle up to 64 bits data. Features • Simple two-line (SCL and SDA) communication with a microcontroller. • 8-bit data conversion between serial and parallel by I2C BUS. • Built-in power-on reset. Application I/O port expansion for a microcontroller. Data conversion between serial and parallel in microcontroller peripherals. Block Diagram CS0 CS1 CS2 16 15 14 Chip-select SCL 2 I2C Bus transceiver SDA 3 Output data 8 Input/output 8 I/O setting data latch Output data latch 8 VDD 13 GND 8 Shift register 8 Input data latch 8 Power-on reset 8 Input data I/O port 12 11 10 9 7 6 5 4 D7 D6 D5 D4 D3 D2 D1 D0 REJ03D0863-0300 Rev.3.00 Mar 25, 2008 Page 1 of 10 1 SO M62320P/FP Pin Arrangement M62320P/FP SO 1 16 CS0 SCL 2 15 CS1 SDA 3 14 CS2 D0 4 13 VDD D1 5 12 D7 D2 6 11 D6 D3 7 10 D5 GND 8 9 D4 (Top view) Outline: PRDP0016AA-A (16P4) PRSP0016DE-A (16P2N-A) Pin Description Pin No. 2 3 1 16 15 14 4 5 6 7 9 10 11 12 13 8 Pin Name SCL SDA SO CS0 CS1 CS2 D0 D1 D2 D3 D4 D5 D6 D7 VDD GND I/O Function Input Input/Output Output Input Serial clock input Serial data input/output Serial data output Chip select data input Input/Output Parallel data input/output — — Power supply GND REJ03D0863-0300 Rev.3.00 Mar 25, 2008 Page 2 of 10 M62320P/FP Absolute Maximum Ratings Item Supply voltage Input voltage Output voltage Output current "Low" Output current "High" Power dissipation Operating temperature Storage temperature Symbol VDD Vl VO IOH IOL Pd Topr Tstg Ratings –0.3 to +7.0 –0.3 to VDD + 0.3 –0.3 to VDD + 0.3 –5 to 0 0 to 30 1220 (P) / 980 (FP) –20 to +85 –40 to +125 Unit V V V mA mA mW °C °C Conditions D0 to D7 D0 to D7 Ta = 25°C Recommended Operating Conditions • Supply voltage: • Input high voltage: • Input low voltage: VDD = 3V to 5.5 V VIH = 0.7 VDD to VDD VIL = 0 to 0.2 VDD Electrical Characteristics (VDD = 5 V ± 10%, GND = 0 V, Ta = –20 to +85°C, unless otherwise noted) Item Circuit current Symbol IDD Input leak current Output low voltage (SDA) Input high voltage Input low voltage Output high voltage (D0 to D7) IILK VOL VIH VIL VOH Output low voltage (D0 to D7) VOL Output current "Low" (D0 to D7) IOL Min Limits Typ Max Unit — 0.05 0.5 mA VIH = VDD, VIL = GND, fSCL = 400 kHz — 0.1 1.0 µA VIH = VDD, VIL = GND, fSCL = stop –10 — 0.7 VDD — VDD – 0.4 VDD – 0.4 0 0 5 2.5 15 5 — — — — — — — — 10 5 25 10 10 0.4 — 0.2 VDD VDD VDD 0.4 0.4 — — — — µA V V V V REJ03D0863-0300 Rev.3.00 Mar 25, 2008 Page 3 of 10 V mA Conditions Isink = 3 mA IOH =–1 mA, VDD = 5 V IOH = –500 µA, VDD = 3 V IOL = 5 mA, VDD = 5 V IOL = 2.5 mA, VDD = 3 V VOL = 0.4V, VDD = 5 V VOL = 0.4 V, VDD = 3 V VOL = 1.0 V, VDD = 5 V VOL = 1.0 V, VDD = 3 V M62320P/FP I2C BUS Characteristics Limits Item Symbol Min Max Unit 0 4.7 4.0 100 — — kHz µs µs — — — µs µs µs — — 1000 300 — µs ns ns ns µs SCL clock frequency Free time: the bus must be free before a new transmission can start fSCL tBUF Hold time START Condition After this period, the first clock pulse is generated. Low period of the clock High period of the clock tHD:STA Set-up time for START condition Only relevant for a repeated START condition Data Hold time Data Set-up time Rise time of SDA and SCL signals Fall time of SDA and SCL signals Set-up time for STOP condition tSU:STA 4.7 4.0 4.7 tHD:DAT tSU:DAT tR tF tSU:STO 0 250 — — 4.0 Note: tLOW tHIGH Transmitter must internally provide at least a hold time to bridge the undefined region (300 ns max) of the falling edge of SCL. Timing Chart tR, tF tBUF VIH SDA VIL tHD:STA tSU:DAT tHD:DAT tSU:STA tSU:STO VIH SCL VIL tLOW tHIGH Start REJ03D0863-0300 Rev.3.00 Mar 25, 2008 Page 4 of 10 Start Stop Start M62320P/FP Functional Blocks I2C BUS Interface The I2C BUS interface recognizes start/stop conditions, a slave address and a write/read mode selection by receiving SDA, SCL, CS0, CS1 and CS2 signals and then the latch pulses, dedicated to each data latch are generated. Data Latch This IC has 3 types of data latch: the I/O setting data latch, the input data latch and the output data latch and each latch is controlled by the I2C BUS interface. • I/O setting data latch These latches set input- or output-state of each parallel data terminals (D0 to D7). They are set at the next byte after receiving the slave address byte in the write mode from the master. In case this latch is set to high, the data is transferred from the I2C BUS interface to the parallel data terminals. In the opposite transmission: from the parallel data terminals to the I2C BUS, it is set to low. • Output data latch In the write mode, the data from the I2C BUS to the parallel data terminals is latched. When the master transmits output data after a setting in write mode, the output data is taken into the latches. • Input data latch In the read mode, the data of parallel data terminals is latched in the input data latches. The input data is taken into the latches from the parallel data terminals on every 8th negative edge of SCL clock. The latched data is output to the master through the sift resistor. On the output terminal assigned by the I/O setting latch, the input data latch takes the state of the output terminal. Parallel Input/Output Port In case I/O setting latch is set to low (the input mode), each parallel terminal becomes hi-impedance and is able to accept an input. In another case I/O setting latch is set to high (output mode), each parallel terminal output a data according to the state of the output data latch. Power on Reset When power is turned on, each latch is reset and then the parallel data I/O terminals become hi-impedance (input mode). REJ03D0863-0300 Rev.3.00 Mar 25, 2008 Page 5 of 10 M62320P/FP Digital Data Format 1. Write mode: I2C BUS data input to parallel data output First S Slave address W A I/O setting A 8-bit data A 8-bit data A ….. A Last P A Last P 2. Read mode: Parallel data input to I2C BUS data output First S Slave address W A 8-bit data A 8-bit data A 8-bit data A ….. 8-bit data Transmission from Master (MCU etc.) to Slave (M62320) Transmission from Slave (M62320) to Master (MCU etc.) • S: Start condition While SCL level is high, SDA line level should be changed from high to low. • Slave address First MSB 0 Note: Last LSB 1 1 1 A2 A1 Chip select data MSB A2 A1 A0 Lower three bits (A0, A1, A2) are a programmable address. This IC is accessed only when the lower 3 bits data of slave address coincide with the data of CS0 to CS2. (refer to the right table) 0 0 0 : 1 LSB A0 0 0 1 : 1 0 1 0 : 1 Note: L = Low, H = High • W: Write (SDA = Low), R: Read (SDA = High) • A: Acknowledge bit • I/O setting data (I/O setting of parallel data I/O terminals.) First MSB P7 Note: Last LSB P6 P5 P4 P3 P2 P1 P0 DATA INPUT from parallel data terminals = Low DATA OUTPUT to parallel data terminals = High Each bit data corresponds to the I/O state of the parallel data terminals. • 8-bit data First MSB D7 Last LSB D6 D5 D4 D3 D2 D1 D0 • P: Stop condition While SCL level is high, SDA level should be changed from low to high. REJ03D0863-0300 Rev.3.00 Mar 25, 2008 Page 6 of 10 CS2 CS1 CS0 L L L : H L L H : H L H L : H M62320P/FP Functional Description All parallel data I/O terminals are set to the input-state after power-on. In case any terminals need to be set to the output state, the corresponding terminals should be set during the write mode. This setting is hold until a next setting. In the write mode, 8 bits data can be transmitted from the I2C BUS interface to the parallel ports continually after the slave address and I/O setting. In the read mode, 8 bits data can be transmitted from the parallel ports to the I2C BUS interface continually after the slave address setting. In the case of a changing between the write-and read-mode, the data must be transmitted again from the starting condition. • In a case of a data conversion from serial to parallel. Transmission from a master (MCU etc.) Transmission from a slave (M62320) Start condition Slave address SDA 0 1 1 1 SCL 1 2 3 4 I/O setting byte A2 A1 A0 5 6 0 7 A DATA P7 P6 P5 P4 P3 P2 P1 P0 8 1 2 3 4 5 6 7 A D17 D16 D15 D14 D13 D12 D11 D10 A D27 D26 D25 D24 D23 D22 D21 D20 A 8 Data output D0 to D7 Stop condition DATA Data output D1X Hi-Z D2X • In a case of a data conversion from parallel to serial. All I/O setting resistors are set to low (input) in the write mode, before a parallel data is read. (All I/O setting resistors are set to the input mode after power-on). Transmission from a master (MCU etc.) Transmission from a slave (M62320) Start condition Slave address SDA 0 1 1 1 SCL 1 2 3 4 D0 to D7 output A2 A1 A0 5 6 0 7 A P7 P6 P5 P4 P3 P2 P1 P0 8 1 2 3 4 5 6 7 A 8 Hi-Z Start condition Slave address SDA 0 1 1 1 SCL 1 2 3 4 D0 to D7 input (example) D0 to D7 output I/O setting byte DATA A2 A1 A0 5 6 7 1 8 DATA DATA A D17 D16 D15 D14 D13 D12 D11 D10 A D37 D36 D35 D34 D33 D32 D31 D30 A D47 D46 D45 D44 D43 D42 D41 D40 A 1 2 3 D1X 4 5 D2X Data latch Hi-Z REJ03D0863-0300 Rev.3.00 Mar 25, 2008 Page 7 of 10 6 7 8 D3X Data latch D4X Data latch Stop condition M62320P/FP • In case the I/O setting is different between each terminals. An example: the parallel port terminals of D0 to D3 and D4 to D7 are assigned as output and input terminals, respectively. Start condition I/O setting DATA P7 P6 P5 P4 P3 P2 P1 P0 A D17 D16 D15 D14 D13 D12 D11 D10 A Slave address SDA 0 1 1 1 SCL 1 2 3 4 A2 A1 A0 5 6 0 7 A 8 1 2 3 4 5 6 7 D27 D26 D25 D24 D23 D22 D21 D20 A 8 Data output D0 to D3 Hi-Z D4 to D7 Hi-Z Stop condition DATA Data output D1X Start condition DATA Slave address SDA 0 1 1 1 SCL 1 2 3 4 A2 A1 A0 5 6 7 1 DATA DATA D2X Stop condition A D17 D16 D15 D14 D13 D12 D11 D10 A D37 D36 D35 D34 D33 D32 D31 D30 A D47 D46 D45 D44 D43 D42 D41 D40 A 8 1 2 3 4 5 6 7 8 D0 to D3 D4 to D7 (instance) D1X Data latch D4 to D7 output D2X D3X Data latch D4X Data latch Hi-Z • Write mode The terminal assigned as an output provides the data written in the output data latch. After power-on, all terminals are reset to the input-state. Then an initial data low of the output latch are output after the I/O setting has been done. Finally the assigned output are provided after the 8-bit data transmission. The terminal assigned as an input keeps the input condition (high-impedance) regardless of 8-bit data setting. • Read mode The input data is taken into the input latch on every 8th negative-going edge of the SCL clock through the terminal assigned as an input, and then the latched data is output via the SDA line. The data of the output assigned terminal is also handled in the same procedures as above. REJ03D0863-0300 Rev.3.00 Mar 25, 2008 Page 8 of 10 M62320P/FP Typical Application 10 µF 13 VDD Chip select data 14 CS2 15 CS1 16 CS0 2 SCL 3 SDA D0 4 D1 5 D2 6 D3 7 D4 9 D5 10 D6 11 D7 12 SO 1 Parallel input/ output terminal MCU Serial data output GND 10 Precaution for Use • Purchase of Renesas’s I2C components conveys a license under the Philips I2C Patent Rights to use these components an I2C system, provided that the system conforms to I2C Standard Specification as defined by Philips. REJ03D0863-0300 Rev.3.00 Mar 25, 2008 Page 9 of 10 M62320P/FP Package Dimensions RENESAS Code PRDP0016AA-A Previous Code 16P4 MASS[Typ.] 1.0g 9 1 8 c *1 E 16 e1 JEITA Package Code P-DIP16-6.3x19-2.54 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. *2 D e1 D E A A1 A2 bp b2 b3 c L A1 A A2 Reference Symbol *3 e *3 bp b3 b2 SEATING PLANE e L JEITA Package Code P-SOP16-5.3x10.1-1.27 RENESAS Code PRSP0016DE-A Previous Code 16P2N-A Min 7.32 18.8 6.15 Nom 7.62 19.0 6.3 Max 7.92 19.2 6.45 4.5 0.51 0.4 0.9 1.4 0.22 0° 2.29 3.0 3.3 0.5 1.0 1.5 0.27 2.54 0.6 1.3 1.8 0.34 15° 2.79 MASS[Typ.] 0.2g E 9 *1 HE 16 Dimension in Millimeters F NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 1 8 Index mark A2 A1 c D Reference Symbol L A *2 e y *3 bp Detail F D E A2 A1 A bp c HE e y L REJ03D0863-0300 Rev.3.00 Mar 25, 2008 Page 10 of 10 Dimension in Millimeters Min Nom Max 10.0 10.1 10.2 5.2 5.3 5.4 1.8 0.1 0.2 0 2.1 0.35 0.4 0.5 0.18 0.2 0.25 0° 8° 7.5 7.8 8.1 1.12 1.27 1.42 0.1 0.4 0.6 0.8 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. 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