MITSUBISHI
MITSUBISHI
〈DIGITAL
〈DIGITAL
ASSP〉
ASSP〉
M66257FP
M66257FP
5120
× 8-BIT
2 LINE
MEMORY
(FIFO)
5120
× 8-BIT
× 2×LINE
MEMORY
(FIFO)
DESCRIPTION
The M66257FP is a high-speed line memory with a FIFO
(First In First Out) structure of 5120-word × 8-bit double configuration which uses high-performance silicon gate CMOS
process technology.
It allows simultaneous output of 1-line delay data and 2-line
delay data, and is most suitable for data correction over multiple lines.
It has separate clock, enable and reset signals for write and
read, and is most suitable as a buffer memory between devices with different data processing throughput.
GND
1
READ ENABLE INPUT
Q01 ← 3
34 ← RRES
READ RESET INPUT
Q02 ← 4
33 ← RCK
READ CLOCK INPUT
Q03 ← 5
32 ← WE
WRITE ENABLE INPUT
Q04 ← 6
31 ← WRES
WRITE RESET INPUT
Q05 ← 7
30 ← WCK
WRITE CLOCK INPUT
Q07 ← 9
Q10 ← 10
Q11 ← 11
APPLICATION
Digital photocopiers, high-speed facsimile, laser beam printers.
VCC
35 ← RE
Q06 ← 8
DATA OUTPUT
36
Q00 ← 2
M66257FP
FEATURES
• Memory configuration of 5120 words × 8 bits × 2 (dynamic
memory)
• High-speed cycle ............................................. 25ns (Min.)
• High-speed access ......................................... 18ns (Max.)
• Output hold ........................................................ 3ns (Min.)
• Fully independent, asynchronous write and read operations
• Output .................................................................... 3 states
• Q00 to Q07 ........................................................ 1-line delay
• Q10 to Q17 ........................................................ 2-line delay
PIN CONFIGURATION (TOP VIEW)
29
GND
28
VCC
27 ← D0
26 ← D1
Q12 ← 12
25 ← D2
Q13 ← 13
24 ← D3
Q14 ← 14
23 ← D4
Q15 ← 15
22 ← D5
Q16 ← 16
21 ← D6
Q17 ← 17
20 ← D7
VCC
19
18
DATA INPUT
GND
Outline 36P2R-A
BLOCK DIAGRAM
WRITE
CLOCK INPUT
WCK 30
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
INPUT BUFFER
OUTPUT BUFFER
MEMORY ARRAY OF
5120-WORD × 8-BIT × 2 CONFIGURATION
1-LINE DELAY DATA ONLY MEMORY/
2-LINE DELAY DATA ONLY MEMORY
READ CONTROL CIRCUIT
WRITE
RESET INPUT WRES 31
DATA OUTPUT
Q10 ~ Q17
READ ADDRESS COUNTER
WE 32
DATA OUTPUT
Q00 ~ Q07
27 26 25 24 23 22 21 20
WRITE ADDRESS COUNTER
WRITE
ENABLE INPUT
WRITE CONTROL CIRCUIT
DATA INPUT
D0 ~ D7
35 RE
READ
ENABLE INPUT
READ
34 RRES RESET INPUT
33 RCK
VCC 18
1 GND
VCC 28
19 GND
VCC 36
29 GND
READ
CLOCK INPUT
1
MITSUBISHI 〈DIGITAL ASSP〉
M66257FP
5120 × 8-BIT × 2 LINE MEMORY (FIFO)
FUNCTION
When write enable input WE is “L”, the contents of data inputs
D0 to D7 are written into 1-line delay data only memory in synchronization with rise edge of write clock input WCK. At this
time, the write address counter of 1-line delay data only
memory is also incremented simultaneously.
The write functions given below are also performed in synchronization with rise edge of WCK.
When WE is “H”, a write operation to 1-line delay data only
memory is inhibited and the write address counter of 1-line
delay data only memory is stopped.
When write reset input WRES is “L”, the write address counter
of 1-line delay data only memory is initialized.
When read enable input RE is “L”, the contents of 1-line delay
data only memory are output to data outputs Q00 to Q07 and
those of 2-line delay data only memory to data outputs Q10 to
Q17 in synchronization with the rise of read clock input RCK.
At this time, the read address counters of 1-line and 2-line
delay data only memories is also incremented simultaneously.
2
Moreover, data of Q00 to Q07 are written into 2-line delay data
only memory in synchronization with rise edge of RCK. At
this time, the write address of 2-line delay data only memory
is incremented.
The read functions given below are also performed in synchronization with rise edge of RCK.
When RE is “H”, a read operation from both of 1-line delay
data only memory and 2-line delay data only memory is inhibited and the read address counter of each memory is
stopped. The outputs of Q00 to Q07 and Q10 to Q17 are in the
high impedance state.
Moreover, a write operation to 2-line delay data only memory
is inhibited and the write address counter of 2-line delay data
only memory is stopped.
When read reset input RRES is “L”, the read address counter
of 1-line delay data only memory, and the write address
counter and read address counter of 2-line delay data only
memory are initialized.
MITSUBISHI 〈DIGITAL ASSP〉
M66257FP
5120 × 8-BIT × 2 LINE MEMORY (FIFO)
ABSOLUTE MAXIMUM RATINGS (Ta = 0 ~ 70°C, unless otherwise noted)
Symbol
VCC
VI
VO
Pd
Tstg
Parameter
Supply voltage
Input voltage
Output voltage
Maximum power dissipation
Storage temperature
Conditions
Ratings
–0.5 ~ +7.0
–0.5 ~ VCC + 0.5
–0.5 ~ VCC + 0.5
660
–65 ~ 150
A value based on GND pin
Ta = 25°C
Unit
V
V
V
mW
°C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
GND
Topr
Parameter
Min.
4.5
Supply voltage
Supply voltage
Operating ambient temperature
Limits
Typ.
5
0
Unit
Max.
5.5
0
V
V
°C
70
ELECTRICAL CHARACTERISTICS (Ta = 0 ~ 70°C, VCC = 5V ± 10%, GND = 0V, unless otherwise noted)
Symbol
VIH
VIL
VOH
VOL
Parameter
“H” input voltage
“L” input voltage
“H” output voltage
“L” output voltage
Test conditions
IOH = –4mA
IOL = 4mA
Max.
WE, WRES, WCK, RE,
RRES, RCK,
D0 ~ D7
WE, WRES, WCK, RE,
RRES, RCK,
D0 ~ D7
VI = VCC
IIL
“L” input current
VI = GND
IOZH
IOZL
Off state “H” output current
Off state “L” output current
Operating mean current dissipation
Input capacitance
Off state output capacitance
VO = VCC
VO = GND
VI = VCC, GND, Output open
tWCK, tRCK = 25ns
f = 1MHz
f = 1MHz
Unit
0.55
V
V
V
V
1.0
mA
–1.0
mA
5.0
–5.0
mA
mA
120
mA
10
15
pF
pF
VCC–0.8
“H” input current
CI
CO
Limits
Typ.
0.8
IIH
ICC
Min.
2.0
3
MITSUBISHI 〈DIGITAL ASSP〉
M66257FP
5120 × 8-BIT × 2 LINE MEMORY (FIFO)
SWITCHING CHARACTERISTICS (Ta = 0 ~ 70°C, VCC = 5V ± 10%, GND = 0V, unless otherwise noted)
Symbol
tAC
tOH
tOEN
tODIS
Parameter
Access time
Output hold time
Output enable time
Output disable time
Min.
Limits
Typ.
3
3
3
Max.
18
18
18
Unit
ns
ns
ns
ns
TIMING CONDITIONS (Ta = 0 ~ 70°C, VCC = 5V ± 10%, GND = 0V, unless otherwise noted)
Symbol
tWCK
tWCKH
tWCKL
tRCK
tRCKH
tRCKL
tDS
tDH
tRESS
tRESH
tNRESS
tNRESH
tWES
tWEH
tNWES
tNWEH
tRES
tREH
tNRES
tNREH
tr, tf
tH
Parameter
Write clock (WCK) cycle
Write clock (WCK) “H” pulse width
Write clock (WCK) “L” pulse width
Read clock (RCK) cycle
Read clock (RCK) “H” pulse width
Read clock (RCK) “L” pulse width
Input data setup time to WCK
Input data hold time to WCK
Reset setup time to WCK or RCK
Reset hold time to WCK or RCK
Reset nonselect setup time to WCK or RCK
Reset nonselect hold time to WCK or RCK
WE setup time to WCK
WE hold time to WCK
WE nonselect setup time to WCK
WE nonselect hold time to WCK
RE setup time to RCK
RE hold time to RCK
RE nonselect setup time to RCK
RE nonselect hold time to RCK
Input pulse rise/fall time
Data hold time (Note 1)
Note 1: For 1-line access, the following should be satisfied:
WE “H” level period < 20ms – 5120 tWCK – WRES “L” level period
RE “H” level period < 20ms – 5120 tRCK – RRES “L” level period
2: Reset the IC after power is turned on.
4
Min.
25
11
11
25
11
11
7
3
7
3
7
3
7
3
7
3
7
3
7
3
Limits
Typ.
Max.
20
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
MITSUBISHI 〈DIGITAL ASSP〉
M66257FP
5120 × 8-BIT × 2 LINE MEMORY (FIFO)
TEST CIRCUIT
VCC
RL=1kΩ
Qn
SW1
CL=30pF : tAC, tOH
Qn
SW2
CL=5pF : tOEN, tODIS
RL=1kΩ
Input pulse level
:
Input pulse rise/fall time :
Decision voltage input :
Decision voltage output :
0 ~ 3V
3ns
1.3V
1.3V (However, tODIS(LZ) is 10% of output amplitude and tODIS(HZ) is 90% of
that for decision).
The load capacitance CL includes the floating capacitance of connection and the input capacitance of
probe.
Parameter
tODIS(LZ)
tODIS(HZ)
tOEN(ZL)
tOEN(ZH)
SW1
Closed
Open
Closed
Open
SW2
Open
Closed
Open
Closed
tODIS/tOEN TEST CONDITION
3V
RCK
1.3V
1.3V
GND
3V
RE
GND
tODIS(HZ)
tOEN(ZH)
1.3V
tODIS(LZ)
Q0n
Q1n
VOH
90%
Q0n
Q1n
tOEN(ZL)
1.3V
10%
VOL
5
MITSUBISHI 〈DIGITAL ASSP〉
M66257FP
5120 × 8-BIT × 2 LINE MEMORY (FIFO)
OPERATING TIMING
• Write cycle
Cycle n
Cycle n+1
Cycle n+2
tWCK
tWCKH tWCKL
Disable cycle
Cycle n+3
Cycle n+4
WCK
tWEH
tNWES
tNWEH
tWES
WE
tDS tDH
tDS tDH
(n)
Dn
( n+1)
(n+2)
(n+3)
(n+4)
WRES = “H”
• Write reset cycle
Cycle n–1
Cycle n
Reset cycle
tWCK
tNRESH tRESS
Cycle 0
Cycle 1
Cycle 2
WCK
tRESH
tNRESS
WRES
Dn
tDS tDH
tDS tDH
(n–1)
(n)
(0)
(1)
WE = “L”
6
(2)
MITSUBISHI 〈DIGITAL ASSP〉
M66257FP
5120 × 8-BIT × 2 LINE MEMORY (FIFO)
• Read cycle
Cycle n
Cycle n+1
Cycle n+2
Disable cycle
Cycle n+3
Cycle n+4
RCK
tRCK
tRCKH
tRCKL
tREH
tNRES
tNREH
tRES
tAC
RE
tODIS
tOEN
Q0n
HIGH-Z
(n)
(n+1)
(n+2)
(n+3)
(n+4)
Q1n
tOH
RRES = “H”
• Read reset cycle
Cycle n–1
Cycle n
tRCK
tNRESH tRESS
Reset cycle
Cycle 0
Cycle 1
Cycle 2
RCK
tRESH tNRESS
RRES
tAC
Q0n
(n–1)
(n)
(0)
(0)
(0)
(1)
(2)
Q1n
tON
tON
tON
RE = “L”
7
MITSUBISHI 〈DIGITAL ASSP〉
M66257FP
5120 × 8-BIT × 2 LINE MEMORY (FIFO)
• Note at WCK stop
n cycle
n+1 cycle
n cycle
Disable cycle
WCK
tNWES
tWCK
WE
Dn
tDS tDH
tDS tDH
(n)
(n)
Period of writing data (n)
into memory
Period of writing data (n)
into memory
WRES = “H”
Input data Dn of n cycle is read at the rising edge after WCK of n cycle. Writing operation starts in the “L” period of WCK of n+1
cycle and ends at the rising edge after n+1 cycle.
To stop reading write data at n cycle, input WCK for up to the rising edge of n+1 cycle.
When the cycle next to n cycle is a disable cycle, input of WCK for a cycle is required after a disable cycle as well.
8
MITSUBISHI 〈DIGITAL ASSP〉
M66257FP
5120 × 8-BIT × 2 LINE MEMORY (FIFO)
• Shortest read of data “n” written in cycle n
Cycle n–1 on read side should be started after end of cycle n+1 on write side
When the start of cycle n–1 on read side is earlier than the end of cycle n+1 on write side, output Q n of cycle n becomes invalid.
In the figure shown below, the read of cycle n–1 is invalid.
Cycle n
Cycle n+1
Cycle n+2
Cycle n+3
WCK
(n)
Dn
(n+1)
Cycle n–2
(n+2)
Cycle n–1
(n+3)
Cycle n
RCK
Qn
invalid
(n)
• Longest read of data “n” written in cycle n: 1-line delay
Cycle n <1>* on read side should be started when cycle n <2>* on write is started
Output Qn of n cycle <1>* can be read until the start of reading side n cycle <1> and the start of writing side n cycle <2>* overlap each other.
Cycle n <1>*
Cycle 0 <2>*
Cycle n <2>*
WCK
Dn
(n–1)<1>*
(n)<1>*
Cycle n <0>*
(0) <2>*
(n–1)<2>*
Cycle 0 <1>*
(n)<2>*
Cycle n <1>*
RCK
Qn
(n–1)<0>*
(n)<0>*
(0)<1>*
(n–1)<1>*
(n)<1>*
<0>*, <1>* and <2>* indicates a line value.
9
MITSUBISHI 〈DIGITAL ASSP〉
M66257FP
5120 × 8-BIT × 2 LINE MEMORY (FIFO)
APPLICATION EXAMPLE
Laplacian Filter Circuit for Correction of Resolution in the Secondary Scanning Direction.
N
Line n image data
M66257
Q00
D7
Q07
×2
Adder
N+K {2N–(A+B)}
B
Line (n+1)
image data
D0
Subtractor
2N–(A+B)
1-line
delay
Q17
Secondary scanning
direction
2-line
delay
10
A
Line (n–1)
image data
Adder
A+B
Q10
×K
Primary scanning
direction
A
Line (n–1)
N
Line n
B
Line (n+1)
N' = N+K { (N–A)+(N–B)}
= N+K { 2N–(A+B)}
K : Laplacean coefficient
Corrected
image data