HD151TS304RP Spread Spectrum Clock for EMI Solution REJ03D0812-0600 (Previous: ADE-205-657E) Rev.6.00 Apr 07, 2006 Description The HD151TS304 is a high-performance Spread Spectrum Clock modulator. It is suitable for low EMI solution. Features • • • • Supports 10 MHz to 60 MHz operation. (Designed for XIN = 24 MHz and 48 MHz) 1 copy of clock out with spread spectrum modulation @3.3 V 1 copy of reference clock @3.3 V Programmable spread spectrum modulation (±0.25%, ±0.5%, ±1.5% central spread modulation and spread spectrum disable mode.) • SOP–8pin • Pin to pin compatible with HD151TS301RP • Ordering Information Part Name HD151TS304RPEL Package Type SOP-8 pin (JEDEC) Key Specifications • • • • Supply voltages : VDD = 3.3 V±0.165 V Ta = 0 to 70°C operating range Clock output duty cycle = 50±5% Cycle to cycle jitter = ±250 ps typ. Rev.6.00 Apr 07, 2006 page 1 of 9 Package Code (Previous code) PRSP0008DD-C (FP-8DCV) Package Abbreviation RP Taping Abbreviation (Quantity) EL (2,500 pcs / Reel) HD151TS304RP Block Diagram VDD GND CLKOUT XIN OSC 1/m SSCCLKOUT Synthesizer XOUT R=1 MΩ 1/n SSC Modulator SEL0 R=100 kΩ Mode Control SEL1 R=100 kΩ Pin Arrangement SSCCLKOUT 1 8 SEL1 VDD 2 7 CLKOUT GND 3 6 SEL0 XIN 4 5 XOUT (Top view) SSC Function Table SEL1 :0 00 01 10 11 Note: ±1.5% SSC is selected for default by internal pull-up & down resistors. Rev.6.00 Apr 07, 2006 page 2 of 9 Spread Percentage ±0.5% ±1.5% SSC OFF ±0.25% HD151TS304RP Clock Frequency Table XIN (MHz) 48 24 SSCCLKOUT (MHz) 48*1 24*1 CLKOUT (MHz) 48*2 24*2 Notes: 1. With spread spectrum modulation. 2. Without spread spectrum modulation. Pin Descriptions Pin name GND VDD CLKOUT SSCCLKOUT XIN XOUT SEL0 No. 3 2 7 1 4 5 6 Type Ground Power Output Output Input Output Input SEL1 8 Input Description GND pin Power supplies pin. Normally 3.3 V. Normally 3.3 V reference clock output. Spread spectrum modulated clock output. Oscillator input. Oscillator output. SSC mode select pin. LVCMOS level input. Pull-up by internal resistor. (100 kΩ). SSC mode select pin. LVCMOS level input. Pull–down by internal resistor (100 kΩ). Absolute Maximum Ratings Item Supply voltage Input voltage Output voltage *1 Input clamp current Output clamp current Continuous output current Symbol VDD VI VO IIK IOK IO Maximum power dissipation at Ta = 55°C (in still air) Storage temperature Notes: Tstg Ratings –0.5 to 4.6 –0.5 to 4.6 –0.5 to VDD+0.5 –50 –50 ±50 Unit V V V mA mA mA 0.7 W –65 to +150 °C Conditions VI < 0 VO < 0 VO = 0 to VDD Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. Recommended Operating Conditions Item Supply voltage DC input signal voltage High level input voltage Low level input voltage Operating temperature Input clock duty cycle Rev.6.00 Apr 07, 2006 page 3 of 9 Symbol VDD VIH VIL Ta Min 3.135 –0.3 2.0 –0.3 0 45 Typ 3.3 — — — — 50 Max 3.465 VDD+0.3 VDD+0.3 0.8 70 55 Unit V V V V °C % Conditions HD151TS304RP DC Electrical Characteristics Ta = 0 to 70°C, VDD = 3.3 V±5% Item Input low voltage Input high voltage Input current Input slew rate Input capacitance Operating current Symbol VIL VIH II CI Min — 2.0 — Typ — — — Max 0.8 — ±10 — — ±100 1 — — — — 7 4 4 — Unit V V µA V / ns pF mA Test Conditions VI = 0 V or 3.465 V, VDD = 3.465 V, XIN pin VI = 0 V or 3.465 V, VDD = 3.465 V, SEL0, SEL1 pins 20% – 80% SEL0, SEL1 XIN = 24 MHz, CL = 0 pF, VDD = 3.3 V DC Electrical Characteristics / Clock Output & SSC Clock Output Ta = 0 to 70°C, VDD = 3.3 V±5% Item Output voltage Output current *1 Note: Symbol VOH VOL IOH IOL Min 3.1 — — — Typ — — –40 40 Max — 50 — — Unit V mV mA 1. Parameters are target of design. Not 100% tested in production. Rev.6.00 Apr 07, 2006 page 4 of 9 Test Conditions IOH = –1 mA, VDD = 3.3 V IOL = 1 mA, VDD = 3.3 V VOH = 1.5 V VOL = 1.5 V HD151TS304RP AC Electrical Characteristics / Clock Output & SSC Clock Output Ta = 25°C, VDD = 3.3 V, CL = 30 pF Item *1, 2 Cycle to cycle jitter Output frequency Symbol tCCS *1, 2 Min — Typ | 250 | Max | 300 | — | 250 | | 300 | — | 250 | | 300 | — | 250 | | 300 | — | 250 | | 300 | — | 250 | | 300 | — | 250 | | 300 | 23.8 — 24.2 47.3 — 48.7 23.7 — 24.3 47.2 — 48.8 23.4 — 24.6 46.6 — 49.4 23.8 — 24.2 47.3 — 48.7 Unit ps MHz *1 Test Conditions SSCCLKOUT, 24 MHz SSCCLKOUT, 48 MHz SSCCLKOUT, 24 MHz SSCCLKOUT, 48 MHz SSCCLKOUT, 24 MHz SSCCLKOUT, 48 MHz CLKOUT, 24 MHz & 48MHz SSCCLKOUT, XIN = 24 MHz SSCCLKOUT, XIN = 48 MHz SSCCLKOUT, XIN = 24 MHz SSCCLKOUT, XIN = 48 MHz SSCCLKOUT, XIN = 24 MHz SSCCLKOUT, XIN = 48 MHz CLKOUT, 24 MHz CLKOUT, 48 MHz @48 MHz CLKOUT Notes SSCOFF SEL1:0 = 10 Figure 1 SSC= ±0.25% SEL1:0 = 11 Figure 1 SSC= ±1.5% SEL1:0 = 01 Figure1 Figure1 SSCOFF SEL1:0 = 10 SSC= ±0.25% SEL1:0 = 11 SSC= ±1.5% SEL1:0 = 01 Slew rate tSL 1.0 — — V/ns 0.4 V to 2.4 V *1 Clock duty cycle 45 50 55 % *1 Output impedance — 30 — Ω — 33 — KHz @48 MHz Spread spectrum *1 SSCCLKOUT modulation frequency Input clock frequency 10 — 60 MHz *1,3 Stabilization time — — 2 ms Notes: 1. Parameters are target of design. Not 100% tested in production. 2. Cycle to cycle jitter and output frequency are included spread spectrum modulation. 3. Stabilization time is the time required for the integrated circuit to obtain phase lock of its input signal after power up. SSCCLKOUT (or CLKOUT) tcycle n tcycle n+1 t CCS = (tcycle n) - (tcycle n+1) Figure 1 Cycle to cycle jitter Rev.6.00 Apr 07, 2006 page 5 of 9 HD151TS304RP Application Information 1. Recommended Circuit Configuration The power supply circuit of the optimal performance on the application of a system should refer to Fig. 2. VDD decoupling is important to both reduce Jitter and EMI radiation. The C1 decoupling capacitor should be placed as close to the VDD pin as possible, otherwise the increased trace inductance will negate its decoupling capability. The C2 decoupling capacitor shown should be a tantalum type. R1 SSCCLKOUT 1 VDD 2 8 SEL1 R2 C2 7 CLKOUT C1 3 6 SEL0 TS300 Series GND GND 4 5 GND Notes: XIN XOUT (Crystal or Reference input) (Crystal or Not connection) C1 = High frequency supply decoupling capacitor. (0.1 µF recommended) C2 = Low frequency supply decoupling capacitor. (22 µF tantalum type recommended) R1, R2 = Match value to line impedance. (22 Ω Reference value) Figure 2 Recommended circuit configuration Rev.6.00 Apr 07, 2006 page 6 of 9 HD151TS304RP 2. Example Board Layout Configuration VDD (+3.3 V Supply) P FB 22 µF G R1 1 SSCCLKOUT 8 0.1 µF R2 7 G G 3 6 4 5 Crystal connection or Reference input Note: Crystal connection or Not connection G Via to GND plane R1, R2 = Match value to line impedance. (22 Ω Reference value) FB = Ferrite bead. Figure 3 Example Board Layout Rev.6.00 Apr 07, 2006 page 7 of 9 CLKOUT HD151TS304RP 3. Example of TS300 EMI Solution IC’s Application Spread Spectrum Modulated Clock XTAL TS30X XOUT CPU & ASIC SSC CLKOUT System BUS Memory XIN Graphics System Cont. Ref. Clock 3.3 V CMOS level ref. Clock Figure 4 Ref. Clock Input Example Spread Spectrum Modulated Clock XTAL XOUT TS30X CPU & ASIC SSC CLKOUT System BUS Memory XIN Graphics System Cont. Figure 5 XTAL Ref. Clock Input Example Rev.6.00 Apr 07, 2006 page 8 of 9 HD151TS304RP Package Dimensions JEITA Package Code P-SOP8-3.95x4.9-1.27 RENESAS Code PRSP0008DD-C *1 Previous Code FP-8DCV MASS[Typ.] 0.085g F D 8 NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. 5 c *2 E HE bp Index mark Terminal cross section ( Ni/Pd/Au plating ) Reference Symbol 4 1 Z e *3 bp x M A L1 A1 θ L y Detail F Rev.6.00 Apr 07, 2006 page 9 of 9 D E A2 A1 A bp b1 c c1 θ HE e x y Z L L1 Dimension in Millimeters Min Nom Max 4.90 5.30 3.95 0.10 0.14 0.25 1.75 0.34 0.40 0.46 0.15 0.20 0.25 0° 8° 5.80 6.10 6.20 1.27 0.25 0.10 0.75 0.40 0.60 1.27 1.08 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. 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