ISSI IS61LV25616AL 256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY ® FEBRUARY 2003 DESCRIPTION The ISSI IS61LV25616AL is a high-speed, 4,194,304-bit FEATURES • High-speed access time: — 10, 12 ns • CMOS low power operation • Low stand-by power: — Less than 5 mA (typ.) CMOS stand-by • TTL compatible interface levels • Single 3.3V power supply • Fully static operation: no clock or refresh required • Three state outputs • Data control for upper and lower bytes • Industrial temperature available static RAM organized as 262,144 words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS61LV25616AL is packaged in the JEDEC standard 44-pin 400-mil SOJ, 44-pin TSOP Type II, 44-pin LQFP and 48-pin Mini BGA (8mm x 10mm). FUNCTIONAL BLOCK DIAGRAM A0-A17 DECODER 256K x 16 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O VDD GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte CE OE WE CONTROL CIRCUIT UB LB Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 02/21/03 1 ISSI IS61LV25616AL ® TRUTH TABLE CE OE LB UB Not Selected X H X X X High-Z High-Z ISB1, ISB2 Output Disabled H X L L H X X H X H High-Z High-Z High-Z High-Z ICC Read H H H L L L L L L L H L H L L DOUT High-Z DOUT High-Z DOUT DOUT I CC Write L L L L L L X X X L H L H L L DIN High-Z DIN High-Z DIN DIN I CC Mode PIN CONFIGURATIONS 44-Pin TSOP (Type II) and SOJ A0 A1 A2 A3 A4 CE I/O0 I/O1 I/O2 I/O3 VDD GND I/O4 I/O5 I/O6 I/O7 WE A5 A6 A7 A8 A9 2 I/O PIN I/O0-I/O7 I/O8-I/O15 WE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 VDD Current PIN DESCRIPTIONS 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A17 A16 A15 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VDD I/O11 I/O10 I/O9 I/O8 NC A14 A13 A12 A11 A10 A0-A17 Address Inputs I/O0-I/O15 Data Inputs/Outputs CE Chip Enable Input OE Output Enable Input WE Write Enable Input LB Lower-byte Control (I/O0-I/O7) UB Upper-byte Control (I/O8-I/O15) NC No Connection VDD Power GND Ground Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 02/21/03 ISSI IS61LV25616AL PIN CONFIGURATIONS 44-Pin LQFP ® 1 48-Pin mini BGA 2 3 4 5 6 A17 A16 A15 A14 A13 A12 A11 A10 OE UB LB 1 44 43 42 41 40 39 38 37 36 35 34 33 1 32 2 31 3 30 4 29 5 TOP VIEW 28 6 27 7 26 8 25 9 24 10 23 11 12 13 14 15 16 17 18 19 20 21 22 I/O15 I/O14 I/O13 I/O12 GND VDD I/O11 I/O10 I/O9 I/O8 NC A LB OE A0 A1 A2 N/C B I/O8 UB A3 A4 CE I/O0 C I/O9 I/O10 A5 A6 I/O1 I/O2 D GND I/O11 A17 A7 I/O3 VDD E VDD I/O12 NC A16 I/O4 GND F I/O14 I/O13 A14 A15 I/O5 I/O6 G I/O15 NC A12 A13 WE I/O7 H NC A8 A9 A10 A11 NC 3 4 5 6 WE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 CE I/O0 I/O1 I/O2 I/O3 VDD GND I/O4 I/O5 I/O6 I/O7 2 7 8 PIN DESCRIPTIONS A0-A17 Address Inputs I/O0-I/O15 Data Inputs/Outputs CE Chip Enable Input OE Output Enable Input WE Write Enable Input LB Lower-byte Control (I/O0-I/O7) UB Upper-byte Control (I/O8-I/O15) NC No Connection VDD Power GND Ground 9 10 11 12 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 02/21/03 3 ISSI IS61LV25616AL ® ABSOLUTE MAXIMUM RATINGS(1) Symbol Parameter VTERM Terminal Voltage with Respect to GND TSTG Storage Temperature PT Power Dissipation Value Unit –0.5 to VDD+0.5 V –65 to +150 °C 1.0 W Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING RANGE VDD Range Ambient Temperature 10ns 12ns 0°C to +70°C 3.3V +10%, -5% 3.3V + 10% –40°C to +85°C 3.3V +10%, -5% 3.3V + 10% Commercial Industrial DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions Min. Max. Unit VOH Output HIGH Voltage VDD = Min., IOH = –4.0 mA 2.4 — V VOL Output LOW Voltage VDD = Min., IOL = 8.0 mA — 0.4 V VIH Input HIGH Voltage 2.0 VDD + 0.3 V VIL Input LOW Voltage(1) –0.3 0.8 V ILI Input Leakage GND ≤ VIN ≤ VDD Com. Ind. –2 –5 2 5 µA ILO Output Leakage GND ≤ VOUT ≤ VDD Outputs Disabled Com. Ind. –2 –5 2 5 µA Notes: 1. VIL (min.) = –2.0V for pulse width less than 10 ns. 4 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 02/21/03 ISSI IS61LV25616AL ® POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter -10 Min. Max. Test Conditions -12 Min. Max. 1 Unit ICC VDD Dynamic Operating Supply Current VDD = Max., Com. IOUT = 0 mA, f = fMAX Ind. — — 100 110 — — 90 100 mA ISB TTL Standby Current (TTL Inputs) VDD = Max., VIN = VIH or VIL CE ≥ VIH, f = fMAX. Com. Ind. — — 50 55 — — 45 50 mA ISB1 TTL Standby Current (TTL Inputs) VDD = Max., VIN = VIH or VIL CE ≥ VIH, f = 0 Com. Ind. — — 20 25 — — 20 25 mA ISB2 CMOS Standby Current (CMOS Inputs) VDD = Max., Com. CE ≥ VDD – 0.2V, Ind. VIN ≥ VDD – 0.2V, or VIN ≤ 0.2V, f = 0 — — 15 20 — — 15 20 mA 2 3 4 5 Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. Shaded area product in development 6 CAPACITANCE (1) Symbol Parameter CIN Input Capacitance COUT Input/Output Capacitance Conditions Max. Unit VIN = 0V 6 pF VOUT = 0V 8 pF 7 8 Note: 1. Tested initially and after any design or process changes that may affect these parameters. 9 10 11 12 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 02/21/03 5 ISSI IS61LV25616AL ® READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol tRC tAA tOHA tACE tDOE tHZOE(2) tLZOE(2) tHZCE(2 tLZCE(2) tBA tHZB(2) tLZB(2) tPU tPD -10 Min. Max. Parameter -12 Min. Max. Unit Read Cycle Time 10 — 12 — ns Address Access Time — 10 — 12 ns Output Hold Time 2 — 2 — ns CE Access Time — 10 — 12 ns OE Access Time — 4 — 5 ns OE to High-Z Output — 4 — 5 ns OE to Low-Z Output 0 — 0 — ns CE to High-Z Output 0 4 0 6 ns CE to Low-Z Output 3 — 3 — ns LB, UB Access Time — 4 — 5 ns LB, UB to High-Z Output 0 3 0 4 ns LB, UB to Low-Z Output 0 — 0 — ns Power Up Time 0 — 0 — ns Power Down Time — 10 — 12 ns Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. AC TEST LOADS 319 Ω 319 Ω 3.3V 3.3V OUTPUT OUTPUT 30 pF Including jig and scope 353 Ω 5 pF Including jig and scope Figure 1 353 Ω Figure 2 AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load 6 Unit 0V to 3.0V 3 ns 1.5V See Figures 1 and 2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 02/21/03 ISSI IS61LV25616AL ® AC WAVEFORMS 1 READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL) t RC 2 ADDRESS t AA t OHA t OHA DOUT 3 DATA VALID PREVIOUS DATA VALID READ1.eps 4 5 READ CYCLE NO. 2(1,3) tRC 6 ADDRESS tAA tOHA OE 7 tHZOE tDOE tLZOE CE tACE tHZCE tLZCE 8 LB, UB DOUT VDD Supply Current HIGH-Z tBA tLZB tHZB tRC DATA VALID tPU 50% tPD 9 ICC 50% ISB UB_CEDR2.eps 10 Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE, UB, or LB = VIL. 3. Address is valid prior to or coincident with CE LOW transition. 11 12 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 02/21/03 7 ISSI IS61LV25616AL ® READ CYCLE NO. 2(1,3) tRC ADDRESS tAA tOHA OE tHZOE tDOE tLZOE CE tACE tHZCE tLZCE LB, UB DOUT HIGH-Z tBA tLZB VDD tHZB tRC DATA VALID tPU tPD 50% ICC 50% ISB Supply Current UB_CEDR2.eps Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE, UB, or LB = VIL. 3. Address is valid prior to or coincident with CE LOW transition. WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) Symbol tWC tSCE tAW tHA tSA tPWB tPWE1 tPWE2 tSD tHD tHZWE(2) tLZWE(2) Parameter -10 Min. Max. -12 Min. Max. Unit Write Cycle Time 10 — 12 — ns CE to Write End 8 — 8 — ns Address Setup Time to Write End 8 — 8 — ns Address Hold from Write End 0 — 0 — ns Address Setup Time 0 — 0 — ns LB, UB Valid to End of Write 8 — 8 — ns WE Pulse Width 8 — 8 — ns WE Pulse Width (OE = LOW) 10 — 12 — ns Data Setup to Write End 6 — 6 — ns Data Hold from Write End 0 — 0 — ns WE LOW to High-Z Output — 5 — 6 ns WE HIGH to Low-Z Output 2 — 2 — ns Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and UB or LB and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 8 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 02/21/03 ISSI IS61LV25616AL ® AC WAVEFORMS 1 WRITE CYCLE NO. 1 (CE Controlled, OE is HIGH or LOW) (1 ) t WC 2 VALID ADDRESS ADDRESS t SA t SCE t HA CE t AW t PWE1 t PWE2 WE 3 t PBW UB, LB t HZWE DOUT 4 t LZWE HIGH-Z DATA UNDEFINED t SD t HD 5 DATAIN VALID DIN UB_CEWR1.eps Notes: 1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least one of the LB and UB inputs being in the LOW state. 2. WRITE = (CE) [ (LB) = (UB) ] (WE). 6 7 WRITE CYCLE NO. 2 (WE Controlled. OE is HIGH During Write Cycle) (1,2) 8 t WC ADDRESS VALID ADDRESS t HA 9 OE CE LOW t AW 10 t PWE1 WE t SA t PBW UB, LB t HZWE DOUT DATA UNDEFINED t LZWE t SD DIN 11 HIGH-Z t HD DATAIN VALID 12 UB_CEWR2.eps Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 02/21/03 9 ISSI IS61LV25616AL ® AC WAVEFORMS WRITE CYCLE NO. 3 (WE Controlled. OE is LOW During Write Cycle) (1) t WC ADDRESS VALID ADDRESS OE LOW CE LOW t HA t AW t PWE2 WE t SA t PBW UB, LB t HZWE DOUT t LZWE HIGH-Z DATA UNDEFINED t SD t HD DATAIN VALID DIN UB_CEWR3.eps WRITE CYCLE NO. 4 (LB, UB Controlled, Back-to-Back Write) (1,3) t WC ADDRESS t WC ADDRESS 1 ADDRESS 2 OE t SA CE LOW t HA t SA WE UB, LB t HA t PBW t PBW WORD 1 WORD 2 t HZWE DOUT t LZWE HIGH-Z DATA UNDEFINED t HD t SD DIN DATAIN VALID t HD t SD DATAIN VALID UB_CEWR4.eps Notes: 1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be in valid states to initiate a Write, but any can be deasserted to terminate the Write. The t SA, t HA, t SD, and t HD timing is referenced to the rising or falling edge of the signal that terminates the Write. 2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state. 3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function. 10 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 02/21/03 ISSI IS61LV25616AL ® DATA RETENTION SWITCHING CHARACTERISTICS (LL) Min. Typ.(1) Max. Unit 2.0 — 3.6 V — — 5 — 10 15 mA See Data Retention Waveform 0 — — ns See Data Retention Waveform tRC — — ns Symbol Parameter Test Condition Options VDR VDD for Data Retention See Data Retention Waveform IDR Data Retention Current VDD = 2.0V, CE ≥ VDD – 0.2V tSDR tRDR Data Retention Setup Time Recovery Time Com. Ind. 1 2 Note 1: Typical values are measured at VDD = 3.0V, TA = 25 C and not 100% tested. 3 DATA RETENTION WAVEFORM (CE Controlled) 4 O tSDR Data Retention Mode 5 tRDR VDD 1.65V 1.4V 6 VDR CE GND 7 CE ≥ VDD - 0.2V 8 9 10 11 12 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 02/21/03 11 ISSI IS61LV25616AL ® ORDERING INFORMATION Commercial Range: 0°C to +70°C Speed (ns) Order Part No. Package 10 IS61LV25616AL-10T IS61LV25616AL-10K IS61LV25616AL-10LQ IS61LV25616AL-10B TSOP (Type II) 400-mil SOJ LQFP Mini BGA (8mm x 10mm) 12 IS61LV25616AL-12T IS61LV25616AL-12K IS61LV25616AL-12B TSOP (Type II) 400-mil SOJ Mini BGA (8mm x 10mm) Industrial Range: –40°C to +85°C Speed (ns) 12 Order Part No. Package 10 IS61LV25616AL-10TI IS61LV25616AL-10KI IS61LV25616AL-10LQI IS61LV25616AL-10BI TSOP (Type II) 400-mil SOJ LQFP Mini BGA (8mm x 10mm) 12 IS61LV25616AL-12TI IS61LV25616AL-12KI TSOP (Type II) 400-mil SOJ Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 02/21/03