IS61WV51216EDALL IS61/64WV51216EDBLL 512K x 16 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH ECC FEATURES • High-speed access times: 8, 10, 20 ns • High-performance, low-power CMOS process • Multiple center power and ground pins for greater noise immunity • Easy memory expansion with CE and OE options • CE power-down • Fully static operation: no clock or refresh required • TTL compatible inputs and outputs • Single Power Supply – Vdd = 1.65V to 2.2V (IS61WV51216EDALL) – Vdd = 2.4V to 3.6V (IS61/64WV51216EDBLL) • Packages available: – 48-ball miniBGA (6mm x 8mm) – 44-pin TSOP (Type II) • Industrial and Automotive Temperature Support • Lead-free available • Data control for upper and lower bytes FEBRUARY 2013 DESCRIPTION The ISSI IS61WV51216EDALL and IS61/64WV51216EDBLL are high-speed, 8M-bit static RAMs organized as 512K words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The device is packaged in the JEDEC standard 44-pin TSOP Type II and 48-pin Mini BGA (6mm x 8mm). FUNCTIONAL BLOCK DIAGRAM Memory Lower IO Array512Kx8 A0-A18 Decoder 8 IO0-7 IO8-15 /CE /OE /WE /UB /LB 8 12 8 I/O Data Circuit ECC 8 ECC 12 8 ECC Array512K x4 4 Memory ECC Array512K x4 Upper IO Array512Kx8 8 4 Column I/O Control Circuit Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. — www.issi.com 1 Rev. A 02/20/2013 IS61WV51216EDALL IS61/64WV51216EDBLL 48-pin mini BGA (6mm x 8mm) 1 2 3 4 5 6 A LB OE A0 A1 A2 NC B I/O8 UB A3 A4 CE I/O0 C I/O9 I/O10 A5 A6 I/O1 I/O2 D GND I/O11 A17 A7 I/O3 VDD E VDD I/O12 NC A16 I/O4 GND F I/O14 I/O13 A14 A15 I/O5 I/O6 G I/O15 NC A12 A13 WE I/O7 H A18 A8 A9 A10 A11 NC PIN DESCRIPTIONS A0-A18 Address Inputs I/O0-I/O15 Data Inputs/Outputs CE Chip Enable Input OE Output Enable Input WE Write Enable Input LB Lower-byte Control (I/O0-I/O7) UB Upper-byte Control (I/O8-I/O15) NC No Connection VddPower GND Ground 2 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 02/20/2013 IS61WV51216EDALL IS61/64WV51216EDBLL PIN CONFIGURATIONS 44-Pin TSOP (Type II) A0 A1 A2 A3 A4 CE I/O0 I/O1 I/O2 I/O3 VDD GND I/O4 I/O5 I/O6 I/O7 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A17 A16 A15 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VDD I/O11 I/O10 I/O9 I/O8 A18 A14 A13 A12 A11 A10 PIN DESCRIPTIONS A0-A18 Address Inputs I/O0-I/O15 Data Inputs/Outputs CE Chip Enable Input OE Output Enable Input WE Write Enable Input LB Lower-byte Control (I/O0-I/O7) UB Upper-byte Control (I/O8-I/O15) NC No Connection VddPower GND Ground Integrated Silicon Solution, Inc. — www.issi.com3 Rev. A 02/20/2013 IS61WV51216EDALL IS61/64WV51216EDBLL TRUTH TABLE Mode Not Selected Output Disabled Read Write WE X H X H H H L L L CE H L L L L L L L L OE X H X L L L X X X I/O PIN LBUB I/O0-I/O7 I/O8-I/O15Vdd Current X X High-Z High-Z Isb1, Isb2 X X High-Z High-Z Icc H H High-Z High-Z L H Dout High-ZIcc H L High-Z Dout L LDoutDout L H Din High-ZIcc H L High-Z Din L LDinDin ABSOLUTE MAXIMUM RATINGS(1) SymbolParameter Vterm Terminal Voltage with Respect to GND Vdd Vdd Relates to GND Tstg Storage Temperature Pt Power Dissipation Value –0.5 to Vdd + 0.5 –0.3 to 4.0 –65 to +150 1.0 Unit V V °C W Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE(1,2) SymbolParameter Cin Input Capacitance CI/O Input/Output Capacitance Conditions Vin = 0V Vout = 0V Max.Unit 6 pF 8 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: Ta = 25°C, f = 1 MHz, Vdd = 3.3V. 4 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 02/20/2013 IS61WV51216EDALL IS61/64WV51216EDBLL OPERATING RANGE (Vdd) RangeAmbient IS61WV51216EDALL IS61WV51216EDBLL Temperature Vdd (20ns) Vdd (8, 10ns) Industrial –40°C to +85°C 1.65V-2.2V 2.4V-3.6V Automotive (A1) –40°C to +85°C — — Automotive (A3) –40°C to +125°C — — IS64WV51216EDBLL Vdd (10ns) — 2.4V-3.6V 2.4V-3.6V ERROR DETECTION AND ERROR CORRECTION • • • • Independent ECC for each byte Detect and correct one bit error per byte Better reliability than parity code schemes which can only detect an error but not correct an error Backward Compatible: Drop in replacement to current in industry standard devices (without ECC) Integrated Silicon Solution, Inc. — www.issi.com5 Rev. A 02/20/2013 IS61WV51216EDALL IS61/64WV51216EDBLL DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Vdd = 2.4V-3.6V Symbol Voh Vol Vih Vil Ili Ilo Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) Input Leakage Output Leakage Test Conditions Vdd = Min., Ioh = –1.0 mA Vdd = Min., Iol = 1.0 mA GND ≤ Vin ≤ Vdd GND ≤ Vout ≤ Vdd, Outputs Disabled Min.Max.Unit 1.8 — V — 0.4 V 2.0 Vdd + 0.3 V –0.3 0.8 V –11µA –1 1 µA Note: 1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width < 2 ns). Not 100% tested. Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width < 2 ns). Not 100% tested. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Vdd = 1.65V-2.2V Symbol Voh Vol Vih Vil Ili Ilo Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Output Leakage Test Conditions Min. Max. Unit Ioh = -0.1 mA 1.4 — V Iol = 0.1 mA — 0.2 V 1.4 Vdd + 0.2 V –0.2 0.4V GND ≤ Vin ≤ Vdd –1 1µA GND ≤ Vout ≤ Vdd, –1 1 µA Outputs Disabled Notes: 1. Vil (min.) = –0.3V DC; Vil (min.) = –1.0V AC (pulse width < 2 ns). Not 100% tested. Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 1.0V AC (pulse width < 2 ns). Not 100% tested. 6 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 02/20/2013 IS61WV51216EDALL IS61/64WV51216EDBLL AC TEST CONDITIONS Parameter Unit UnitUnit (2.4V-3.6V) (3.3V + 5%) (1.65V-2.2V) Input Pulse Level 0.4V to Vdd - 0.3V 0.4V to Vdd - 0.3V 0.4V to Vdd - 0.3V Input Rise and Fall Times 1V/ ns 1V/ ns 1V/ ns Input and Output Timing VDD /2 VDD + 0.05 0.9V and Reference Level (VRef) 2 Output Load See Figures 1 and 2 See Figures 1 and 2 See Figures 1 and 2 R1 ( Ω ) 1909 317 13500 R2 ( Ω ) 1105 351 10800 Vtm (V) 3.0V 3.3V 1.8V AC TEST LOADS R1 ZO = 50Ω VTM 50Ω VDD/2 OUTPUT 30 pF Including jig and scope OUTPUT Figure 1. R2 5 pF Including jig and scope Figure 2. POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) -8 SymbolParameter Test Conditions Min. Max. Icc Vdd Dynamic Operating Vdd = Max., Com. — 45 Supply Current Iout = 0 mA, f = fmax Ind. — 55 Auto. — — typ.(2) Icc1 Operating Vdd = Max., Com. — 20 Supply Current Iout = 0 mA, f = 0 Ind. — 25 Auto. — — Isb1 TTL Standby Current Vdd = Max., Com. — 20 (TTL Inputs) Vin = Vih or Vil Ind. — 25 CE ≥ Vih, f = 0 Auto. — — Isb2 CMOS Standby Vdd = Max., Com. — 10 Current (CMOS Inputs) CE ≥ Vdd – 0.2V, Ind. — 15 Vin ≥ Vdd – 0.2V, or Auto. — — Vin ≤ 0.2V, f = 0 typ.(2) -10 Min.Max. — 40 — 50 — 65 15 — 20 — 25 — 50 — 20 — 25 — 45 — 10 — 15 — 35 2 -20 Min.Max. Unit — 30 mA — 40 — 55 — — — — — — — — — 20 mA 25 50 20 mA 25 45 10mA 15 35 Note: 1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at Vdd = 3.0V, Ta = 25oC and not 100% tested. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 02/20/2013 7 IS61WV51216EDALL IS61/64WV51216EDBLL READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) -8 Symbol Parameter Min. Max. trc Read Cycle Time 8 — taa Address Access Time — 8 toha Output Hold Time 2.5 — tace CE Access Time — 8 tdoe OE Access Time — 5.5 thzoe(2) OE to High-Z Output — 3 tlzoe(2) OE to Low-Z Output 0 — thzce(2 CE to High-Z Output 0 3 (2) tlzce CE to Low-Z Output 3 — tba LB, UB Access Time — 5.5 thzb(2) LB, UB to High-Z Output 0 3 (2) tlzb LB, UB to Low-Z Output 0 — tpu Power Up Time 0 — tpd Power Down Time — 8 -10 Min. Max. Unit 10 — ns — 10 ns 2.5 — ns — 10 ns — 6.5 ns — 4 ns 0 — ns 0 4 ns 3 — ns — 6.5 ns 0 3 ns 0 — ns 0 — ns — 10 ns Notes: 1. Test conditions and output loading conditions are specified in the AC Test Conditions and AC Test Loads (Figure 1). 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. 8 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 02/20/2013 IS61WV51216EDALL IS61/64WV51216EDBLL READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) -20 ns Symbol ParameterMin.Max. Unit trc Read Cycle Time 20 — ns taa Address Access Time — 20 ns toha Output Hold Time 2.5 — ns tace CE Access Time — 20 ns tdoe OE Access Time — 8 ns (2) thzoe OE to High-Z Output 0 8 ns (2) tlzoe OE to Low-Z Output 0 — ns thzce(2 CE to High-Z Output 0 8 ns tlzce(2) CE to Low-Z Output 3 — ns tba LB, UB Access Time — 8 ns thzb LB, UB to High-Z Output 0 8 ns tlzb LB, UB to Low-Z Output 0 — ns Notes: 1. Test conditions and output loading conditions are specified in the AC Test Conditions and AC Test Loads (Figure 1). 2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. Not 100% tested. Integrated Silicon Solution, Inc. — www.issi.com9 Rev. A 02/20/2013 IS61WV51216EDALL IS61/64WV51216EDBLL AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = Vil) t RC ADDRESS t OHA DOUT t AA t OHA DATA VALID PREVIOUS DATA VALID READ CYCLE NO. 2(1,3) (CE and OE Controlled) t RC ADDRESS t AA t OHA OE t HZOE t DOE t LZOE CE t LZCE DOUT t ACE HIGH-Z t HZCE DATA VALID Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE = Vil. 3. Address is valid prior to or coincident with CE LOW transitions. 10 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 02/20/2013 IS61WV51216EDALL IS61/64WV51216EDBLL WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) -8-10 Symbol Parameter Min. Max. Min. Max. Unit twc Write Cycle Time 8 — 10 — ns tsce CE to Write End 6.5 — 8 — ns taw Address Setup Time 6.5 — 8 — ns to Write End tha Address Hold from Write End 0 — 0 — ns tsa Address Setup Time 0 — 0 — ns tpwb LB, UB Valid to End of Write 6.5 — 8 — ns tpwe1 WE Pulse Width 6.5 — 8 — ns tpwe2 WE Pulse Width (OE = LOW) 8.0 — 10 — ns tsd Data Setup to Write End 5 — 6 — ns thd thzwe(2) tlzwe(2) Data Hold from Write End WE LOW to High-Z Output WE HIGH to Low-Z Output 0 — 2 — 3.5 — 0 — 2 — 5 — s n ns ns Notes: 1. Test conditions and output loading conditions are specified in the AC Test Conditions and AC Test Loads (Figure 1). 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. Shaded area product in development Integrated Silicon Solution, Inc. — www.issi.com11 Rev. A 02/20/2013 IS61WV51216EDALL IS61/64WV51216EDBLL WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range) Symbol Parameter twc Write Cycle Time tsce CE to Write End taw Address Setup Time to Write End tha Address Hold from Write End tsa Address Setup Time tpwb LB, UB Valid to End of Write tpwe1 WE Pulse Width (OE = HIGH) tpwe2 WE Pulse Width (OE = LOW) tsd Data Setup to Write End thd thzwe(2) tlzwe(2) Data Hold from Write End WE LOW to High-Z Output WE HIGH to Low-Z Output -20 ns Min. Max.Unit 20 — ns 12 — ns 12 — ns 0 0 12 12 17 9 — — — — — — ns ns ns ns ns ns 0 — 3 — 9 — ns ns ns Notes: 1. Test conditions and output loading conditions are specified in the AC Test Conditions and AC Test Loads (Figure 1). 2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 12 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 02/20/2013 IS61WV51216EDALL IS61/64WV51216EDBLL AC WAVEFORMS WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW) t WC VALID ADDRESS ADDRESS t SA t SCE t HA CE t AW t PWE1 t PWE2 WE t HZWE DOUT DATA UNDEFINED t LZWE HIGH-Z t SD DIN t HD DATAIN VALID Integrated Silicon Solution, Inc. — www.issi.com13 Rev. A 02/20/2013 IS61WV51216EDALL IS61/64WV51216EDBLL AC WAVEFORMS WRITE CYCLE NO. 2 (WE Controlled. OE is HIGH During Write Cycle) (1,2) t WC ADDRESS VALID ADDRESS t HA OE CE LOW t AW t PWE1 WE t SA t PBW UB, LB t HZWE DOUT t LZWE HIGH-Z DATA UNDEFINED t SD t HD DATAIN VALID DIN WRITE CYCLE NO. 3 (WE Controlled. OE is LOW During Write Cycle) (1) t WC ADDRESS VALID ADDRESS OE LOW CE LOW t HA t AW t PWE2 WE t SA t PBW UB, LB t HZWE DOUT DATA UNDEFINED t LZWE HIGH-Z t SD DIN 14 t HD DATAIN VALID Integrated Silicon Solution, Inc. — www.issi.com Rev. A 02/20/2013 IS61WV51216EDALL IS61/64WV51216EDBLL AC WAVEFORMS WRITE CYCLE NO. 4 (LB, UB Controlled, Back-to-Back Write) (1,3) t WC ADDRESS t WC ADDRESS 1 ADDRESS 2 OE t SA CE LOW t HA t SA WE UB, LB t HA t PBW t PBW WORD 1 WORD 2 t HZWE DOUT t LZWE HIGH-Z DATA UNDEFINED t HD t SD DIN DATAIN VALID t HD t SD DATAIN VALID Notes: 1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be in valid states to initiate a Write, but any can be deasserted to terminate the Write. The t sa, t ha, t sd, and t hd timing is referenced to the rising or falling edge of the signal that terminates the Write. 2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state. 3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function. Integrated Silicon Solution, Inc. — www.issi.com15 Rev. A 02/20/2013 IS61WV51216EDALL IS61/64WV51216EDBLL DATA RETENTION SWITCHING CHARACTERISTICS (2.4V-3.6V) Symbol Parameter Test Condition VdrVdd for Data Retention See Data Retention Waveform Idr Data Retention Current Vdd = Vdr(min), CE ≥ Vdd – 0.2V tsdr Data Retention Setup Time See Data Retention Waveform trdr Recovery Time See Data Retention Waveform Note 1: Typical values are measured at Vdd = Vdr(min) Ta = 25 C and not 100% tested. Options Min. Typ.(1) Max.Unit 2.0 — 3.6 V Com. — 2 10 mA Ind. — — 15 Auto. 35 0 — — ns trc — — ns o DATA RETENTION SWITCHING CHARACTERISTICS (1.65V-2.2V) Symbol Parameter Test Condition VdrVdd for Data Retention See Data Retention Waveform Idr Data Retention Current Vdd = Vdr(min), CE ≥ Vdd – 0.2V tsdr Data Retention Setup Time See Data Retention Waveform trdr Recovery Time See Data Retention Waveform Note 1: Typical values are measured at Vdd = Vdr(min), Ta = 25 C and not 100% tested. Options Com. Ind. Auto. Min. 1.2 — — — 0 trc Typ.(1) Max.Unit — 3.6 V 2 10 mA — 15 — 35 — — ns — — ns o DATA RETENTION WAVEFORM (CE Controlled) tSDR Data Retention Mode tRDR VDD VDR CE GND 16 CE ≥ VDD - 0.2V Integrated Silicon Solution, Inc. — www.issi.com Rev. A 02/20/2013 IS61WV51216EDALL IS61/64WV51216EDBLL ORDERING INFORMATION Industrial Range: -40°C to +85°C Voltage Range: 2.4V to 3.6V Speed (ns) 8 10 Order Part No. IS61WV51216EDBLL-8BLI IS61WV51216EDBLL-8TLI IS61WV51216EDBLL-10BI IS61WV51216EDBLL-10BLI IS61WV51216EDBLL-10TI IS61WV51216EDBLL-10TLI Package 48 mini BGA (6mm x 8mm), Lead-free TSOP (Type II), Lead-free 48 mini BGA (6mm x 8mm) 48 mini BGA (6mm x 8mm), Lead-free TSOP (Type II) TSOP (Type II), Lead-free Industrial Range: -40°C to +85°C Voltage Range: 1.65V to 2.2V Speed (ns) 20 Order Part No. IS61WV51216EDALL-20BLI IS61WV51216EDALL-20TLI Package 48 mini BGA (6mm x 8mm), Lead-free TSOP (Type II), Lead-free Automotive Range: -40°C to +125°C Voltage Range: 2.4V to 3.6V Speed (ns) 10 Order Part No. Package IS64WV51216EDBLL-10BA3 48 mini BGA (6mm x 8mm) IS64WV51216EDBLL-10BLA3 48 mini BGA (6mm x 8mm), Lead-free IS64WV51216EDBLL-10CTA3 TSOP (Type II), Copper Leadframe IS64WV51216EDBLL-10CTLA3TSOP (Type II), Lead-free, Copper Leadframe Integrated Silicon Solution, Inc. — www.issi.com Rev. A 02/20/2013 17 18 08/12/2008 Package Outline 1. CONTROLLING DIMENSION : MM . 2. Reference document : JEDEC MO-207 NOTE : IS61WV51216EDALL IS61/64WV51216EDBLL Integrated Silicon Solution, Inc. — www.issi.com Rev. A 02/20/2013 Rev. A 02/20/2013 Θ Package Outline 06/04/2008 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION. 2. DIMENSION D AND E1 DO NOT INCLUDE MOLD PROTRUSION. 1. CONTROLLING DIMENSION : MM NOTE : Θ IS61WV51216EDALL IS61/64WV51216EDBLL Integrated Silicon Solution, Inc. — www.issi.com19