IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL 1M x 16 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY FEATURES • High-speed access times: 8, 10, 20 ns • High-performance, low-power CMOS process • Multiple center power and ground pins for greater noise immunity • Easy memory expansion with CE and OE options • CE power-down • Fully static operation: no clock or refresh required • TTL compatible inputs and outputs • Single power supply Vdd 1.65V to 2.2V (IS61WV102416ALL) speed = 20ns for Vdd 1.65V to 2.2V Vdd 2.4V to 3.6V (IS61/64WV102416BLL) speed = 10ns for Vdd 2.4V to 3.6V speed = 8ns for Vdd 3.3V + 5% • Packages available: – 48-ball miniBGA (9mm x 11mm) – 48-pin TSOP (Type I) • Industrial and Automotive Temperature Support • Lead-free available • Data control for upper and lower bytes MAY 2012 DESCRIPTION The ISSI IS61WV102416ALL/BLL and IS64WV102416BLL are high-speed, 16M-bit static RAMs organized as 1024K words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The device is packaged in the JEDEC standard 48-pin TSOP Type I and 48-pin Mini BGA (9mm x 11mm). FUNCTIONAL BLOCK DIAGRAM A0-A19 DECODER 1024K x 16 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O VDD GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte CE OE WE UB CONTROL CIRCUIT LB Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. F 05/09/12 1 IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL 48-pin mini BGA (9mmx11mm) 1 2 3 4 5 6 A LB OE A0 A1 A2 NC B I/O8 UB A3 A4 CE I/O0 C I/O9 I/O10 A5 A6 I/O1 I/O2 D GND I/O11 A17 A7 I/O3 VDD E VDD I/O12 NC A16 I/O4 GND F I/O14 I/O13 A14 A15 I/O5 I/O6 G I/O15 A19 A12 A13 WE I/O7 H A18 A8 A9 A10 A11 NC PIN DESCRIPTIONS A0-A19 I/O0-I/O15 CE OE WE LB UB NC Vdd GND 2 Address Inputs Data Inputs/Outputs Chip Enable Input Output Enable Input Write Enable Input Lower-byte Control (I/O0-I/O7) Upper-byte Control (I/O8-I/O15) No Connection Power Ground Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. F 05/09/12 IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL 48-pin TSOP-I (12mm x 20mm) A4 A3 A2 A1 A0 NC CE I/O0 I/O1 I/O2 I/O3 VDD GND I/O4 I/O5 I/O6 I/O7 WE NC A19 A18 A17 A16 A15 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 A5 A6 A7 A8 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VDD I/O11 I/O10 I/O9 I/O8 NC A9 A10 A11 A12 A13 A14 PIN DESCRIPTIONS A0-A19 I/O0-I/O15 CE OE WE LB UB NC Vdd GND Address Inputs Data Inputs/Outputs Chip Enable Input Output Enable Input Write Enable Input Lower-byte Control (I/O0-I/O7) Upper-byte Control (I/O8-I/O15) No Connection Power Ground Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. F 05/09/12 3 IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL TRUTH TABLE Mode Not Selected Output Disabled Read Write WE X H X H H H L L L CE H L L L L L L L L OE X H X L L L X X X LB X X H L H L L H L UB X X H H L L H L L I/O PIN I/O0-I/O7 I/O8-I/O15 High-Z High-Z High-Z High-Z High-Z High-Z Dout High-Z High-Z Dout Dout Dout Din High-Z High-Z Din Din Din Vdd Current Isb1, Isb2 Icc Icc Icc ABSOLUTE MAXIMUM RATINGS(1) Symbol Vterm Vdd Tstg Pt Parameter Terminal Voltage with Respect to GND Vdd Relates to GND Storage Temperature Power Dissipation Value –0.5 to Vdd + 0.5 –0.3 to 4.0 –65 to +150 1.0 Unit V V °C W Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE(1,2) Symbol Cin CI/O Parameter Input Capacitance Input/Output Capacitance Conditions Vin = 0V Vout = 0V Max. 6 8 Unit pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: Ta = 25°C, f = 1 MHz, Vdd = 3.3V. 4 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. F 05/09/12 IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL OPERATING RANGE (Vdd) (IS61WV102416ALL) Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C Automotive –40°C to +125°C Vdd (20 ns) 1.65V-2.2V 1.65V-2.2V 1.65V-2.2V OPERATING RANGE (Vdd) (IS61WV102416BLL)(1) Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C Vdd (8 ns) 3.3V + 5% 3.3V + 5% Vdd (10 ns) 2.4V-3.6V 2.4V-3.6V Note: 1. When operated in the range of 2.4V-3.6V, the device meets 10ns. When operated in the range of 3.3V + 5%, the device meets 8ns. OPERATING RANGE (Vdd) (IS64WV102416BLL) Range Ambient Temperature Automotive –40°C to +125°C Vdd (10 ns) 2.4V-3.6V Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. F 05/09/12 5 IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Vdd = 3.3V + 5% Symbol Voh Vol Vih Vil Ili Ilo Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) Input Leakage Output Leakage Test Conditions Vdd = Min., Ioh = –4.0 mA Vdd = Min., Iol = 8.0 mA GND ≤ Vin ≤ Vdd GND ≤ Vout ≤ Vdd, Outputs Disabled Min. 2.4 — 2 –0.3 –1 –1 Max. — 0.4 Vdd + 0.3 0.8 1 1 Unit V V V V µA µA Min. 1.8 — 2.0 –0.3 –1 –1 Max. — 0.4 Vdd + 0.3 0.8 1 1 Unit V V V V µA µA Note: 1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width 2.0 ns). Not 100% tested. Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width 2.0 ns). Not 100% tested. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Vdd = 2.4V-3.6V Symbol Voh Vol Vih Vil Ili Ilo Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) Input Leakage Output Leakage Test Conditions Vdd = Min., Ioh = –1.0 mA Vdd = Min., Iol = 1.0 mA GND ≤ Vin ≤ Vdd GND ≤ Vout ≤ Vdd, Outputs Disabled Note: 1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width 2.0 ns). Not 100% tested. Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width 2.0 ns). Not 100% tested. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Vdd = 1.65V-2.2V Symbol Voh Vol Vih Vil(1) Ili Ilo Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Output Leakage Test Conditions Vdd Ioh = -0.1 mA 1.65-2.2V Iol = 0.1 mA 1.65-2.2V 1.65-2.2V 1.65-2.2V GND ≤ Vin ≤ Vdd GND ≤ Vout ≤ Vdd, Outputs Disabled Min. 1.4 — 1.4 –0.2 –1 –1 Max. — 0.2 Vdd + 0.2 0.4 1 1 Unit V V V V µA µA Notes: 1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width -2.0ns). Not 100% tested. Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width -2.0ns). Not 100% tested. 6 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. F 05/09/12 IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL AC TEST CONDITIONS (HIGH SPEED) Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level (VRef) Output Load Unit (2.4V-3.6V) 0.4V to Vdd-0.3V 1.5ns Vdd/2 Unit (3.3V + 5%) 0.4V to Vdd-0.3V 1.5ns Vdd/2 + 0.05 Unit (1.65V-2.2V) 0.4V to Vdd-0.2V 1.5ns Vdd/2 See Figures 1 and 2 See Figures 1 and 2 See Figures 1 and 2 AC TEST LOADS 319 Ω ZO = 50Ω 3.3V 50Ω 1.5V OUTPUT 30 pF Including jig and scope OUTPUT Figure 1. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. F 05/09/12 5 pF Including jig and scope 353 Ω Figure 2. 7 IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) -8 Symbol Parameter Test Conditions Min. Max. Icc Vdd Dynamic Operating Vdd = Max., Com. — 110 Supply Current Iout = 0 mA, f = fmax Ind. — 115 Vin = 0.4V or Vdd –0.3V Auto. — — typ.(2) Icc1 Operating Vdd = Max., Com. — 85 Supply Current Iout = 0 mA, f = 0 Ind. — 90 Vin = 0.4V or Vdd –0.3V Auto. — — Isb1 TTL Standby Current Vdd = Max., Com. — 30 (TTL Inputs) Vin = Vih or Vil Ind. — 35 CE ≥ Vih, f = 0 Auto. — — Isb2 CMOS Standby Vdd = Max., Com. — 20 Current (CMOS Inputs) CE ≥ Vdd – 0.2V, Ind. — 25 Vin ≥ Vdd – 0.2V, or Auto. — — Vin ≤ 0.2V, f = 0 typ.(2) -10 Min. Max. — 90 — 95 — 140 60 — 85 — 90 — 110 — 30 — 35 — 70 — 20 — 25 — 60 4 -20 Min. Max. — 50 — 60 — 100 — — — — — — — — — 45 55 90 30 35 70 20 25 60 Unit mA mA mA mA Note: 1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at Vdd = 3.0V, Ta = 25oC and not 100% tested. 8 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. F 05/09/12 IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter trc Read Cycle Time taa Address Access Time toha Output Hold Time tace CE Access Time tdoe OE Access Time (2) thzoe OE to High-Z Output tlzoe(2) OE to Low-Z Output thzce(2 CE to High-Z Output (2) tlzce CE to Low-Z Output tba LB, UB Access Time thzb(2) LB, UB to High-Z Output tlzb(2) LB, UB to Low-Z Output tpu Power Up Time tpd Power Down Time -8 Min. Max. 8 — — 8 2.5 — — 8 — 5.5 — 3 0 — 0 3 3 — — 5.5 0 3 0 — 0 — — 8 -10 Min. Max. 10 — — 10 2.5 — — 10 — 6.5 — 4 0 — 0 4 3 — — 6.5 0 3 0 — 0 — — 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. F 05/09/12 9 IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) -20 ns Symbol Parameter Min. Max. trc Read Cycle Time 20 — taa Address Access Time — 20 toha Output Hold Time 2.5 — tace CE Access Time — 20 tdoe OE Access Time — 8 (2) thzoe OE to High-Z Output 0 8 (2) tlzoe OE to Low-Z Output 0 — thzce(2 CE to High-Z Output 0 8 (2) tlzce CE to Low-Z Output 3 — tba LB, UB Access Time — 8 thzb LB, UB to High-Z Output 0 8 tlzb LB, UB to Low-Z Output 0 — Unit ns ns ns ns ns ns ns ns ns ns ns ns Notes: 1. Test conditions assume signal transition times of 1.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to Vdd-0.3V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. Not 100% tested. 10 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. F 05/09/12 IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = Vil) t RC ADDRESS t OHA DOUT t AA t OHA DATA VALID PREVIOUS DATA VALID READ1.eps READ CYCLE NO. 2(1,3) (CE and OE Controlled) t RC ADDRESS t AA t OHA OE t HZOE t DOE t LZOE CE t LZCE DOUT t ACE HIGH-Z t HZCE DATA VALID CE_RD2.eps Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE = Vil. 3. Address is valid prior to or coincident with CE LOW transitions. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. F 05/09/12 11 IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) -8 Symbol twc tsce taw tha tsa tpwb tpwe1 tpwe2 tsd thd thzwe tlzwe(2) (2) Parameter Write Cycle Time CE to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time LB, UB Valid to End of Write WE Pulse Width WE Pulse Width (OE = LOW) Data Setup to Write End Data Hold from Write End WE LOW to High-Z Output WE HIGH to Low-Z Output Min. 8 6.5 6.5 Max. — — — -10 Min. Max. 10 — 8 — 8 — Unit ns ns ns 0 0 6.5 6.5 8.0 5 — — — — — — 0 0 8 8 10 6 — — — — — — ns ns ns ns ns ns 0 — 2 — 3.5 — 0 — 2 — 5 — s n ns ns Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. Shaded area product in development 12 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. F 05/09/12 IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range) -20 ns Symbol Parameter Min. Max.Unit twc Write Cycle Time 20 — ns tsce CE to Write End 12 — ns taw Address Setup Time 12 — ns to Write End tha Address Hold from Write End 0 — ns tsa Address Setup Time 0 — ns tpwb LB, UB Valid to End of Write 12 — ns tpwe1 WE Pulse Width (OE = HIGH) 12 — ns tpwe2 WE Pulse Width (OE = LOW) 17 — ns tsd Data Setup to Write End 9 — ns thd Data Hold from Write End 0 — ns thzwe(3) tlzwe(3) WE LOW to High-Z Output WE HIGH to Low-Z Output — 3 9 — ns ns Notes: 1. Test conditions for IS61WV6416LL assume signal transition times of 1.5ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to Vdd-0.3V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. F 05/09/12 13 IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL AC WAVEFORMS WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW) t WC VALID ADDRESS ADDRESS t SA t SCE t HA CE t AW t PWE1 t PWE2 WE t HZWE DOUT DATA UNDEFINED t LZWE HIGH-Z t SD DIN t HD DATAIN VALID CE_WR1.eps 14 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. F 05/09/12 IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL AC WAVEFORMS WRITE CYCLE NO. 2 (WE Controlled. OE is HIGH During Write Cycle) (1,2) t WC ADDRESS VALID ADDRESS t HA OE CE LOW t AW t PWE1 WE t SA t PBW UB, LB t HZWE DOUT t LZWE HIGH-Z DATA UNDEFINED t SD t HD DATAIN VALID DIN UB_CEWR2.eps WRITE CYCLE NO. 3 (WE Controlled. OE is LOW During Write Cycle) (1) t WC ADDRESS VALID ADDRESS OE LOW CE LOW t HA t AW t PWE2 WE t SA t PBW UB, LB t HZWE DOUT DATA UNDEFINED t LZWE HIGH-Z t SD DIN t HD DATAIN VALID UB_CEWR3.eps Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. F 05/09/12 15 IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL AC WAVEFORMS WRITE CYCLE NO. 4 (LB, UB Controlled, Back-to-Back Write) (1,3) t WC ADDRESS t WC ADDRESS 1 ADDRESS 2 OE t SA CE LOW t HA t SA WE UB, LB t HA t PBW t PBW WORD 1 WORD 2 t HZWE DOUT t LZWE HIGH-Z DATA UNDEFINED t HD t SD DIN DATAIN VALID t HD t SD DATAIN VALID UB_CEWR4.eps Notes: 1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be in valid states to initiate a Write, but any can be deasserted to terminate the Write. The t sa, t ha, t sd, and t hd timing is referenced to the rising or falling edge of the signal that terminates the Write. 2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state. 3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function. 16 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. F 05/09/12 IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL DATA RETENTION SWITCHING CHARACTERISTICS Symbol Vdr Idr tsdr trdr Parameter Vdd for Data Retention Data Retention Current Data Retention Setup Time Recovery Time Test Condition See Data Retention Waveform Vdd = 1.2V, CE ≥ Vdd – 0.2V Ind. Auto. See Data Retention Waveform See Data Retention Waveform Min. 1.2 — — 0 trc Max. 3.6 20 50 — — Unit V mA ns ns DATA RETENTION WAVEFORM (CE Controlled) tSDR Data Retention Mode tRDR VDD 1.65V 1.4V VDR CE GND CE ≥ VDD - 0.2V Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. F 05/09/12 17 IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL ORDERING INFORMATION Industrial Range: -40°C to +85°C Voltage Range: 2.4V to 3.6V peed (ns) S 10 (81) Order Part No. IS61WV102416BLL-10MI IS61WV102416BLL-10MLI IS61WV102416BLL-10TLI Package 48 mini BGA (9mm x 11mm) 48 mini BGA (9mm x 11mm), Lead-free TSOP (Type I), Lead-free Note: 1. Speed = 8ns for Vdd = 3.3V + 5%. Speed = 10ns for Vdd = 2.4V - 3.6V Industrial Range: -40°C to +85°C Voltage Range: 1.65V to 2.2V peed (ns) S 20 Order Part No. IS61WV102416ALL-20MI IS61WV102416ALL-20TLI Package 48 mini BGA (9mm x 11mm) TSOP (Type I), Lead-free Automotive Range: -40°C to +125°C Voltage Range: 2.4V to 3.6V peed (ns) S 10 18 Order Part No. IS64WV102416BLL-10MA3 IS64WV102416BLL-10MLA3 IS64WV102416BLL-10CTLA3 Package 48 mini BGA (9mm x 11mm) 48 mini BGA (9mm x 11mm), Lead-free TSOP (Type I), Copper Leadframe, Lead-free Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. F 05/09/12 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. F 05/09/12 1. CONTROLLING DIMENSION : MM . 2. Reference document : JEDEC MO-207 NOTE : 08/21/2008 IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL 19 20 Θ NOTE : 07/06/2006 4. Formed leads shall be planar with respect to one another within 0.1mm at the seating plane after final test. 3. Dimension b does not include dambar protrusion/intrusion. 2. Dimension D1 adn E do not include mold protrusion . 1. Controlling dimension : mm Θ IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. F 05/09/12