R2A20112SP/DD Critical Conduction Mode Interleaved PFC Control IC REJ03D0904-0200 Preliminary Rev.2.00 Nov 13, 2007 Description The R2A20112 controls a boost converter to provide a active power factor correction. The R2A20112 adopts critical conduction mode for power factor correction and realizes high efficiency and a low switching noise by zero current switching. Interleaving function improve ripple current on input or output capacitor by 180 degrees phase shift. The feedback loop open detection, two mode overvoltage protection, overcurrent protection are built in the R2A20112, and can constitute a power supply system of high reliability with few external parts. Features • Maximum Ratings Supply voltage Vcc: 24 V Operating junction temperature Tjopr: –40 to +150°C • Electrical characteristics VREF output voltage VREF: 5.0 V ± 3% UVLO operation start voltage VH: 10.5 V ± 0.7 V UVLO operation shutdown voltage VL: 9.3 V ± 0.5 V UVLO hysteresis voltage Hysuvl: 1.2 V ± 0.5 V • Functions Boost converter control with critical conduction mode Interleaving control Two mode overvoltage protection Mode1: Dynamic OVP corresponding to a voltage rise by load change Mode2: Static OVP corresponding to overvoltage in stable Feedback loop open detection Master and Slave independence overcurrent protection 280 µs restart timer Package lineup: Pb-free SOP-16/DILP-16 REJ03D0904-0200 Rev.2.00 Nov 13, 2007 Page 1 of 7 R2A20112SP/DD Pin Arrangement ZCD-M 1 16 VCC ZCD-S 2 15 GD-M NC 3 14 PGND VREF 4 13 GD-S SGND 5 12 NC RT 6 11 OCP-M RAMP 7 10 OCP-S COMP 8 9 FB (Top view) Pin Functions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name ZCD-M ZCD-S N.C. VREF SGND RT RAMP COMP FB OCP-S OCP-M N.C. GD-S PGND GD-M VCC Input/Output Input Input — Output — Input/Output Input/Output Output Input Input Input — Output — Output Input REJ03D0904-0200 Rev.2.00 Nov 13, 2007 Page 2 of 7 Function Master converter zero current detection input terminal Slave converter zero current detection input terminal Open Reference voltage output terminal Ground for small signal circuit Oscillator frequency setting terminal Ramp waveform setting terminal Error amplifier output terminal Error amplifier input terminal Slave converter overcurrent detection terminal Master converter overcurrent detection terminal Open Slave converter Power MOSFET drive terminal Ground for power stage Master converter Power MOSFET drive terminal Supply voltage terminal R2A20112SP/DD Block Diagram ZCD-M VREF: 5 V 0.8V ~ 6.4V Clamp VCC UVLO ON: 10.5 V OFF: 9.3 V – + GD-M Vzcd_lo = 1.5 V 300 mVhys 0.8V ~ 6.4V NC Slave Control + OSC – + NC OCP COMP1 Vzcd_lo = 1.5 V 300 mVhys VREF GD-S OCP-S OCP-M TIMER OCP COMP2 SGND OCP-S OCP-S S Q OSC RT OCP-M – + Clamp – + ZCD-S PGND 0.3 V OCP-M R Q A GD Disable OVP BLOCK COMP Discharge FB – + S Q VCC Iramp – + 0.92 V RAMP R Ramp Low 0.2 V detect Error Amp – + FB 2.5 V A 9.1 V COMP Static OVP – + GD Disable COMP Discharge FB VFB × 1.09 V/100 mVhys Dynamic OVP – + VFB × 1.05 V + – 0.5 V/0.2 Vhys FB open detect OVP BLOCK REJ03D0904-0200 Rev.2.00 Nov 13, 2007 Page 3 of 7 R2A20112SP/DD Absolute Maximum Ratings (Ta = 25°C) Item Symbol Supply voltage GD-M Peak current GD-M DC current GD-S Peak current GD-S DC current ZCD terminal current RT terminal current Vref terminal current COMP terminal current Terminal voltage Ratings –0.3 to 24 ±200 ±10 ±200 ±10 ±10 –200 –5 ±1 –0.3 to Vcc –0.3 to Vref –0.3 to Vref+0.3 1 –40 to +150 –55 to +150 Vcc Ipk-gdm Idc-gdm Ipk-gds Idc-gds Izcd Irt Iref Icomp Vt-group1 Vt-group2 Vt-ref Pt Tj-opr Tstg Vref terminal voltage Power dissipation Operating junction temperature Storage temperature Unit V mA mA mA mA mA µA mA mA V V V W °C °C Note 3 3 4 5 6 Notes: 1. 2. 3. 4. Rated voltages are with reference to the SGND terminal. For rated currents, inflow to the IC is indicated by (+), and outflow by (–). Shows the transient current when driving a capacitive load. This is the rated voltage for the following pins: RAMP, FB 5. This is the rated voltage for the following pins: RT, OCP-M , OCP-S 6. In case of R2A20112DD (DILP): θja = 120°C/W In case of R2A20112SP (SOP): θja = 120°C/W This value is a thing mounting on 40 × 40 × 1.6 [mm], a glass epoxy board of wiring density 10%. Electrical Characteristics (Ta = 25°C, Vcc = 12 V, RT = 22 kΩ, OCP = GND, CRAMP = 680 pF, RZCD-GND = 51 kΩ, FB = COMP) Item Supply VREF Note: Symbol Min Typ Max Unit V Test Conditions UVLO Turn-on threshold Vuvlh 9.8 10.5 11.2 UVLO Turn-off threshold Vuvll 8.8 9.3 9.8 V UVLO hysteresis Hysuvl 0.7 1.2 1.7 V Standby current Istby — 120 200 µA Operating current Icc — 4.9 7.0 mA Output voltage Vref 4.85 5.00 5.15 V Line regulation Vref-line — 5 20 mV Isource = –1 mA, Vcc = 10 V to 24 V Load regulation Vref-load — 5 20 mV Isource = –1 mA to –5 mA Temperature stability dVref — ±80 — ppm/°C 1. Design spec. REJ03D0904-0200 Rev.2.00 Nov 13, 2007 Page 4 of 7 Vcc = 8.9 V, ZCD = Open Isource = –1 mA 1 Ta = –40 to 125°C * R2A20112SP/DD Electrical Characteristics (cont.) (Ta = 25°C, Vcc = 12 V, RT = 22 kΩ, OCP = GND, CRAMP = 680 pF, RZCD-GND = 51 kΩ, FB = COMP) Item Error amplifier RAMP Symbol Min Typ Max Unit Test Conditions Feedback voltage Vfb 2.40 2.50 2.60 V FB-COMP short, RAMP = 0 V Input bias current Ifb –0.5 0 0.5 µA Measured pin: FB Open loop gain Av — 60 — dB *1 Upper clamp voltage Vclamp-comp 8.0 9.1 10.6 V FB = 2.0 V, COMP: Open Low voltage Vl-comp — 0.1 0.3 V FB = 3.0 V, COMP: Open FB = 1.5 V, COMP = 2.5 V Source current Isrc-comp — –120 — µA Sink current 1 Isnkcomp1 — 120 — µA *1 Sink current 2 Isnkcomp2 — 300 — µA FB = 3.5 V, COMP = 2.5 V Transconductance gm 150 200 290 µs FB = 2.45 V ↔ 2.55 V, COMP = 2.5 V RAMP charge current Ic-ramp 130 150 170 µA RAMP = 0 V to 7 V RAMP discharge current Id-ramp 7 16 29 mA FB = 1 V, COMP = 2 V, RAMP = 0 V to 1.5 V to 1 V Low voltage Vl-ramp — 17 200 mV FB = 1 V, COMP = 3 V, RAMP = 0 V to 2.5 V to open Isink = 100 µA Zero Upper clamp voltage current detector Vzcdh 5.8 6.4 7.0 V Lower clamp voltage Vzcdl 0.3 0.8 1.3 V Isink = 3 mA ZCD low threshold voltage Vzcd_lo 1.05 1.50 1.75 V *1 ZCD hysteresis Hyszcd 180 300 390 mV *1 Input bias current Izcd –1 — 1 µA Phase delay Phase 160 180 200 deg. Isource = –3 mA 1.2 V < Vzcd < 5 V *1, *2 Slave control On time ratio Ton-ratio –5 — 5 % *1, *2 Restart Restart time delay Tstart 210 280 350 µs Cramp = 3300 pF FB = 2.0 V, COMP = 5 V Note: 1. Design spec. 2. Tperiod (25 µs) Ton-m (12.5 µs) GD-M Tdelay GD-S Phase = Tdelay × 360 [deg.] Tperiod Ton-ratio = 1 – Ton-s Ton-m × 100 [%] REJ03D0904-0200 Rev.2.00 Nov 13, 2007 Page 5 of 7 Ton-s R2A20112SP/DD Electrical Characteristics (cont.) (Ta = 25°C, Vcc = 12 V, RT = 22 kΩ, OCP = GND, CRAMP = 680 pF, RZCD-GND = 51 kΩ, FB = COMP) Item Gate drive Symbol Min Typ Max Unit Test Conditions Master gate drive rise time tr-gdm — 30 100 ns CL = 100 pF, Cramp = 3300 pF Slave gate drive rise time tr-gds — 30 100 ns CL = 100 pF, Cramp = 3300 pF Master gate drive fall time tf-gdm — 30 100 ns CL = 100 pF, Cramp = 3300 pF FB = 2.0 V, COMP = 5 V FB = 2.0 V, COMP = 5 V FB = 2.0 V, COMP = 5 V Slave gate drive fall time tf-gds — 30 100 ns Master gate drive low voltage Vol1-gdm — 0.05 0.2 V CL = 100 pF, Cramp = 3300 pF FB = 2.0 V, COMP = 5 V Over Isink = 2 mA Vol2-gdm — 0.03 0.7 Master gate drive high voltage Voh-gdm 11.5 11.9 — V Isink = 1 mA, VCC = 5 V Isource = –2 mA Slave gate drive low voltage Vol1-gds — 0.05 0.2 V Isink = 2 mA Vol2-gds — 0.03 0.7 Slave gate drive high voltage Voh-gds 11.5 11.9 — V Isink = 1 mA, VCC = 5 V OCP threshold voltage Vocp 0.27 0.3 0.33 V Dynamic OVP threshold voltage Vdovp VFB× 1.035 VFB× 1.050 VFB× 1.065 V Static OVP threshold voltage Vsovp VFB× 1.075 VFB× 1.090 VFB× 1.105 V COMP = Open Isource = –2 mA * current protection Over voltage protection Note: Static OVP hysteresis Hys-sovp 50 100 150 mV COMP = Open FB open detect threshold voltage Vfbopen 0.45 0.50 0.55 V COMP = Open FB open detect hysteresis Hysfbopen 0.16 0.20 0.24 V COMP = Open 1. Design spec. REJ03D0904-0200 Rev.2.00 Nov 13, 2007 Page 6 of 7 1 R2A20112SP/DD Package Dimensions JEITA Package Code P-SOP16-5.5x10.06-1.27 RENESAS Code PRSP0016DH-B *1 Previous Code FP-16DAV MASS[Typ.] 0.24g D F 16 NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. 9 c HE *2 E bp Index mark Terminal cross section ( Ni/Pd/Au plating ) 1 8 e Z *3 bp x Reference Dimension in Millimeters Symbol M A L1 θ A1 y L Detail F JEITA Package Code P-DIP16-6.3x19.2-2.54 RENESAS Code PRDP0016AE-B Previous Code DP-16FV D E A2 A1 A bp b1 c c1 θ HE e x y Z L L1 Min Nom Max 10.06 10.5 5.50 0.00 0.10 0.20 2.20 0.34 0.40 0.46 0.15 0.20 0.25 0° 8° 7.50 7.80 8.00 1.27 0.12 0.15 0.80 0.50 0.70 0.90 1.15 MASS[Typ.] 1.05g D 9 E 16 1 8 b3 0.89 A1 A Z L Reference Symbol e bp θ c e1 ( Ni/Pd/Au plating ) REJ03D0904-0200 Rev.2.00 Nov 13, 2007 Page 7 of 7 e1 D E A A1 bp b3 c θ e Z L Dimension in Millimeters Min Nom Max 7.62 19.2 20.32 6.3 7.4 5.06 0.51 0.40 0.48 0.56 1.30 0.19 0.25 0.31 0° 15° 2.29 2.54 2.79 1.12 2.54 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. 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