Preliminary Datasheet TBB1004 R07DS0314EJ1200 (Previous: REJ03G0842-1100) Rev.12.00 Mar 28, 2011 Twin Built in Biasing Circuit MOS FET IC VHF/UHF RF Amplifier Features • • • • • Small SMD package CMPAK-6 built in twin BBFET; To reduce using parts cost & PC board space. Suitable for World Standard Tuner RF amplifier. Very useful for total tuner cost reduction. Withstanding to ESD; Built in ESD absorbing diode. Withstand up to 200V at C=200pF, Rs=0 conditions. Provide mini mold packages; CMPAK-6 Outline RENESAS Package code: PTSP0006JA-A (Package name: CMPAK-6) 6 5 4 2 3 1 Notes: 1. Drain(1) 2. Source 3. Gate-1(1) 4. Gate-1(2) 5. Gate-2 6. Drain(2) 1. Marking is “DM”. 2. TBB1004 is individual type number of RENESAS TWIN BBFET. Absolute Maximum Ratings (Ta = 25°C) Item Drain to source voltage Gate1 to source voltage Symbol VDS VG1S Ratings 6 Unit V +6 -0 V Gate2 to source voltage VG2S V Drain current Channel power dissipation Channel temperature Storage temperature ID Pch*3 Tch Tstg +6 -0 30 250 150 –55 to +150 Note: mA mW °C °C 3. Value on the glass epoxy board (49mm × 38mm × 1mm). R07DS0314EJ1200 Rev.12.00 Mar 28, 2011 Page 1 of 8 TBB1004 Preliminary Electrical Characteristics The below specification are applicable for UHF unit (FET1) (Ta = 25°C) Item Drain to source breakdown voltage Gate1 to source breakdown voltage Gate2 to source breakdown voltage Gate1 to source cutoff current Gate2 to source cutoff current Gate1 to source cutoff voltage Symbol V(BR)DSS V(BR)G1SS V(BR)G2SS IG1SS IG2SS VG1S(off) Min 6 +6 +6 — — 0.5 Typ — — — — — 0.7 Max — — — +100 +100 1.0 Unit V V V nA nA V VG2S(off) 0.5 0.7 1.0 V Drain current ID(op) 13 17 21 mA VDS = 5 V, VG1 = 5 V VG2S = 4 V, RG = 100 kΩ Forward transfer admittance |yfs| 21 26 31 mS Input capacitance Output capacitance Ciss Coss 1.4 1.0 1.8 1.4 2.2 1.8 pF pF Reverse transfer capacitance Power gain Noise figure Crss PG NF — 16 — 0.02 21 1.7 0.04 — 2.5 pF dB dB VDS = 5 V, VG1 = 5 V, VG2S = 4 V RG = 100 kΩ, f = 1 kHz VDS = 5 V, VG1 = 5 V VG2S =4 V, RG = 100 kΩ f = 1 MHz Gate2 to source cutoff voltage Test conditions ID = 200 μA, VG1S = VG2S = 0 IG1 = +10 μA, VG2S = VDS = 0 IG2 = +10 μA, VG1S = VDS = 0 VG1S = +5 V, VG2S = VDS = 0 VG2S = +5 V, VG1S = VDS = 0 VDS = 5 V, VG2S = 4 V ID = 100 μA VDS = 5 V, VG1S = 5 V ID = 100 μA VDS = VG1 = 5 V, VG2S = 4 V RG = 100 kΩ, f = 900 MHz Zi = S11*, Zo = S22*(:PG) Zi = S11opt (:NF) The below specification are applicable for VHF unit (FET2) (Ta = 25°C) Item Drain to source breakdown voltage Gate1 to source breakdown voltage Gate2 to source breakdown voltage Gate1 to source cutoff current Gate2 to source cutoff current Gate1 to source cutoff voltage Symbol V(BR)DSS V(BR)G1SS V(BR)G2SS IG1SS IG2SS VG1S(off) Min 6 +6 +6 — — 0.5 Typ — — — — — 0.75 Max — — — +100 +100 1.0 Unit V V V nA nA V VG2S(off) 0.5 0.75 1.0 V Drain current ID(op) 16 20 24 mA VDS = 5 V, VG1 = 5 V VG2S = 4 V, RG = 100 kΩ Forward transfer admittance |yfs| 27 32 37 mS Input capacitance Output capacitance Reverse transfer capacitance Power gain Noise figure Ciss Coss Crss PG NF 2.3 1.4 — 24 — 2.7 1.8 0.03 29 1.2 3.1 2.2 0.05 — 1.7 pF pF pF dB dB VDS = 5 V, VG1 = 5 V, VG2S = 4 V RG = 100 kΩ, f = 1 kHz VDS = 5 V, VG1 = 5 V VG2S = 4 V, RG = 100 kΩ f = 1 MHz Gate2 to source cutoff voltage R07DS0314EJ1200 Rev.12.00 Mar 28, 2011 Test conditions ID = 200 μA, VG1S = VG2S = 0 IG1 = +10 μA, VG2S = VDS = 0 IG2 = +10 μA, VG1S = VDS = 0 VG1S = +5 V, VG2S = VDS = 0 VG2S = +5 V, VG1S = VDS = 0 VDS = 5 V, VG2S = 4 V ID = 100 μA VDS = 5 V, VG1S = 5 V ID = 100 μA VDS = VG1 = 5 V, VG2S = 4 V RG = 100 kΩ, f = 200 MHz Page 2 of 8 TBB1004 Preliminary Test Circuits • DC Biasing Circuit for Operating Characteristic Items (ID(op), |yfs|, Ciss, Coss, Crss, NF, PG) Measurment of FET1 Gate 2 Open VG2 ID Open RG A VG1 Gate 1 Drain VD Source Measurment of FET2 VG2 Gate 2 Drain ID Gate 1 A RG VG1 VD Open Open Source R07DS0314EJ1200 Rev.12.00 Mar 28, 2011 Page 3 of 8 TBB1004 Preliminary • Equivalent Circuit No.1 No.6 Drain(1) Drain(2) BBFET-(1) BBFET-(2) No.2 No.5 Source Gate-2 No.3 No.4 Gate-1(1) Gate-1(2) • 200 MHz Power Gain, Noise Figure Test Circuit VT VG2 VT 1000p 1000p 1000p 47k 47k 1000p 47k TWINBBFET Output (50Ω) 1000p L2 Input (50Ω) L1 10p max 1000p 1000p 1SV70 36p RG RFC 100k 1SV70 1000p VD = VG1 Unit : Resistance (Ω) Capacitance (F) L1 : φ1mm Enameled Copper Wire,Inside dia 10mm, 2Turns L2 : φ1mm Enameled Copper Wire,Inside dia 10mm, 2Turns RFC : φ1mm Enameled Copper Wire,Inside dia 5mm, 2Turns R07DS0314EJ1200 Rev.12.00 Mar 28, 2011 Page 4 of 8 TBB1004 Preliminary Typical Output Characteristics (FET1) 200 100 0 50 100 150 0 kΩ kΩ G = R 15 10 kΩ 0 12 kΩ 0 15 10 0k 18 5 0 200 68 VG2S = 4 V VG1 = VDS 20 82 300 kΩ 25 400 Drain Current ID (mA) Channel Power Dissipation Pch* (mW) Maximum Channel Power Dissipation Curve 1 2 3 Ω 4 5 Drain to Source Voltage VDS (V) Ambient Temperature Ta (°C) * Value on the glass epoxy board (49mm × 38mm × 1mm) Forward Transfer Admittance vs. Gate1 Voltage (FET1) 25 Drain Current ID (mA) 20 VDS = 5 V RG = 100 kΩ 4V 15 3V 10 2V 5 VG2S = 1 V 0 1 2 3 4 5 Forward Transfer Admittance |yDfs| (mS) Drain Current vs. Gate1 Voltage (FET1) 50 VDS = 5 V VG2S = 4 V 40 30 150 kΩ 20 10 0 1 Gate1 Voltage VG1 (V) 3 4 5 Input Capacitance vs. Gate2 to Source Voltage (FET1) 30 20 15 10 5 20 50 100 200 500 1000 Gate Resistance RG (kΩ) R07DS0314EJ1200 Rev.12.00 Mar 28, 2011 Input Capacitance Ciss (pF) 4 VDS = 5 V VG1 = 5 V VG2S = 4 V 25 Drain Current ID (mA) 2 Gate1 Voltage VG1 (V) Drain Current vs. Gate Resistance (FET1) 0 10 RG = 68 kΩ 100 kΩ 3 2 VDS = 5 V VG1 = 5 V RG = 100 kΩ f = 1 MHz 1 0 0 1 2 3 4 Gate2 to Source Voltage VG2S (V) Page 5 of 8 TBB1004 Preliminary Drain Current vs. Gate1 Voltage (FET2) Typical Output Characteristics (FET2) 25 Ω kΩ Drain Current ID (mA) kΩ 68 82 k G = 0 10 12 0 15 kΩ 20 VG2S = 4 V VG1 = VDS R Drain Current ID (mA) 25 kΩ 0 15 Ω 0k 18 10 5 20 VDS = 5 V RG = 100 kΩ 4V 3V 15 2V 10 5 VG2S = 1 V 1 2 3 4 0 5 2 3 4 Gate1 Voltage VG1 (V) Forward Transfer Admittance vs. Gate1 Voltage (FET2) Drain Current vs. Gate Resistance (FET2) 50 5 30 VDS = 5 V VG2S = 4 V 40 RG = 68 kΩ 100 kΩ 30 150 kΩ 20 10 VDS = 5 V VG1 = 5 V VG2S = 4 V 25 20 15 10 5 0 1 2 3 4 0 10 5 Gate1 Voltage VG1 (V) 20 50 100 200 500 1000 Gate Resistance RG (kΩ) Power Gain vs. Gate Resistance (FET2) Input Capacitance vs. Gate2 to Source Voltage (FET2) 40 4 35 Power Gain PG (dB) Input Capacitance Ciss (pF) 1 Drain to Source Voltage VDS (V) Drain Current ID (mA) Forward Transfer Admittance |yfs| (mS) 0 3 2 VDS = 5 V VG1 = 5 V RG = 100 kΩ f = 1 MHz 1 0 0 1 25 20 15 2 3 4 Gate2 to Source Voltage VG2S (V) R07DS0314EJ1200 Rev.12.00 Mar 28, 2011 30 10 10 VDS = 5 V VG1 = 5 V VG2S = 4 V f = 200 MHz 20 50 100 200 500 1000 Gate Resistance RG (kΩ) Page 6 of 8 TBB1004 Preliminary Noise Figure vs. Gate Resistance (FET2) Gain Reduction vs. Gate2 to Source Voltage (FET2) 0 3 VDS = 5 V VG1 = 5 V VG2S = 4 V f = 200 MHz Gain Reduction GR (dB) Noise Figure NF (dB) 4 2 1 0 10 10 20 30 50 20 50 100 200 Gate Resistance RG (kΩ) R07DS0314EJ1200 Rev.12.00 Mar 28, 2011 500 1000 VDS = VG1 = 5 V RG = 100 kΩ 40 4 3 2 1 0 Gate2 to Source Voltage VG2S (V) Page 7 of 8 TBB1004 Preliminary Package Dimensions JEITA Package Code SC-88 Package Name CMPAK-6 RENESAS Code PTSP0006JA-A D Previous Code CMPAK-6 / CMPAK-6V MASS[Typ.] 0.006g A e Q c E HE LP L A A x M L1 S A3 b A Reference Symbol e A2 A A1 y S S e1 b l1 c b2 A-A Section Pattern of terminal position areas A A1 A2 A3 b c D E e HE L L1 LP x y b2 e1 l1 Q Dimension in Millimeters Min 0.8 0 0.8 0.15 0.1 1.8 1.15 2.0 0.3 0.1 0.2 Nom 0.9 0.25 0.2 0.15 2.0 1.25 0.65 2.1 Max 1.1 0.1 1.0 0.25 0.25 2.2 1.35 2.2 0.7 0.5 0.6 0.05 0.05 0.35 1.5 0.9 0.25 Ordering Information Orderable Part Number TBB1004DMTL-E TBB1004DMTL-H Note: Quantity 3000 Shipping Container φ 178 mm Reel, 8 mm Emboss Taping For some grades, production may be terminated. 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