XC878 Product Overview

XC878 series
8-bit microcontrollers with
64K Flash and CAN connectivity
New member to cost-effective
XC800 8-bit Family
July 2008
Agenda
„ XC878 Product Presentation (Technical Overview)
†
†
†
†
Family Overview
System & Core
Embedded Memories
Standard Peripherals
¬
¬
¬
¬
GPIO
Timers & WDT
UART & LIN
SSC
† Special Peripherals
¬
¬
¬
¬
¬
ADC
CAPCOM6E
T2CCU
MultiCAN
MDU & Cordic
† Debug Support & Toolchain
28.06.2007
Copyright © Infineon Technologies 2007. All rights reserved.
Page 2
Roadmap for XC800 Family
28.06.2007
Copyright © Infineon Technologies 2007. All rights reserved.
Page 3
New XC878 Series on a Glance
Applications
: Automotive Body: Power Closure Systems, Steering lock , Immobilizers
: Motor Control: Air conditioners, White goods, Forklifts, Automation
: Building control: Compressors, pumps, Fans, LED lighting
Advantage
Advanced peripheral integration for motor control performance
FOC + PFC on a single MCU together with CAN connectivity
: 64KB Flash, 3KB RAM and CAN connectivity Identify which feature is
most important to the
Key Benefits : Powerful motor control features: Vector Computer,
ADClisted
,CCU6E
customers
above
to Customers : 2 PWM timers with 8 PWM channels and 4 independent time bases
: Integrated safety features: Voltage &Clock supervisory, ECC
Eval Boards
28.06.2007
XC878 Easy Kit €99
Copyright © Infineon Technologies 2007. All rights reserved.
Page 4
XC878 Product Block Diagram
„ 64KB Flash, 3KB RAM and CAN
connectivity
„ Powerful motor control features:
Vector Computer, ADC ,CCU6E
† Enables Field Oriented Control
at lowest system cost
„ 2 PWM Modules with 10 PWM
channels and 4 independent
time bases
„ Enables PFC + FOC motor
control on a single MCU
„ Integrated safety features:
Voltage & Clock supervisory,
ECC
„ Supporting Documentation
www.infineon.com/XC878
–
–
–
–
28.06.2007
Copyright © Infineon Technologies 2007. All rights reserved.
AppNotes
Data Sheets
Users Manual
Hands On Training
Page 5
Pin-Out Compatibility within XC800 Family
† LQFP64 and LQFP48
XC878 and
XC888
† Body Size
LQFP64
10.0 x 10.0
† Pin Pitch
28.06.2007
„ LQFP64 and TSSOP38
LQFP48
7.0 x 7.0
TSSOP38
9.7 x 4.4
0.5mm
Copyright © Infineon Technologies 2007. All rights reserved.
TSSOP20
6.5 x 4.4
0.65mm
Page 6
Migration from XC886/888 to XC878
„ Migration guide is available Æ Starterkit CD
„ List of differences:
† Memory Extension
† Flash Architecture
† Clock System
† EVR and Interrupts
† Bootstrap Loader
† Pinout
„ Note: Actual Starter Kit CD contents is available on
www.infineon.com\xc878
28.06.2007
Copyright © Infineon Technologies 2007. All rights reserved.
Page 7
Agenda
„ XC878 Product Presentation (Technical Overview)
†
†
†
†
Family Overview
System & Core
Embedded Memories
Standard Peripherals
¬
¬
¬
¬
GPIO
Timers & WDT
UART & LIN
SSC
† Special Peripherals
¬
¬
¬
¬
¬
ADC
CAPCOM6E
T2CCU
MultiCAN
MDU & Cordic
† Debug Support & Toolchain
28.06.2007
Copyright © Infineon Technologies 2007. All rights reserved.
Page 8
System Control Unit – EVR & Powerup
„ Dual voltage supply concept
„ Embedded Voltage Regulator (EVR)
„ Features:
† Input voltage
– pad supply VDDP: 3V / 5V
† Output voltage
– core supply VDDC: 2.5V
† Main EVR can be turned off
(power down mode)
† Auxiliary EVR maintains RAM and
wake-up logic (power down mode)
† EVR needs external buffer
capacitor on pins VDDC / VSSC
† CPU and all peripherals (including
flash & ADC) are running at VDDC
¬ all modules are widely indepent on
pad supply VDDP
† Power On RESET and Brownout
RESET generation
28.06.2007
Copyright © Infineon Technologies 2007. All rights reserved.
Page 9
System Control Unit – Clock System
RC-OSC
CAN / CC6 / T2CCU /
Cordic / MDU
@53.3MHz
ext. OSC
default
28.06.2007
OR
core & flash
@26.7MHz
Copyright © Infineon Technologies 2007. All rights reserved.
Page 10
System Control Unit – Interrupt Controller
„ Interrupt Controller
† 14 interrupt vectors with
four priority levels
¬ up to 15 external
interrupts
† Non-Maskable interrupt
(NMI); highest priority
28.06.2007
Copyright © Infineon Technologies 2007. All rights reserved.
Page 11
System Control Unit – Power Management
„ Four Power Management Modes
† Active Mode
¬ peripherals can be
individually enabled/disabled
† Idle Mode
¬ CPU is off and wakes up on
any interrupt
† Slowdown Mode
¬ CPU and all modules are
clocked down
¬ prescaler /1, /2, /3, /4, /5,
/8, etc...
Mode
Typical current
consumption
Active
~37mA
Idle
~29mA
Slow Down
(fsys/2048)
~9mA
Power Down
[email protected]°C
† Powerdown Mode
¬ CPU and all peripherals are
clockless
¬ main EVR is off
¬ wakeuplogic active
¬ RAM/SFRs keep value
¬ wakeup thru EXINT0 or
RESET
28.06.2007
Copyright © Infineon Technologies 2007. All rights reserved.
Page 12
System Control Unit – Fail Safe
„ XC878 provides Hardware functions to meet Safety standards:
† Class B, Class C, IEC 60730
28.06.2007
Copyright © Infineon Technologies 2007. All rights reserved.
Page 13
Boot-Concept
Bootstrap Loader Options
UART
LIN
CAN
ALTERNATE
download to
XRAM or Flash
download to XRAM
jumps to user defined
Flash address
Mark
„C“
„L“
„CM“
„-“
UART
x
-
x
x
LIN
-
x
CAN
x
-
Boot
x
-
„ BSL is entered
† with MBC = 0 (always)
† with MBC = 1 (if flash @0x0000 is zero)
„ Booting only on pins
† P1.0/RXD/RXDC0_0
† P1.1/TXD/TXDC0_0
„ Booting always supports autobaudrate detection
„ MultiCan Booting
† point-to-point connection
† external clock required
¬ default 8MHz (initial programming)
28.06.2007
Copyright © Infineon Technologies 2007. All rights reserved.
Page 14
Agenda
„ XC878 Product Presentation (Technical Overview)
†
†
†
†
Family Overview
System & Core
Embedded Memories
Standard Peripherals
¬
¬
¬
¬
GPIO
Timers & WDT
UART & LIN
SSC
† Special Peripherals
¬
¬
¬
¬
¬
ADC
CAPCOM6E
T2CCU
MultiCAN
MDU & Cordic
† Debug Support & Toolchain
28.06.2007
Copyright © Infineon Technologies 2007. All rights reserved.
Page 15
Memory Layout
„ XC878 – 13FF (52K flash)
† compatible to XC886
„ XC878 – 16FF (64K flash)
† banking for XRAM
3k XRAM
3k XRAM
@ 0xF000
@ 0xF000
Bank 0
Bank 16
MEX3 = 0
MEX3 = 0x1F
64k
64k
28.06.2007
Copyright © Infineon Technologies 2007. All rights reserved.
Page 16
Memory Layout – Flash
4-KByte block of flash memory
(D-Flash) used for
emulation of EEPROM data
60-KByte block of flash memory
(P-Flash) used
for code or constant data
28.06.2007
Copyright © Infineon Technologies 2007. All rights reserved.
Page 17
Flash Architecture
„ XC878 has two independent Flash-Blocks:
† PFLASH (48/60k) & DFLASH (4k)
¬ both can be used for CODE and DATA
¬ but DFLASH is capable for „background EEPROM emulation“
† for data integrity a hardware error correction (ECC) is provided
† Flash Readout- and Write-Protection mechanism
„ Characteristics for Programming & Erase:
PFLASH
20-40us
Programming Time
Page Erase Time
20ms
Mass Erase Time
200ms
Min Programming Width
1 Byte
Max Programming Width
28.06.2007
DFLASH
64 Bytes
32 Bytes
Min Erase Width
512 Bytes
64 Bytes
Max Erase Width
60k
4k
Copyright © Infineon Technologies 2007. All rights reserved.
Page 18
Flash Retention & Endurance
„ Characteristics for Retention & Endurance for DFLASH:
Automotive
Endurance
[cycles]
Retention
[years]
Size
[bytes]
1k
15
4096
10k
5
1024
2
512
1
2048
120k
2
512
emulation mode using
dataset size of 128bytes
Endurance
[cycles]
Retention
[years]
Size
[bytes]
Remark
1k
15
4096
10k
10
4096
30k
5
4096
100k
1
4096
30k
Industrial
28.06.2007
Copyright © Infineon Technologies 2007. All rights reserved.
Remark
non-emulated
non-emulated
Page 19
Agenda
„ XC878 Product Presentation (Technical Overview)
†
†
†
†
Family Overview
System & Core
Embedded Memories
Standard Peripherals
¬
¬
¬
¬
GPIO
Timers & WDT
UART & LIN
SSC
† Special Peripherals
¬
¬
¬
¬
¬
ADC
CAPCOM6E
T2CCU
MultiCAN
MDU & Cordic
† Debug Support & Toolchain
28.06.2007
Copyright © Infineon Technologies 2007. All rights reserved.
Page 20
GPIO
„ Flexible IO
configuration
„ Two driver strength
„ Open drain mode
„ Selectable
pullup/down devices
„ Up to 4 alternate
output functions on
each I/O
„ Up to 15 external
interrupts on
different nodes
28.06.2007
Copyright © Infineon Technologies 2007. All rights reserved.
Page 21
Timers T0, T1
„ Incremented once every fsys / 2
„ Timer Modes
† Mode 0: 13-bit timer
† Mode 1: 16-bit timer
† Mode 2: 8-bit timer with auto-reload
† Mode 3; T0 is configured as two 8-bit timers. T1 holds the count.
† external counter mode
† two interrupt vectors for T0 / T1
28.06.2007
Copyright © Infineon Technologies 2007. All rights reserved.
Page 22
Timers T2, T21
„ T2 / T21 have same functionality
† 16bit up/down-count with
autoreload
† capture – T2EX
† external start – T2EX
† output toggle – EXF2
† external count input – T2
„ large prescaler arrangement
„ supports automatic baudrate
capture for UART/UART1
„ two interrupt vectors on shared
nodes
28.06.2007
Copyright © Infineon Technologies 2007. All rights reserved.
Page 23
Watchdog Timer
„ Window Watchog Timer
† Provides a reliable and secure way to detect and
recover from SW or HW failures
„ If the WDT is not serviced (refreshed) within the allowed
window a system malfunction is assumed and an internal
RESET is performed
„ The window can be freely programmed
28.06.2007
Copyright © Infineon Technologies 2007. All rights reserved.
Page 24
UART / UART1
„
„
„
„
„
„
„
„
Two independent UART modules
Full Duplex
Receive Double Buffered
8/9-bit UART with a variable baud rate
Integrated Baudrate Generator
Integrated Fractional Divider for accurate baudrate adjustment
Autobaudrate capture feature for LIN2.0 header
Two interrupt vectors for UART/UART1
28.06.2007
Copyright © Infineon Technologies 2007. All rights reserved.
Page 25
SSC
„ High Speed Synchronous Serial Interface
† Supports both full-duplex and half-duplex serial synchronous
communication up to 13.3 MBaud
† Serial clock signal can be generated by the SSC (in Master mode) or
can be received from an external master (Slave mode).
† Transmission and reception is double-buffered.
† A 16-bit baud-rate generator provides a separate clock signal.
† Communication with SPI compatible devices is supported
† Flexible data format
¬ Programmable number of data bits: 2 to 8 bits
¬ Programmable shift direction: LSB or MSB shift first
¬ Programmable clock polarity: idle low or high state for the shift
clock
¬ Programmable clock/data phase: data shift with leading or
trailing edge of the shift clock.
† Interrupt generation
¬ On a transmitter empty condition
¬ On a receiver full condition
¬ On an error condition (receive, phase, baud rate, transmit error)
28.06.2007
Copyright © Infineon Technologies 2007. All rights reserved.
Page 26
Agenda
„ XC878 Product Presentation (Technical Overview)
†
†
†
†
Family Overview
System & Core
Embedded Memories
Standard Peripherals
¬
¬
¬
¬
GPIO
Timers & WDT
UART & LIN
SSC
† Special Peripherals
¬
¬
¬
¬
¬
ADC
CAPCOM6E
T2CCU
MultiCAN
MDU & Cordic
† Debug Support & Toolchain
28.06.2007
Copyright © Infineon Technologies 2007. All rights reserved.
Page 27
ADC
„ ADC – Block Diagram
Result 0
Converter
analog
Result 1
Result 2
Result 3
Result Assignment
Sample Time Adjust
Channel
Control
Cancel- Inject Repeat
28.06.2007
Request
Control
Copyright © Infineon Technologies 2007. All rights reserved.
8 / 9/ 10 / 11 bit
limit checker
Result
Control
Interrupt
Generation
Autoscan
digital
Request
Sources
Sequence
Timer
Software
Page 28
ADC – Features
„ ADC Characteristics
† 8 channels with 10bit resolution
† TUE = +/- 3 lsb, DNLE = +/- 2 lsb, INLE = +/- 2 lsb
† sample time down to 75ns
† conversion time down to [email protected] and [email protected]
„ ADC Features
† Fully autonomous peripheral which off loads CPU while
converting
¬
¬
¬
¬
¬
¬
¬
ADC triggering and result storage is solved in hardware
background conversions in a defined sequence are possible
limit & boundary checking with interrupt (comparator mode)
autoscan and queued conversion on several channels
result accumulator & data reduction filter (median filter)
timetriggered and injected conversions (hardware arbitration)
8, 9, 10, 11 bits result
more details on Starterkit CD
28.06.2007
Copyright © Infineon Technologies 2007. All rights reserved.
Page 29
ADC– Limit and Boundary Checking
Comparator Mode
• comparator mode
is selective per
channel
• limit is global for
all channels
• 4bits for upper &
lower limit
• 8 combinations
with 3 areas
Reduced
Reduced CPU
CPU load
load
Software
Software interaction
interaction for
for interesting
interesting results
results only
only
28.06.2007
Copyright © Infineon Technologies 2007. All rights reserved.
Page 30
ADC – Arbitration on Trigger Sources
Sequential and Parallel Source
Full
Full hardware
hardware support
support on
on priotization
priotization
Software
Software is
is decoupled
decoupled from
from hardware
hardware
28.06.2007
Copyright © Infineon Technologies 2007. All rights reserved.
Page 31
CAPCOM6E
„ CAPCOM6E – Block Diagram
28.06.2007
Copyright © Infineon Technologies 2007. All rights reserved.
Page 32
CAPCOM6E
„ Timer 12 features
† Three capture/compare channels (each can be used as capture or as
compare)
† Supports generation of a three-phase PWM
† 16-bit resolution
† Dead-time control for each channel (avoid short-circuits in power
stage)
† Concurrent update of the required T12/T13 registers
† Center aligned and edge aligned PWM
† Single shot mode
† Hysteresis-like control mode
† Hall-mode for multiphase BLDC motors
„ Timer 13 features
†
†
†
†
†
28.06.2007
One independent compare channel with one output
16-bit resolution
Can be sychonized to T12
Interrupt generation at period-match and compare-match
Single-shot mode supported
Copyright © Infineon Technologies 2007. All rights reserved.
Page 33
CAPCOM6E
„ Additional Features
† Block commutation for Brushless DC-drives implemented
† Position detection via Hall-sensor pattern
† Automatic rotational speed measurement for block
commutation
† Integrated error handling
† Fast emergency stop with CPU load via external signal
(CTRAP)
† Control modes for multi-channel AC-drives
† Output levels can be selected and adapted to the power stage
„ Module Interface
† T12 and T13 can be started from external pin (T12HR, T13HR)
† ADC can be synchronized on
¬
¬
¬
¬
¬
¬
28.06.2007
T12PM
T12CM0,1,2
T13PM
T13CM
STR
CHE
Copyright © Infineon Technologies 2007. All rights reserved.
Page 34
CAPCOM6E – FOC of BLDC Motors
„ T12 Generates Symmetric PWM with Dead-Time
„ T13 in single shot mode and synchronized to T12 generates 2 A/D
Triggers for current measurement
T12
FCPU
CC
CC Channel
Channel 00 CC0
CC0
CC0
COUT0
CC1
COUT1
CC2
COUT2
CC
CC Channel
Channel 22 CC2
CC2
T13 Compare
Timer 16-bit
Period
Register
Period
Reg.
Period
PeriodRegister
Reg.
28.06.2007
CTRAP
CC
CC Channel
Channel 11 CC1
CC1
T12
Capture/Compare
Timer 16-bit
deadtime
deadtime
Control
Control
FCPU
Mode
A/D Triggers
Port Control Logic
Period Register
Period Register
Burst Mode
Compare
Register
Comp
CC3
Compare
Register
CompReg.
Reg.
CC3
Block
Commutation
Control
Copyright © Infineon Technologies 2007. All rights reserved.
COUT3
INT0
INT1
INT2
M
Page 35
CAPCOM6E – BLDC Motors with Hall Sensors
Period
PeriodRegister
Register
Mode
CC
Channel
11 CC1
Delay
CCPhase
Channel
CC1
Phase
Delay
T12
T12
T12
Capture/Compare
Capture/Compare
Capture/Compare
Timer 16-bit
16-bit
Timer
Timer
16-bit
Time
Out
CC
CC2
Time
Out (Stall
(Stall22Detect)
Detect)
CC Channel
Channel
CC2
Hall
deadtime
Hall Effect
Effect
Noise
Control
Noise Filter
Filter
FCPU
T13
T13
Compare
CompareTimer
Timer
16-bit
16-bit
Port Control Logic
CC
Speed
CC Channel
Channel
CC0
Speed00 CC0
T12
FCPU
CTRAP
Burst Mode
Comp
CMP2
Comp
Register
Comp
Reg.
CMP2
CompReg.
Register
Block
Block
Commutation
Commutation
Control
Control
Period
Reg.
Period
Register
Period
Reg.
CC0
COUT0
CC1
COUT1
CC2
COUT2
COUT3
INT0
INT1
INT2
A/D Trigger
more details on Starterkit CD
28.06.2007
Copyright © Infineon Technologies 2007. All rights reserved.
Hall Effect
Sensors
Page 36
T2CCU – Overview
„ T2CCU is a simplified
Capture/Compare Unit
† one 16bit autoreload timer
which counts up
† programmable reload
value
† interrupt on overflow
† 6 independent capcom
channels interrupt
† two selectable time base
units: CCT or T2
† clock prescaler options up
to ft2ccu = 2x fcpu
(48MHz)
† synchronize features for
CCT & T2
† ADC trigger features
28.06.2007
Copyright © Infineon Technologies 2007. All rights reserved.
Page 37
T2CCU – Applications
„ T2CCU can be used for
† stepper motor control (full-/half-/microstep)
† 6 channel PWM generation (e.g. LED control)
† 3 phase PWM with deadtime (motor control, PFC, lampballast)
† multiple trigger pulses (e.g. for valve control)
† capturing external events
28.06.2007
Copyright © Infineon Technologies 2007. All rights reserved.
Page 38
T2CCU – PWM Generation
„ Compare Mode 0:
† output change (set / reset) on
¬
compare and overflow
† up to 6 channels
† 2 can be combined with PolA/B and
deadtime for 3 phase halfbridge
control
„ shadow transfer mechanism for
compare value update
† update compare channels
† set TXOF
† clear TXOF
† compare value is active with next
timer overflow
„ note: compare value must not be
smaller than reload value
28.06.2007
Copyright © Infineon Technologies 2007. All rights reserved.
Page 39
T2CCU – Pulse Pattern Generation
„ Compare Mode 1:
† use this mode for flexible
pulse pattern generation
† use TXOF for timer
synchronous update for
shadow transfer of all
compare values
28.06.2007
Copyright © Infineon Technologies 2007. All rights reserved.
Page 40
T2CCU – Stepper Motor Control
„ Concurrent Compare Mode:
¬ similar to Compare Mode 1
„
„
„
„
† but only Compare 0 register has
to be written
Stepper Motor Control
† fullstep / halfstep mode
† timer period refers to speed
† equidistant compare values
use ENSHDW to update next
compare value
pattern & time schedule table can
be used
note: realtime update is mandatory
28.06.2007
Copyright © Infineon Technologies 2007. All rights reserved.
Page 41
T2CCU – Capturing External Events
„ Capture Modes :
† capture external events on
¬ rising / falling / both edges
† soft-capture – read actual
timervalue
† individual interrupt flags for
every capture event
„ note: take care on timer
overflow while capturing
more details on Starterkit CD
28.06.2007
Copyright © Infineon Technologies 2007. All rights reserved.
Page 42
MultiCAN
„ ISO 11898 compliant CAN module
(V2.0B active)
„ 2 independent CAN nodes, with
dedicated control registers for each
CAN node
„ 32 independent message objects
with acceptance mask filtering for
each MO
„ Data transfer rate up to 1MBaud
„ Flexible and powerful message
transfer control (double chained
list) and error handling capabilities
to offload CPU
„ Automatic gateway mode support
„ CAN Analyzer Mode for bus
monitoring
28.06.2007
Copyright © Infineon Technologies 2007. All rights reserved.
Page 43
MultiCAN Module Conformance Test
„ CAN Conformance test
for XC88xC passed
„ CAN Gateway test passed
ate
c
i
f
i
t
r
e
C
granted
more details on Starterkit CD
28.06.2007
Copyright © Infineon Technologies 2007. All rights reserved.
Page 44
Coprocessors – MDU
„ MDU can be used
for e.g.
† long divisions
† shifting data for
scaling operations
† together with
Cordic in
interleaved mode
† example code
available
„ MDU runs at 2xfcpu at XC878
„ CPU has to MOVE the operands and result
† e.g. signed multiplication 16bit x 16bit: number of clocks
32 (load operands) + 16/2 (multiplication) + 32 (fetch result) = 72clk =
3.0µs @ 24MHz
„ For continues MDU operation, next operands can be loaded in parallel to current
calculation
† e.g. continuous (interleaved) signed multiplication 16bit x 16bit:
16/2(multiplication) || 32 (load operands for next multiplication) + 32 (fetch
result) = 56clk = 2.3µs @ 24MHz
28.06.2007
Copyright © Infineon Technologies 2007. All rights reserved.
Page 45
Coprocessors – Cordic
„ Cordic (COordinate Rotation
DIgital Computer)
† Mathematical co-processor for
16bit trigonometric, hyperbolic
and linear functions (e.g. to
solve SIN, COS, LOG, EXP,
SQRT...)
† Hardcoded - Look Up Table
based on iterative
approximation algorithm (16
iterations, max 41 cycles =
1.7us @24MHz)
† Cordic runs at 2xfcpu at XC878
„ Cordic can be used for e.g.
† PI Controller
† PT1 Filter
† Clark / Park Transformation
† Space Vector Modulator
† ... example code available
28.06.2007
Copyright © Infineon Technologies 2007. All rights reserved.
Page 46
Cordic – Math Functions
CORDIC
IN
Linear
MUL/DIV/MAC OUT
K=1
Circular
SINE/COSINE
angle/
magnitude
K = 1.64676
IN
OUT
IN
Hyperbolic
K = 0.828
Rotation
Vectoring
xn,zn,yn
xn,yn,zn
yn+1 = xn * zn + yn
zn+1 = yn / xn + zn
zn=angle, xn=1/K,yn=0
xn,yn, zn=0
xn+1 = cos(angle)
yn+1 = sin(angle)
zn+1 = arctan(yn/xn )
xn+1 = K*(xn2 + yn2)1/2
z1=angle,x1=1/K,y1=0
OUT
xn+1 = cosh(angle)
yn+1 = sinh(angle)
y1 < x1, z1=0
zn+1 = arctanh(y1/x1)
xn+1 = K*(x12 - y12)1/2
more details on Starterkit CD
28.06.2007
Copyright © Infineon Technologies 2007. All rights reserved.
Page 47
Agenda
„ XC878 Product Presentation (Technical Overview)
†
†
†
†
Family Overview
System & Core
Embedded Memories
Standard Peripherals
¬
¬
¬
¬
GPIO
Timers & WDT
UART & LIN
SSC
† Special Peripherals
¬
¬
¬
¬
¬
ADC
CAPCOM6E
T2CCU
MultiCAN
MDU & Cordic
† Debug Support & Toolchain
28.06.2007
Copyright © Infineon Technologies 2007. All rights reserved.
Page 48
On-Chip Debug Support
„ On-Chip Debug Support (OCDS)
† Two interfaces can be used to access the OCDS system:
¬ The JTAG interface is the primary channel
¬ The UART is an alternative channel
† Two dedicated pins are used for external configuration
¬ TMS – JTAG activate (active high, integrated pulldown)
¬ MBC – Bootstraploader activate (active low, external pullup required)
† Breakpoints:
¬ Up to 4 HW breakpoints on CODE and DATA
¬ Unlimited SW breakpoints using the TRAP instruction within the code
– The TRAP_EN bit must be set to 1 within the Extended Operation
(EO) register.
28.06.2007
Copyright © Infineon Technologies 2007. All rights reserved.
Page 49
Getting Started Tools
„ Starterkits, EasyKits,
Evaluation Boards
† for the XC800 family we
offer hardware kits which
can be ordered easily on
¬ www.ehitex.de Æ Starter
Kits for XC800
„ All kits come with a complete
toolchain with getting started
presentation and tested
example code - they are
ready for use.
„ The goal is that the getting
started example can be
repeated within 30min after
unpacking.
28.06.2007
Copyright © Infineon Technologies 2007. All rights reserved.
Page 50
Toolchain
Code Generator
DAvE
Mini
IDE
IDE
Device Connect
Flash Loader
Debugger
KEIL µVision
Compiler
SDCC
Hitop
Simulator
Monitor
USPY
U2CAN
Free of
Charge
28.06.2007
Copyright © Infineon Technologies 2007. All rights reserved.
Page 51
28.06.2007
Copyright © Infineon Technologies 2007. All rights reserved.
Page 52