ISOFACE™ ISO1I813T Isolated 8 Channel Digital Input with IEC61131-2 Type 1/2/3 Characteristics Data Sheet V 2.1, 2015-05-22 Power Management & Multimarket Edition 2015-05-22 Published by Infineon Technologies AG 81726 Munich, Germany © 2015 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. ISO1I813T Revision History: 2015-05-22, V 2.1 Previous Version: Data Sheet V2.0 Page Subjects (major changes since last revision) V 2.1 Data Sheet 48,55 Typo inside register adress for GLCFG corrected V 2.0 Data Sheet 6, 9, 11 Description of SEL pin corrected 24 Chapter 3.6 Programmable Digital Input Filter updated and information about filter times added 26 Chapter 3.7 Parallel Interface Mode updated 29 Chapter 3.8.1 SPI Modes write access decription updated 34 Chapter 3.9 SYNC Operation updated 35 Chapter 3.10 Write-Read- Access and Read-Read-Access for Different Applications added 37 Table 3 System Insulation Characteristics Condition for Production test added 45 Table 15 Parallel Interface timing updated 46 Table 16 Serial Interface timing updated Trademarks of Infineon Technologies AG AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, EconoPACK™, CoolMOS™, CoolSET™, CORECONTROL™, CROSSAVE™, DAVE™, DI-POL™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPIM™, EconoPACK™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I²RF™, ISOFACE™, IsoPACK™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OptiMOS™, ORIGA™, POWERCODE™; PRIMARION™, PrimePACK™, PrimeSTACK™, PRO-SIL™, PROFET™, RASIC™, ReverSave™, SatRIC™, SIEGET™, SINDRION™, SIPMOS™, SmartLEWIS™, SOLID FLASH™, TEMPFET™, thinQ!™, TRENCHSTOP™, TriCore™. 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Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™ of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co. TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex Limited. Last Trademarks Update 2011-11-11 Data Sheet 3 V 2.1, 2015-05-22 ISO1I813T 1 1.1 1.2 1.2.1 1.2.2 Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pins of Sensor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pins of Serial and Parallel logic Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Blockdiagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 3.1 3.2 3.2.1 3.2.2 3.2.3 3.3 3.4 3.4.1 3.4.2 3.5 3.6 3.7 3.8 3.8.1 3.8.2 3.9 3.10 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Limits on VBB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC/DC Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sensor Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Type Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wire Break Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Common Error Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Digital Input Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel Interface Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Interface Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Architecture of CRC-Engines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SYNC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write-Read- Access and Read-Read-Access for Different Applications . . . . . . . . . . . . . . . . . . . . . . 4 Standard Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5 5.1 5.2 5.3 5.4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Conditions and Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics Input Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics Microcontroller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 38 39 41 43 6 6.1 6.2 6.2.1 6.2.2 6.2.3 6.3 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.3.6 Registers of Microcontroller-Interface-Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . µController Chip Registers Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Presentation of the Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sensor Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . µController Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Collective Diagnostics Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Channel Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Error Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Filter Time of Channel 0-7 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Error Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 48 49 49 49 50 51 51 51 52 53 54 55 7 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Data Sheet 4 6 6 8 8 9 12 12 12 13 14 15 18 19 19 21 22 24 26 28 29 33 34 35 V 2.1, 2015-05-22 ISO1I813T Isolated 8 Channel Digital Input with IEC61131-2 Type 1/2/3 Characteristics Product Highlights • • • • Minimization of power dissipation due to constant current characteristic Status LED output for each input Digital averaging of the input signals to suppress interference pulses Isolation between Input and Output using Coreless Transformer Technology Features Description • The ISO1I813T is an electrically isolated 8 bit data input interface in TSSOP-48 package. • • • • • • • • Complete system integration (digital sensor or switch input, galvanic isolation and intelligent micro-controller or bus-ASIC interface) 8-channel input according to IEC61131-2 (Type 1/2/3) Integrated galvanic isolation 500VAC (EN60664-1, UL1577) 3.3V/5V SPI and parallel micro-controller interface Adjustable deglitching filters Up to 500 kHz sampling frequency Wire-break detection VBB under-voltage detection Package: TSSOP-48, 8 mm x 12.5 mm This part is used to detect the signal states of eight independent input lines according to IEC61131-2 Type 1/2/3 (e.g. two-wire proximity switches) with a common ground (GNDFI). For operating sensors of type 1/2/3 in accordance with IEC61131-2, it is necessary for the device to be wired with resistors RV and REXT (it is recommended to use resistors with an accuracy of 2%, in any case < 5% - is mandatory, temperature-coefficients < 200ppm are allowed). An 8 bit parallel µC compatible interface allows to connect the IC directly to a µC system. The input interface is designed to operate with 3.3/5V CMOS compatible levels. Typical Application Programmable Logic Controllers(PLC) Industrial PC The data transfer from input to output side is realized by the integrated Coreless Transformer Technology. General Control Equipment VBB VFI VCC TS 330n DC ENA SW1 8 sensors WB IN0 12k I0H 2k I0L I7H IN7 12k 2k I7L D E S E R I A L I Z E S E R I A L I Z E SW2 digital filter /ERR L O G I C SYNC µC /CS parallel or serial interface digital filter e.g. XE166 Rosc GNDFI GND GNDBB ISO1I813T Typical Application for Sensor of Type 1/3 Data Sheet 5 V 2.1, 2015-05-22 ISO1I813T Pin Configuration and Functionality 1 Pin Configuration and Functionality The pin configuration slightly differs for the parallel or the serial interface. 1.1 Pin Configuration The ordering, type and functions of the IC pins are listed in the Table 1. Table 1 Pin Pin Configuration Parallel Interface Mode Symbol Ctrl Type Function 1) 1 GND 2 SEL 3 SYNC 4 Serial Interface Mode Symbol 2) Ctrl. Type Function 1) 2) A Logic Ground GND I PU Serial Parallel Mode Select SEL I PU Freeze Data & Diagnostics SYNC Rosc A Clock Frequency Adjustment Rosc 5 VCC A Positive 5/3.3V logic supply VCC 6 ERR OD, PU Fault Indication output ERR 7 GND A Logic Ground GND 8 AD0 IO PPZ Data output bit0 SDI I PD SPI Data input 9 AD1 IO PPZ Data output bit1 SSO O PPZ SPI Status output 10 AD2 IO PPZ Data output bit2 GND 11 AD3 IO PPZ Data output bit3 GND 12 AD4 IO PPZ Data output bit4 CRCERR O OD, PU CRC Error output 13 AD5 IO PPZ Data output bit5 SCLK I PD SPI Shift Clock input 14 AD6 IO PPZ Data output bit6 SSI I PD SPI Status input 15 AD7 IO PPZ Data output bit7 SDO O PPZ SPI Data output 16 CS I PU Chip Select CS 17 RD I PU Data Read n.c. 18 GND A Logic Ground GND 19 WR I PU Data Write MS0 I PD SPI Mode Select bit 0 20 ALE I PD Address Latch Enable MS1 I PD SPI Mode Select bit 1 21 DC_ENA I PD DC-DC Supply Enable DC_ENA 22 SW1 A DC-DC Switch Output 1 SW1 23 SW2 A DC-DC Switch Output 2 SW2 24 GND A Logic Ground GND GNDBB O Sensor Side Pins 25 GNDBB A Input Ground 26 VBB A Positive input supply voltage VBB 27 I0L A Input 0 Low, LED Out I0L 28 I0H A Input 0 High I0H 29 I1L A Input 1 Low, LED Out I1L 30 I1H A Input 1 High I1H Data Sheet 6 V 2.1, 2015-05-22 ISO1I813T Pin Configuration and Functionality Table 1 Pin Pin Configuration Parallel Interface Mode Symbol Serial Interface Mode Ctrl Type Function 1) Symbol 2) Ctrl. Type Function 1) 31 GNDBB A Input Ground GNDBB 32 I2L A Input 2 Low, LED Out I2L 33 I2H A Input 2 High I2H 34 I3L A Input 3 Low, LED Out I3L 35 I3H A Input 3 High I3H 36 TS A Sensor Type 1/2/3 Select TS 37 GNDBB A Input Ground GNDBB 38 WB A Wire Break Select WB 39 I4L A Input 4 Low, LED Out I4L 40 I4H A Input 4 High I4H 41 I5L A Input 5 Low, LED Out I5L 42 I5H A Input 5 High I5H 43 GNDBB A Input Ground GNDBB 44 I6L A Input 6 Low, LED Out I6L 45 I6H A Input 6 High I6H 46 I7L A Input 7 Low, LED Out I7L 47 I7H A Input 7 High I7H 48 GNDBB A Input Ground GNDBB 2) 1) Direction of the pin: I = input, O = output, IO = Input/Output 2) Type of the pin: A = analog, OD = Open-Drain, PU = internal Pull-Up resistor, PD = internal Pull-Down resistor, PPZ = Push-Pull pin with High-Impedance functionality Data Sheet 7 V 2.1, 2015-05-22 ISO1I813T Pin Configuration and Functionality GND 1 48 GNDBB GND 1 48 GNDBB SEL 2 47 I7H SEL 2 47 I 7H SYNC 3 46 I 7L SYNC 3 46 I7L Rosc 4 45 I6H Rosc 4 45 I 6H VCC 5 44 I 6L VCC 5 44 I6L / ERR 6 43 GNDBB /ERR 6 43 GNDBB GND 7 42 I5H GND 7 42 I 5H AD0 8 41 I 5L SDI 8 41 I5L AD1 9 40 I4H SSO 9 40 I 4H AD2 10 39 I 4L GND 10 39 I4L AD3 11 38 WB GND 11 38 WB AD4 12 37 GNDBB AD5 13 AD6 CRCERR 12 37 GNDBB 36 TS SCLK 13 14 35 I3H SSI AD7 15 34 I 3L /CS 16 33 I2H Pinout for parallel Interface Pinout for serial Interface 36 TS 14 35 I 3H SDO 15 34 I3L /CS 16 33 I 2H /RD 17 32 I 2L nc 17 32 I2L GND 18 31 GNDBB GND 18 31 GNDBB /WR 19 30 I1H MS0 19 30 I 1H ALE 20 29 I 1L MS1 20 29 I1L DC_ENA 21 28 I0H DC_ENA 21 28 I 0H SW1 22 27 I 0L SW1 22 27 I0L SW2 23 26 VBB SW2 23 26 VBB GND 24 25 GNDBB GND 24 25 GNDBB n.c. = Not Connected Figure 1 TSSOP-48 Pinout for Parallel and Serial Interface Modes 1.2 Pin Functionality 1.2.1 Pins of Sensor Interface VBB (Positive supply 9.6-35V sensor supply) VBB supplies the sensor input stage. GNDBB (Ground for VBB domain) This pin acts as the ground reference for the sensor input stage that is supplied by VBB. I0H... I7H (Input channel 0 ... 7) Sensor inputs with current sink characteristic according IEC61131-2 Type 1/2/3 which has been selected by pin TS I0L... I7L (LED output channel 0 ... 7) This pin provides the output signal to switch on the LED if the input voltage and current has been detected as “High” according to the selected type. WB (Wire-Break Select) By connecting a resistor between pin WB and pin GNDBB, the level for the Wire-Break detection can be adjusted (refer to Table 10 for corresponding resistor value). This pin is for static configuration (pin-strapping). The input voltage at pin WB is not allowed to be changed during operation. TS (Type Select) By connecting a resistor between TS and GNDBB the sensor type (Type 1/2/3) can be selected (refer to Table 10 for corresponding resistor value). This pin is for static configuration (pin-strapping). The input voltage at pin TS is not allowed to be changed during operation. Data Sheet 8 V 2.1, 2015-05-22 ISO1I813T Pin Configuration and Functionality 1.2.2 Pins of Serial and Parallel logic Interface Some pins are common for both interface types, some others are specific for the parallel or serial access. VCC (Positive 3.3/5V logic supply) VCC supplies the output interface that is electrically isolated from the sensor input stage. The interface can be supplied with 3.3/5V. GND (Ground for VCC domain) This pin acts as the ground reference for the uC-interface that is supplied by pin VCC. Rosc (Clock Adjustment) A high precision resistor has to be connected between pin Rosc and pin GND to set the frequency of the sampling clock. DC_ENA (DC-DC Converter Enable) When the DC_ENA pin is connected to VCC, the internal DC-DC driver is activated. When DC_ENA is in the state Low, the switches are not driven. The input voltage must not change during operation. This pin has an internal Pull-Down resistor. SW1, SW2 (DC-DC switch outputs 1/2) When the pin DC_ENA is connected to VCC, the outputs SW1 and SW2 switch at the clock-frequency determined by the resistor at pin Rosc to supply the external push-pull converter. The switching frequency can be divided by two by setting the responsible bit in the GLCFG register (see also Chapter 6). Both outputs provide an open drain functionality. ERR (Error) The active Low ERR signal contains the OR-wired information of the sensor input undervoltage and missing voltage detection, the internal data transmission failure detection unit and the overcurrent fault of the DC-DCconverter. The output pin ERR provides an open drain functionality. During Start Up this pin ERR is pulled to High. This pin ERR has an internal Pull-Up resistor. In normal operation the signal ERR is High. See Chapter 3.5 for more details. SEL (Serial or Parallel Mode Select) When this pin is in a logic Low state, the IC operates in Parallel Mode. For Serial Mode operation the pin has to be pulled into logic High state. During Start Up the IC is operating in Serial Mode. This pin has an internal Pull-Up resistor. This pin must not change during operation. SYNC When this pin is in a logic High state, the IC operates in continuous mode with the internal sampling clock. In isochronous mode, the internal data and diagnostics registers are synchronized on each falling edge detected at SYNC. The internal data and diagnostics registers are frozen with the falling edge of SYNC. In logic Low state the internal data and diagnostic registers are not updated. During Start-Up this pin is pulled to High state. This pin has an internal Pull-Up resistor. (see also Chapter 3.9) CS (Chip Select) When the pin CS pin is logic Low, the IC interface is enabled and data can be transferred. This pin CS has an internal Pull-Up resistor. Data Sheet 9 V 2.1, 2015-05-22 ISO1I813T Pin Configuration and Functionality The following pins are provided in the parallel interface mode AD7:AD0 (AddressData input / output bit7 ... bit0) The pins AD0 .. AD7 are the bidirectional input / outputs for data write and read. Depending on the state of the pins ALE, RD, WR and the AD7 bit register addresses or data can be transferred between the internal registers and the parallel interface of a e.g. micro-controller . RD, WR (Read / Write) By pulling one of these pins down, a read or write transaction is initiated on the AddressData bus and the data becomes valid. These pins have internal Pull-Up resistors. ALE (Address Latch Enable) The pin ALE is used to select between address (ALE is in a logic High state) or data (ALE is in a logic Low state). Furthermore, a read or write transaction can be selected in conjunction with the AD7 bit. When ALE is pulled high, addresses are transferred and latched over the bit AD0 to AD6. The AD7 bit serves for a read access (AD7 is Low) or a write access (AD7 is High) at this address. During the Low State of ALE all transactions hit the same adress. This pin has an internal Pull-Down resistor. The following pins are provided in the serial interface mode MS0, MS1 (Serial Mode Select) By driving the pins MS, MS1 to Logic High or Logic Low the Serial Interface Mode can be selected. These pins have internal Pull-Down resistors. The mode of the Serial Interface can be changed by the user during operation. SCLK (Serial interface shift clock) Input data are sampled with the rising edge and output data are updated with the falling edge of this input clock signal. This pin SCLK has an internal Pull-Down resistor. SDI, SSI (Serial interface data/status input ) SDI/SSI data is put into a dedicated FIFO to program the filtering time and mask the Wire-Break diagnostic bits of each channel (SPI Mode 2 and 3). It is also used to set the address of the register, which is intended to be accessed. This pin has an internal Pull-Down resistor. SDO, SSO (Serial interface data/status outputs) SDO provides the sensor data bits and or the register content, SSO provides the sensor diagnostics bits. CRCERR (CRC Error output) This pin CRCERR is in a logic Low state when CRC errors or Shift-Clock errors are detected internally. This pin CRCERR provides an open drain functionality. This pin has an internal Pull-Up resistor. Data Sheet 10 V 2.1, 2015-05-22 ISO1I813T Blockdiagram 2 Blockdiagram VBB Rosc UVLO MV WB TS VCC OSC UV SW1 UVLO DC/DC SW2 CLK DC_ENA WireBreak Selector Startup /ERR TX/RX Control Type Selector TX/RX Common Control Error SYNC Validation / CS /WR I0H I0L Sensor Circuit 0 I1H I1L Sensor Circuit 2 Sensor Circuit 3 Sensor Circuit 4 S E R DIAG S DATA E DIAG DIAG DIAG I R A I DATA L A DIAG I L Z I E Z DIAG E DATA DIAG DATA DIAG DATA Sensor Circuit 7 DIAG DATA DIAG DIAG Filter 0 DATA /RD ALE DATA E DATA Sensor Circuit 6 I7H I7L D DIAG DATA Sensor Circuit 5 I6H I6L DIAG DATA I5H I5L DIAG DATA I4H I4L DIAG DATA I3H I3L DATA DATA Sensor Circuit 1 I2H I2L DATA Filter 1 AD7 U P D A T E G A T E AD6 Filter 2 AD5 AD4 Filter 3 parallel interface AD3 AD2 Filter 4 Interface AD1 AD0 Handler SCLK Filter 5 SDO SDI Filter 6 SSO SSI Filter 7 DIAG serial interface MS0 MS1 Control Registers CRC GNDBB GND /CRCERR SEL 813 T - Blockdiagram Figure 2 Data Sheet Block Diagram ISO1I813T 11 V 2.1, 2015-05-22 ISO1I813T Functional Description 3 Functional Description The ISO1I813T is an electrically isolated 8 bit data input interface. This part is used to detect the signal states of eight independent input lines according to IEC61131-2 Type 1/2/3 (e.g. two-wire proximity switches) with a common ground (GNDBB). 3.1 Introduction The current in the input circuit is determined by the switching element in state “0” and by the characteristics of the input stage in state “1”. The octal input device is intended for a configuration comprising two specified external resistors per channel, as shown in Figure 10 “Typical Application for Sensor Input Type 1, 2 and 3” on Page 19. As a result the power dissipation within the package is at a minimum. The voltage dependent current through the external resistor REXT is compensated by a negative differential resistance of the current sink across pins IxH and IxL, therefore input INx behaves like a constant current sink. The comparator assigns level 1 or 0 to the voltage present at input IxH. To improve interference protection, the comparator is provided with hysteresis. A status LED is connected in series with the input circuit (REXT and current sink). If no LED is used an external resistor of 2 kΩ (type 1 and 3) has to be connected between IxL and GNDBB. The specified switching thresholds may change if the LED is replaced by a resistor. The internal LED drive short-circuits the status LED if the comparator detects “0”. A constant current sink in parallel with the LED reduces the operating current of the LED, and a voltage limiter ensures that the input circuit remains operational if the LED opens, but the switching thresholds may change. For each channel an adjustable digital filter is provided which samples the comparator signal at a rate configured by programming internal registers. The digital filter is designed to provide averaging characteristics. If the input value remains the same for the selected number of sampling values, then the output changes to the corresponding state. The µC compatible interfaces allow a direct connection to the ports of a microcontroller without the need for other components. The diagnostic logic on the chip monitors the internal data transfer as well as the sensor input supply. The information is sent via the internal coreless transformer to the pin ERR at the input interface 3.2 Power Supply The IC contains two electrically isolated voltage domains that are independent from each other. The microcontroller interface is supplied via pin VCC, GND and the input stage is supplied via pin VBB, GNDBB. The different voltage domains can be switched on at different times. Figure 4 shows the Start Up behaviour if both voltage domains are powered by an external power supply. If the VCC and VBB voltage have reached their operating range and the internal data transmission has been started successfully, the IC indicates the end of the Start Up procedure by setting the pin ERR to logic low. In the situation of a supply voltage drop at VBB on the Sense Side - even short - the Sense Chip requires a proper restart and therefore the µController Side control unit needs to react accordingly, especially to guarantee the integrity of the sensor data provided to the filter stage. Data Sheet 12 V 2.1, 2015-05-22 ISO1I813T Functional Description 3.2.1 Voltage Limits on VBB VVBB Voltage VUV VVBBhys VMV VVBBhys VRESET VVBBhys VVBBuvoff VVBBuvon VVBBmvoff VVBBmvon VVBBoff VVBBon Time RST MV UV por_uv_mv_events .vsd Figure 3 Start Up Procedure with external Power Supply During UVLO, all registers are reset to their reset values as specified in the Chapter 6.2. As a result, the flags TE, UV as well as MV are High and the ERR pin is Low (error condition). Immediately after the reset is released, the IC is first configured by “reading“ the logic level of the SEL, MS1, MS0 (when available). The IC powers up as a serial device (SEL has a pull-up resistor). The supply voltage VBB is monitored during operation by two internal comparators (with typ. 8 µs blanking time @ 500kHz fscantyp) detecting: • • VBB Undervoltage: If the voltage drops below the UV threshold (see Table 7), the UV-bit in the GLERR register is set High. The IC remains in normal operation. VBB Missing Voltage: If the voltage further drops below the MV threshold, lower than the previous threshold, the MV-bit in the GLERR register is set, the Sense Side of the IC is turned off when reaching the VRESET threshold whereas the Micro-Controller Side remains active. These 2 thresholds are inactive when the IC operates in Self Power Mode i.e. when the DC_ENA pin is High. Note: In case DC_ENA is High the integrated DC/DC driver is active. The driver stage is self-protected in overload condition: the internal switches will be turned off as long as the overcurrent condition is detected and the IC will automatically restart once the overload condition disappears. Important: Since the UV and MV (as well as the TE and W4S) bits used for generating the ERR signal are preset to High during UVLO, the ERR pin is Low after power up. Therefore the ERR signal requires to be explicitly cleared after power up. At least one read access to the GLERR and INTERR registers is needed to update those status bits and thus release the ERR pin. Data Sheet 13 V 2.1, 2015-05-22 ISO1I813T Functional Description 3.2.2 External Supply Figure 4 shows the Start Up behaviour if both voltage domains are powered by an external power supply. If the VCC and VBB voltage have reached their operating range and the internal data transmission has been started successfully, the IC indicates the end of the Start Up procedure by setting the pin ERR to logic low. 16 V 13 V 9.3 V 2.85 V VB B IC pins VCC 1 DC_ENA 0 1 /ERR 0 1 UV 0 MV GL ERR register 1 0 1 CF 0 1 Read Access to Adr. 04H 0 1 DC_ERR 0 1 W4S INT ERR register 0 1 TE 0 1 Read Access to Adr. 16H 0 tds_startup_timing_813 .vsd Figure 4 Data Sheet Start Up procedure with external power supply 14 V 2.1, 2015-05-22 ISO1I813T Functional Description 3.2.3 DC/DC Supply µC Supply (5V / 3.3V) VCC PP Output driver VBB SW1 Clk Temp. Sense :2 GLCFG:DCK SW2 N1 GND N2 Tr GNDBB VCC µC Supply (GND) DC_ENA µC-Domain Figure 5 dcdc _typapp .VSD Sense-Domain Typical Circuitry for Self Powered Mode with Push-Pull Converter The IC can as well operate in self powered mode. In this case, the Process Side (Sense-Domain) can be supplied at VBB with an isolated push-pull converter connected to the Micro-controller Side and driven by the pins SW1 and SW2 . The internal driver stage at SW1 and SW2 is designed to power up two ISO1I813T (refer to Table 8). The DC/DC-Converter is driven by the internal clock. Parameters are calculated with the internal clock of 500 kHz. By setting the DCK Bit in the GLCFG register a prescaler by 2 can be activated. Should the user adjust the internal clock to a different frequency the transformer has to be adjusted accordingly. The short-circuit protection uses a temperature sensor located close to the drivers and disables the driver stages when a predefined temperature is reached (Figure 7, Figure 5). The target value for the switch-off-temperature is 160°C with a hysteresis of < 10°C. That means that the drivers are switched off at a junction temperature of 160 °C and switched on at a junction temperature of <=150°C Data Sheet 15 V 2.1, 2015-05-22 ISO1I813T Functional Description 16 V 13 V 9.3 V 2.85 V VC C IC pins B VB 1 DC_ENA 0 1 /ERR 0 1 UV t VBBfil 0 GL ERR register 1 MV 0 1 CF 0 1 DC_ERR 0 1 INT ERR register W4S 0 1 TE 0 1 Read Access to Adr. 16H 0 tds _startupdcdc _timing_813.vsd Figure 6 Data Sheet Start Up Procedure with DC/DC Supply 16 V 2.1, 2015-05-22 ISO1I813T Functional Description VBB 9.3 V 8V Overtemperature detected at DC-DC IC pins Restart after returning from OT SW1, SW2 DC_ENA /ERR DC_ERR INT ERR register W4S TE Read Access to Adr. 16H Sense-Chip Power-Up Sense-Chip Shut Down Sense-Chip Restart uc_dcovt_timing_813.vsd Figure 7 Data Sheet Restart Procedure after VBB drop due to DC/DC Supply Overtemperature 17 V 2.1, 2015-05-22 ISO1I813T Functional Description 3.3 Internal Oscillator An external resistor has to be connected to Rosc and allows the adjustment of the frequency as shown in Figure 8. 600 500 KHz 400 300 200 100 0 0 50 100 150 200 250 Resistance at Rosc (KOhm) Figure 8 Internal Frequency Setting at Rosc The internal oscillator provides the scan clock for the sampling of the sensor data and diagnostics as well as for the internal digital averaging filters. Therefore the filter times as defined in the Table 11 for the typical frequency of 500 KHz will change accordingly. As an example, it is possible to define filter time longer than 20 ms by reducing the internal oscillator frequency. Moreover, in the applications where the IC current consumption is critical, it is possible to reduce the internal oscillator frequency by increasing the ROSC (see Figure 9). 12 Supply Current [mA] 10 8 6 4 2 0 0 100 200 300 400 500 600 CT_Frequency [kHz] Sense Chip 24V Figure 9 Data Sheet uC Chip 5V uC Chip 3.3V IC Current Consumption in function of the internal frequency 18 V 2.1, 2015-05-22 ISO1I813T Functional Description 3.4 Sensor Input 3.4.1 Input Type Select The sensor input structures are shown in Figure 10 (Type 1,2,3). Due to its active current a V-I-characteristic as shown in Figure 11 is maintained. This V-I-curve is well within the IEC 61131 standard requirements of Type 1, Type 2 and Type 3 sensors, respectively. The Figure 12 shows the typical application for sensor of type 2. It is recommended to choose for the external resistors REXT, RV, RLED an accuracy of 2 % (< 5% is mandatory) otherwise the V/I-characteristic shown in Figure 11 cannot be guaranteed. VFI VBB WB Sensor x x = 1,...,8 RWB TS RTS RV INx IxH mA DATAx Rext IxL GNDBB STATUSx Figure 10 Type 1,3 Type 2 RV 2kΩ 1.5kΩ Rext 12kΩ 8.5kΩ Typical Application for Sensor Input Type 1, 2 and 3 The filtered input-data information is visible in the Input Channel Data Register : INPDATA and is also described by the nomenclature : input-data. Data Sheet 19 V 2.1, 2015-05-22 ISO1I813T Functional Description VFI=30V 10 10 15V/11V VINxDset VINxDhys VINxDclr active current sink 5V 00 00 -3V 0.5mA I INxOpen 2mA/3mA I INxsnkC,M "open" 01 00 Data Bit must be zero Figure 11 15mA Data Bit must be one 10 Data Bit = 1, Status Bit = 0 Sensor Input Characteristics VBB VFI VCC TS 330n DC ENA SW1 WB IN0 4 sensors only 8,2k I0H 1.5k I0L I1H IN1 8,2k 1.5k I1L ... D E S E R I A L I Z E S E R I A L I Z E I7H /ERR L O G I C SYNC µC /CS e.g. XE166 parallel or serial interface digital filter Rosc I7L GNDFI SW2 digital filter GND GNDBB ISO1I813T Figure 12 Data Sheet Typical Application for Sensor Type 2 20 V 2.1, 2015-05-22 ISO1I813T Functional Description 3.4.2 Wire Break Detection The wire-break current can be adjusted by the RWB-resistor value connected to the pin WB (Figure 13). The minimum wirebreak-current can be choosen only when a LED- or Zener-Diode is connected to the pin IxL with a forward current in the range of few uA in the voltage range below 1 V. In the case of a connected resistor at IxL a large current is flowing across the external resistor Rext and the IxL-resistor (RLED). This part cannot be measured internally and has to be added to the internal current part. In this case the minimum adjustable current is 230uA (RLED = 2kOhm). The WB bits in the status register have a sticky (latched) property and remains set as long as they are not cleared by a read access and the fault condition is not detected anymore. Wire-Break-Current Versus RWB 450 Wire-Break-Current[uA] 400 350 300 250 200 150 100 50 0 25 30 35 40 45 50 55 RWB[kOhm] WBmin_LED Figure 13 Data Sheet WBmax_LED WBmin_Rled WBmax_Rled Wire Break Detection for Type 1,3 (typ. @ 25°C) 21 V 2.1, 2015-05-22 ISO1I813T Functional Description Wire-Break-Current Versus RWB 800 Wire-Break-Current[uA] 700 600 500 400 300 200 100 0 25 30 35 40 45 50 55 RWB[kOhm] WBmin_LED Figure 14 WBmax_LED WBmin_Rled WBmax_Rled Wire Break Detection for Type 2 (typ. @ 25°C) In the case of Type 2 two sense inputs are switched in parallel to achieve 2 * 3 mA (Figure 12). In each sense input a mimimum wirebreak current of 60 µA can be measured which means in sum a minimum wirebreak current of 120 µA. It is not recommended to use external resistors at the pins IxL in case of wirebreak measurements. The recommended value would be RLED = 1.2 kΩ which has been choosen in order not to produce a large voltage drop between IxL and GNDBB which in turn would limit the voltage drop across the sink. The low value of RLED would cause a high external current in case of wirebreak-measurements which has to be multiplied by two due to the parallel circuitry of the sense inputs. The filtered wirebreak-diagnosis is visible in the Collective Diagnostic Register : DIAG and is also described by the nomenclature: status. 3.5 Common Error Output The input (VBB) undervoltage and missing voltage status which are transmitted via the integrated coreless transformer to the output block and the internal data transmission monitoring information are evaluated in the common error output block, see Figure 15. In self-powered mode, extra information in case of over-current at SW1/2 is evaluated as well. In case of an internal data transmission error the data and status bits are replaced by the last valid transmission. Moreover, if four consecutive erroneous data transmissions (TE1=1) occur, an internal error signal (TE4=1) is set. The averaging filters are reset and this status is held until four consecutive error-free transmissions (TE1=0) occur. An example timing diagram is shown in Figure 15. This internal error signal is OR-wired with the current VBB undervoltage and missing voltage status. Additionally in the ISO1I813T, the Collective Diagnostics flag is combined in the ERR. Since the output error signal is active-Low, the OR-wired result is negated. Data Sheet 22 V 2.1, 2015-05-22 ISO1I813T Functional Description In the Self Powered mode, the UV and MV are masked out. Instead the DC_ERR bit of the register INTERR is combined with the Transmission Error signal and output at the pin ERR. The output stage at pin ERR has an open drain functionality with a pull-up resistor. See Table 13 for the electrical characteristics. TRIG scan trigger TE1 transmission error TE4 TRIG DC_ERR VBB undervoltage UV 1 /ERR TE1 0 1 2 3 0 1 2 3 TE4 MUX DC/DC Converter Error filter N O R VBB missing voltage MV /ERR DC_ENA W4S Wait for Sense Collective Diagnostics Error Figure 15 Data Sheet CF (with parallel interface only) Common Error Output 23 V 2.1, 2015-05-22 ISO1I813T Functional Description 3.6 Programmable Digital Input Filter The sensor data and diagnosis bits of each input channel can be filtered by a configurable digital input filter. If selected, the filter changes its output according to an averaging rule with a selectable average length. When the sensor state changes without any spikes and noise the change is delayed by the averaging length. Sensor spikes that are shorter than the averaging length are suppressed. Figure 16 shows the behaviour of the filter. The clock of the Digital Filter is supplied from the internal oscillator. Therefore the filtertime depends on the oscillator frequency setting. For the filtering times of 1.6 msec , 3.2 msec , 10 msec , 20 msec a prescaler was used. Therefore the update interval was choosen to be 4 usec, 8 usec, 64 usec , 64 usec respectively (based on 500 kHz clock). scan trigger filter input output is 1 N-1 N-2 N-3 output is unchanged filter state 2 1 0 output is 0 filter output averaging time Figure 16 Digital Filter Behavior The averaging length is selected for each channel individually using the configuration registers COEFIL0-7. The programmed filter time apply for both the data and the diagnostics of one channel. See Table 11 for the different setting options including filter bypass. Figure 17 and Table 17 describe the timing for changing filter-coefficients. Especially timing restrictions have to be obeyed implying a minimal processing time until the new configuration and the filtered data are valid and can e.g. be frozen with the pin SYNC. Changing the filter coefficients means resetting always the related filter. tfilwr t filrd /CS SCLK SDI Wr/Adr03 SDO INPDATA Coef3 DIAG Wr/Adr04 Coef4 INPDATA DIAG Rd/Adr04 XX INPDATA Coef4 Rd tfilrdy SYNC t SPI Mode 2 Coeff_Timing3.vsd Figure 17 Filter Time Programming and Update Timing Whereas the absolute filter time depends on the internal oscillator frequency accuracy, the maximal jitter per channel of the IC is 1.5 %. The channel jitter defined in the Figure 18 is due to the sampling error of the sensor data with the internal clock and applies equally for all the channels. Data Sheet 24 V 2.1, 2015-05-22 ISO1I813T Functional Description Furthermore, a fixed propagation delay has to be taken into account due to the data transmission over the Coreless Transformer. Channel Input (e.g. IN0) int. clock at filter input (internal ) tctdelay tfil (e.g. 3,2 ms) Filter Output channel jitter tchnjitter /CS tcsrdy SCLK data SDO valid t Jitter _Timing.vsd Figure 18 Data Sheet Channel Jitter Definition 25 V 2.1, 2015-05-22 ISO1I813T Functional Description 3.7 Parallel Interface Mode The ISO1I813T contains a parallel interface that can be selected by pulling the pin SEL to logic Low state. The interface can be directly controlled by the microcontroller output ports. (Figure 19). The output pins AD7:AD0 are in state “Z” as long as CS=1. Otherwise, new sensor data bits (Input-Value) or diagnosis bits (Status) are driven with the falling edge of RD and provided at pins AD7:AD0. Incoming data for a write access are sampled with the rising edge of WR. Although write- and read-commands can be distinguished by the pins WR and RD additionally the MSB of the address-byte has to be set or not set (analog to the serial access). Write commands are configured with the MSB of the addess-byte set to “1”, read commands are configured with the MSB of the address-byte set to “0”. VCC VCC /CS ALE /RD, /WR AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 MCU (e.g. XE166) or ASIC SEL ISO1I813T parallel _interface 1.vsd Figure 19 Bus Configuration for Parallel Mode The timing requirements for the parallel interface are shown in Figure 20, Figure 21 and Table 15. Data Sheet 26 V 2.1, 2015-05-22 ISO1I813T Functional Description /CS tCSD tRD_su ALE tRDlow tRD_hd tRDhigh /RD tAD_su tAD_hd AD[7:0] GLERR address (04h) tclrrdy tfloat tADvalid GLERR data GLERR data GLERR 00h Rd_timing_813T - uc _parallel Figure 20 Parallel Bus Timing Read /CS tCSD tWR_su ALE tWRhigh tWR_hd /WR tWR_su tWR_hd tAD_su tAD_hd AD[7:0] COEFILx address COEFILx COEFILx data 00h tlat COEFILx data 0Fh Wr_timing_813 T - uc_parallel Figure 21 Data Sheet Parallel Bus Timing Write 27 V 2.1, 2015-05-22 ISO1I813T Functional Description 3.8 Serial Interface Mode The ISO1I813T contains two serial interfaces that can be activated by pulling the pin SEL to logic High state. The interface can be directly controlled by the microcontroller output ports. The output pins SDO and SSO are in state “Z” as long as CS=1. Otherwise, the bits are sampled with the falling edge of CS. With every falling edge of SCLK the bits are provided serially to the pin SDO and SSO respectively. At the same time, the inputs to SDI, SSI are registered into input-FIFO buffers (sampled with the rising edge of SCLK). When all internally sampled bits have been transferred to SDO/SSO, the buffered bits from the inputs SDI/SSI are provided to these pins (daisy-chain support). The timing requirements for the serial interface are shown in Figure 22 and in Table 16. inactive /CS tSCLK_su active tCSD tSCLK receive edge SCLK tSU SDI, SSI transmit edge tHD t CSH MSB LSB tCS_valid SDO, SSO tSCLK_valid MSB t float LSB Serial_Bus_Timing Figure 22 Serial Bus Timing Several SPI topologies are supported: pure bus topology, daisy-chain and any combinations (Figure 23). Of course independent individual control with dedicated SPI controller interfaces for each slave IC is possible, as well. A SCLK SCLK SDO MISO0 SSO MISO1 A SCLK SCLK A MISO 0 SDO SCLK SDO SDI SDI /CS /CS SSO SCLK SCLK SCLK MISO0 SSI B B SDO C SSO SDI /CS /CS SCLK /CS SDO MCU or ASIC C SDO MCU or ASIC SCLK MCU or ASIC SDO SSO SDI /CS /CS SCLK SCLK D SCLK SDO D D SDO SDO SSO SDI /CS D SDI SSO MOSI0 SSI MOSI0 /CS /CS spi_topologies .vsd Figure 23 Data Sheet Example SPI Topologies 28 V 2.1, 2015-05-22 ISO1I813T Functional Description 3.8.1 SPI Modes The architecture provides 2 independent SPI-interfaces with serial read and serial write options. All register addresses can be accessed independently from both SPI-interfaces with one restriction : a simultaneous serial write on both SPI-interfaces is forbidden. Therefore only one temporary register for storing the write data is provided. All other combinations read (SPI_channel 1) / read (SPI_channel 2) and write (SPI_channel 1) / read (SPI_channel 2) and read (SPI_channel 1) / write (SPI_channel 2) are allowed. There are no restrictions on the selection of register addresses from both channels. Write commands are configured with the MSB of the addess-byte set to “1”, read commands are configured with the MSB of the address-byte set to “0”. 3.8.1.1 Switching Serial Modes All serial modes MS1, MS0 = 11, 01, 10, 00 are switchable during operation but not within a serial transfer frame. No internal registers are affected. Only multiplexers and CRC-engines can be activated or deactivated. Internal FSMs are reset. The user has to run one dummy serial process after switching of a serial mode to clear the serial shift registers and reset the internal FSMs. For example: switching from MS1, MS0 = 00 to MS1, MS0 = 11 means the 24 bit serial shift registers and the CRC-engines will be activated. To guarantee proper operation one dummy read sequence has to be processed means “shift in 24 bits with read address, zeros and CRC within a CS= Low frame” to operate the serial interface in the new mode. A reliable output is not guaranteed for the first serial process. The same is true for changing the serial mode in the reverse direction : from MS1, MS0 = 11 to MS1, MS0 = 00. Here at least one dummy serial access (8 SCLK-cycles) within a CS=Low frame is necessary. Be aware that in Mode01 read access the date at SDO/SSO corresponds to the adress which has been written in the frame before. Mode00 and Mode 01 support the daisy-chain application. Mode 0: MS0:=0, MS1:=0; 8 Bit Access; Daisy-Chain supported Chip select active CS SCLK MSB SDO D7 D6 D5 D4 D3 D2 D1 D0 Input-Value MSB SSO WB7 WB6 WB5 WB4 WB3 WB2 WB1 WB0 Collective Diagnosis Figure 24 Data Sheet SPI Mode 0 29 V 2.1, 2015-05-22 ISO1I813T Functional Description Mode 1: MS0:=1, MS1:=0; 16 Bit Access; Daisy-Chain supported Chip select active CS SCLK Write Command MSB SDI 1 MSB A6 A5 1 A3 A2 A1 A0 D7 D6 Register-Adress 1 MSB SSI A4 A5 A4 A3 A2 A1 A0 D7 D6 Register-Adress 2 D7 D6 WB7 D2 D1 D0 D5 D4 D3 D2 D1 D0 MSB D5 D4 D3 D2 D1 D0 Input-Value MSB SSO D3 Value 2 (valid on write) MSB SDO D4 Value 1 (valid on write) MSB A6 D5 WB7 WB6 WB5 WB4 WB3 WB2 WB1 Collective Diagnosis MSB WB6 WB5 WB4 WB3 WB2 WB1 WB0 UV 0 MV CF 0 Global Error Bits Collective Diagnosis WB0 W4S TE DC_ ERR Internal Error Bits Read Command MSB SDI 0 MSB A6 A5 A4 A3 A2 A1 A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D6 D5 D4 D3 D2 D1 D0 D2 D1 D0 Register-Adress 1 MSB SSI 0 MSB A6 A5 A4 A3 A2 A1 A0 0 Register-Adress 2 MSB SDO D7 MSB D6 WB7 D4 D3 D2 D1 D0 Input-Value MSB SSO D5 Data Sheet Register Data 1 MSB WB6 WB5 WB4 WB3 WB2 WB1 WB0 D7 D6 D5 D4 D3 Register Data 2 Collective Diagnosis Figure 25 D7 SPI Mode 1 30 V 2.1, 2015-05-22 ISO1I813T Functional Description Mode 2: MS0:=0, MS1:=1; 16 Bit Access; No Daisy-Chain supported Chip select active CS Write Command SCLK MSB SDI MSB 1 A6 A5 A4 A3 A2 A1 A0 D7 D6 Register-Adress 1 A6 A5 A4 A3 A2 A1 A0 Register-Adress 2 MSB D7 D6 D5 D4 D3 D7 D6 MSB D2 D1 D0 D2 D1 D0 D5 D4 D3 D2 D1 D0 Value 2 (valid on write) WB7 WB6 WB5 WB4 WB3 WB2 WB1 WB0 Collective Diagnosis Input Data MSB SSO D3 MSB 1 SDO D4 Value 1 (valid on write) MSB SSI D5 MSB WB7 WB6 WB5 WB4 WB3 WB2 WB1 WB0 0 Collective Diagnosis UV MV CF 0 W4S TE DC_ ERR Internal Error Bits Global Error Bits Read Command MSB SDI 0 MSB A6 A5 A4 A3 A2 A1 A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D6 D5 D4 D3 D2 D1 D0 D2 D1 D0 Register-Adress 1 MSB SSI 0 MSB A6 A5 A4 A3 A2 A1 A0 0 Register-Adress 2 MSB SDO D7 MSB D6 D5 D4 D3 D2 D1 D0 D7 Input Data Register Data 1 MSB SSO WB7 MSB WB6 WB5 WB4 WB3 WB2 WB1 WB0 Collective Diagnosis Figure 26 Data Sheet D7 D6 D5 D4 D3 Register Data 2 SPI Mode 2 31 V 2.1, 2015-05-22 ISO1I813T Functional Description Mode 3: MS0:=1, MS1:=1; 24 Bit Access; No Daisy-Chain supported Chip select active CS SCLK Write Command MSB SDI 1 MSB A6 1 A6 D7 A3 A2 A1 A0 A5 A4 A3 D7 MSB A2 A1 A0 D7 Register-Adress 2 MSB SDO A4 Register-Adress 1 MSB SSI A5 MSB D6 D6 D3 D2 D1 D0 Value 1 (valid on write) D6 D5 D4 D3 0 0 0 C4 D2 D1 D0 0 C3 C2 C1 C0 C1 C0 C1 C0 C1 C0 Checksum 1 MSB 0 0 C4 Value 2 (valid on write) D5 D4 D3 D2 D1 C3 C2 Checksum 2 D0 WB7 WB6 WB5 WB4 WB3 WB2 WB1 WB0 Input-Data WB7 D4 MSB UV MV CF W4S DC_ ERR CF C4 Error * Collective Diagnosis MSB SSO D5 C3 C2 Checksum 3 MSB WB6 WB5 WB4 WB3 WB2 WB1 WB0 0 Collective Diagnosis UV MV CF 0 W4S TE DC_ GLC2 GLC1 GLC0 C4 ERR Internal Error Global Error Global Config C3 C2 Checksum 4 Read Command MSB SDI 0 MSB A6 A5 A4 A3 A2 A1 A0 0 MSB 0 0 0 0 0 0 0 0 0 0 C4 MSB 0 A5 A4 A3 A2 A1 A0 0 0 0 0 0 0 0 0 0 0 0 C4 Register-Adress 2 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 Input-Data WB7 C3 C2 C1 C0 MSB MSB SSO C0 Checksum 2 MSB SDO C1 MSB MSB A6 C2 Checksum 1 Register-Adress 1 SSI C3 D4 D3 D2 D1 D0 UV MV CF W4S DC_ ERR CF C4 Error * Register-Data 1 C3 C2 C1 C0 Checksum 3 MSB WB6 WB5 WB4 WB3 WB2 WB1 WB0 Collective Diagnosis D7 D6 D5 D4 D3 D2 Register-Data 2 D1 D0 GLC2 GLC1 GLC0 C4 Global Config C3 C2 C1 C0 Checksum 4 *) DC_ENA = 0 , upper values DC_ENA = 1 , lower values Figure 27 SPI Mode 3 The error values in the SDO-segment depends on the setting of DC_ENA. If DC_ENA is set to ‘1’ the IC is supplied by the integrated DC/DC converter and the error information W4S, DC_ERR, CF is valid. If DC_ENA is set to ‘0’ the error information UV, MV, CF is valid Data Sheet 32 V 2.1, 2015-05-22 ISO1I813T Functional Description 3.8.2 Architecture of CRC-Engines For writing serial data into the uC-interface chip one serial-SPI-mode (MS1, MS0 = 11) delivers with the pure input data bit stream (write by an uC, 19 bits ) also the CRC-signature (5 bits). The total bitstream is fed into the CRCinput engines and processed according to the underlying CRC-algorithm serially. The CRC is a 5-Bit-checksum and will be calculated with the polynom X5+ X4+ X2+1 and is calculated from Bit [23:5]. The checksum is transfered to Bit [4:0]. After totally processed 24 serially shifted in-bits (including the CRCsignature) the total result of the CRC-algorithm processing has to be zero. In the case of another result different from zero the delivered signature is not consistent with the delivered bit stream. This will be indicated by setting the CRC_ERR Pin to Low. For reading of registers by a uC a CRC-signature (5 bits) (MS1, MS0 = 11) will be delivered with the pure data bit stream (19 bits) : data output (read by a uC). The read bitstream has to be processed according to the CRCalgorithm serially. After totally processed 19 serially shifted out-bits the CRC-signature has been calculated and delivered to the output pins SDO, SSO. CRC-Calculation Data-Stream MSB LSB ds[18] ds[i] „for all data-bits“ for (i=0; i < 19;i++) ds[0] Step 1 tmp = crc_reg[4] ^ ds[i] crc_reg[4:0] [4] [3] m= 4 [2] m= 3 crc_pol[4:0] [1] m= 2 [0] Step 3 crc_reg[0] = tmp 1 1 0 1 0 m= 1 Step 2 : Iteration for (m= 4; m > 0;m--) crc_reg[m] = crc_reg[m-1] ^(crc_pol[5-m] && tmp) Data-Stream CRC-Stream ds[18] SDO ds[0] crc_reg[4:0] Transmitting Sequence start-value : crc_reg[4:0] = 11111 Figure 28 Data Sheet CRC-Calculation 33 V 2.1, 2015-05-22 ISO1I813T Functional Description 3.9 SYNC Operation In automation systems there is sometimes the need to actualize the input-signal/collective diagnostics at the same time system-wide. Therefore a signal SYNC is needed to latch the input-signals/collective diagnostics at the given time, otherwise the input-signals/collective diagnostics have to be actualized continously with the system clock clk_500k. The filtered data and diagnostics can be synchronized on the falling edge of the SYNC pin or “frozen” by holding SYNC Low (see Figure 29 and Table 17). The filtered input data will be latched in the input-value-register and the filtered wire-break diagnosis (inclusive CFbit) will be latched into the collective diagnosis register every data-cycle when the SYNC-signal is in high state or with the falling edge of SYNC . When the SYNC-signal is in low state the input-data-register and the collective diagnosis register won’t be updated any longer. In the same way the SYNC-signal actualizes the information of the global and internal error register. The SYNC-signal doesnot affect the operation of the internal filtering-structures. Channel Input tsyncper SYNC tsyncw int. clock tsynccon Filtered Data tsyncmin /CS SYNC_Timing.vsd Figure 29 Data Sheet SYNC Operation Timing 34 V 2.1, 2015-05-22 ISO1I813T Functional Description 3.10 Write-Read- Access and Read-Read-Access for Different Applications Depending on the application different timing requirements on the CS-idle cycle (CS = high) or on the CS-period have to be obeyed ( Figure 30 ). The parameters are specified in the electrical requirements. The verification of the parameter tRD_PER is performed in the way that a wirebreak signal for 4 usec is generated, after the propagation delay over the sense chip and the CT the corresponding DIAG-bit (plus an uncertainty of +- 1 cycle (fscantyp )) has to be detected. After reading the DIAG-register it has to be assured that the DIAG-register has been cleared (after about 2 cycles with an uncertainty of +- 1 cycle (fscantyp )). Read-Timing-Parameters for Different Applications (Example for Serial Mode ; also Valid for Parallel Mode ) Write Coefil Register / Read the same Coefil Register ... /CS needed to synchronize data tCSD_WRRD = min 4,8 usec SCLK Read Diagnostic Register / Read Diagnostic Register tRD_PER = min 2,3 usec /CS clear operation of diagnostic register may not be performed at the begin of the next read -access min 0,5 usec to be tested in 1. serial mode 00, only 8 bits 2. parallel mode (specify DIAG-address in an „ALE“ -cycle, then read without changing the address SCLK Read Arbitrary Register / Read Different Register t CSD = min 0,1 usec to be tested in serial mode 10 : write COEFIL0,…,7 with data 0,…,7 ; read COEFIL0,…,7 sequentially with the specified t CSD-time; SCLK = 5 MHz /CS SCLK Figure 30 Data Sheet Critical Timing Parameters for Write-Read-Access or Read-Read-Access 35 V 2.1, 2015-05-22 ISO1I813T Standard Compliance 4 Standard Compliance The ISO1I813T allows the design of a sensor interface compliant with the standard requirements listed below: System Insulation Characteristics as shown in Table 3, System Immunity Characteristics as shown in Table 5. There requirements are valid for an application using the ISO1I813T including external circuitry (as proposed in Figure 31), not for the IC alone. Note: When the IC is not supplied, probing of the digital input interface is still possible due to the external circuitry, i.e. the 12k resistor and the LED. In addition to the current through the LED a small current IIxH flows through the pins IxH and IxL. VFI VBB VCC TS 330n DC ENA SW1 8 sensors WB IN0 12k I0H 2k I0L IN7 12k I7H 2k I7L D E S E R I A L I Z E S E R I A L I Z E SW2 digital filter /ERR L O G I C SYNC µC /CS parallel or serial interface digital filter e.g. XE166 Rosc GNDFI GND GNDBB ISO1I813T Figure 31 Recommended Application Circuit Table 2 System Absolute Maximum Ratings Parameter Symbol Values Min. Typ. Unit Max. Field Input Voltage Overvoltage 1300 ms VFIov -45 +45 V Input Voltage INx VINx -45 +45 V + I Figure 32 Data Sheet Note / Test Condition − VISO RIO ,CIO O System Insulation Characteristics 36 V 2.1, 2015-05-22 ISO1I813T Standard Compliance Table 3 System Insulation Characteristics Parameter Symbol Values Min. Typ. Pollution Degree (DIN VDE 0110/1.89, DIN EN 60664-1) Unit Max. Note / Test Condition 2 Minimum External Clearance CLR 6.7 mm Minimum External Creepage CPG 6.2 mm Maximum Working Insulation Voltage VISO 500 VAC 1 min duration1) 1) not subject to production test, verified by characterization Approvals: UL1577 Certificate Number 20120309-E311313 Data Sheet 37 V 2.1, 2015-05-22 ISO1I813T Electrical Characteristics 5 Electrical Characteristics This section comprises: • • • Operating Conditions and Power Supply (see Chapter 5.2) Electrical Characteristics Input Side (see Chapter 5.3) Electrical Characteristics Microcontroller Interface (see Chapter 5.4) Tolerance values always contain the sum of process-related tolerance values and tolerance-values based on the temperature drift within the specified temperature range. 5.1 Absolute Maximum Ratings All voltages at pins 25 to 48 are measured with respect to ground GNDBB. All voltages at pins 1 to 24 are measured with respect to GND. The voltage levels are valid if other ratings are not violated. The two voltage domains VCC, GND and VBB, GNDBB are internally electrically isolated. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 4 Absolute Maximum Ratings Parameter Symbol Value Min. Max. Unit Note / Test Condition Power Dissipation must not exceed max-value Continuous Voltage at pin VBB VVBB -0.3 45 V Peak Voltage VBB, Overvoltage 500 ms VVBB -0.3 45 V Supply Voltage VCC VVCC -0.3 6.5 V Continuous Voltage at logic pins 1 - 24 (except VLOG VCC and GND pins) -0.3 6.5 V Continuous Voltage at pin TS, WB -0.3 6.5 V TJ -40 150 °C Storage Temperature TS -50 150 °C Power Dissipation Ptot 800 mW Input Voltage Range VIxH -45 45 V Input Voltage Range VIxL -0.3 5 V Error Pin Sink Current (ERR=0) IERRsink 5 mA VERR < 0.25·VVCC Error Pin Sink Current (CRCERR=0) ICRCsink 5 mA VERR < 0.25·VVCC DC-DC switch outputs 1/2 SW1/2 20 V Electrostatic discharge voltage (Human Body Model) according to JESD22-A114-B VESD – – 2.5 kV Electrostatic discharge voltage (Charge Device Model) according to ESD STM5.3.1 - 1999 VESD – – 1.5 kV Junction Temperature Data Sheet 38 V 2.1, 2015-05-22 ISO1I813T Electrical Characteristics 5.2 Operating Conditions and Power Supply For proper operation of the device, absolute maximum rating (Chapter 5.1) and the parameter ranges in Table 5 must not be violated. Exceeding the limits of operating condition parameters may result in device malfunction or spec violations. The power supply pins VBB and VCC have the characteristics given in Table 7. Table 5 Operating Range Parameter at Tj = -40 ... 125°C Symbol Supply Voltage Logic VCC Supply Voltage Senses VBB Value Unit Note / Test Condition Min. Max. VVCC 2.85 5.5 V related to GND VVBB 9.6 35 V related to GNDBB Continuous VBB Voltage in Self-Power Mode VVBBDC 12 16 V see Figure 5 and Table 8 for operation points1) Ambient Temperature TA -40 85 °C Junction Temperature TJ -40 125 °C Common Mode Transient dVISO/dt -25 25 kV/μs Magnetic Field Immunity |HIM| 30 A/m IEC61000-4-8 Symbol Limit Values Unit Note / Test Condition 1) recommended for operation Table 6 Thermal Characteristics Parameter at Tj = -40 ... 125°C, Vbb=9.6...35V, VCC=2.85...5.5V, unless otherwise specified Min. Max. Thermal resistance junction - case top RthJC_Top 15.0. K/W measured on top side1) Thermal resistance junction - case bottom RthJC_Bot 13.8. K/W 1) Thermal resistance junction - pin RthJP 11.8 K/W 1) Thermal resistance @ 2 cm² cooling area2) (thermal conductance only by radiation and free convection) Rth(JA) 88.6 K/W 1) 1) not subject to production test, specified by design 2) Device on 50 mm x 50 mm x 1.5 mm epoxy PCB FR4 with 2 cm² (one layer, 35 µm thick) copper area. PCB is vertical without blow air. Table 7 Electrical Characteristics of the Power Supply Pins Parameter at Tj = -40 ... 125°C, Vbb=9.6...35V, VCC=2.85...5.5V, unless otherwise specified Symbol VBB UVLO startup threshold VVBBon VBB UVLO shutdown threshold VVBBoff Min. VBB UVLO Hysteresis VVBBhys VBB missing voltage OFF (MV) threshold VVBBmvoff Data Sheet Values Typ. Unit Max. 9.6 8.0 V V 1 1) V 13.9 39 Note / Test Condition V V 2.1, 2015-05-22 ISO1I813T Electrical Characteristics Table 7 Electrical Characteristics of the Power Supply Pins (cont’d) Parameter at Tj = -40 ... 125°C, Vbb=9.6...35V, VCC=2.85...5.5V, unless otherwise specified Symbol VBB missing voltage ON (MV) threshold VVBBmvon VBB undervoltage OFF (UV) threshold VVBBuvoff VBB undervoltage voltage ON (UV) threshold VVBBuvon Glitch filters for VBB missing voltage and undervoltage TVBBfil 8 µs 2) Undervoltage Current for VBB IVBBuv 3.5 mA VVBB < VVBBon Quiescent Current VBB IVBBq 5 mA VVBB = 24 V, IINx = 0, VCC = 0V Startup Delay (time between VBBon/VCCon and first data output) tVXXon 26 µs Digital Filter bypassed 2) 3) VCC UVLO startup threshold VVCCon VCC UVLO shutdown threshold VVCCoff VCC UVLO threshold hysteresis VVCChys 0.1 V Quiescent Current VCC IVCCq 3.1 mA VVCC = 5 V 2) 5) VVBB = 0V Quiescent Current VCC IVCCq 2.3 mA VVCC = 3.3 V 2) 5) VVBB = 0V Unit Note / Test Condition 140 mA 1) 2) 3) 4) 5) Values Min. Typ. Unit Max. 12.1 Note / Test Condition V 17.0 15.0 V V 2.85 2.5 V V 4) Note that the specified operation of the IC requires VVBB as given in Table 5 defined for fscantyp 500kHz not subject to production test, specified by design Note that the specified operation of the IC requires VVCC as given in Table 5 No Push-Pull Converter connected at SW1/2 Table 8 Self-Powered Supply Operation Parameter at Tj = -40 ... 125°C, Vbb=9.6...35V, VCC=2.85...5.5V, unless otherwise specified Symbol Values ON Resistance at SW1/2 RDSON 2.3 Ω Current Rating ISW 140 mA 165 °C 1) K 1) Min. Thermal overload trip temperature Tjt Typ. 157 Thermal hysteresis ΔTjt 1) not subject to production test, specified by design Data Sheet 5 40 Max. V 2.1, 2015-05-22 ISO1I813T Electrical Characteristics 5.3 Electrical Characteristics Input Side The electrical characteristics of the input side (pins 25-48) are given in Table 9. Note that some parameters refer to IN0 to IN7 which are nodes of external circuitry (see Figure 10 or Figure 31). Electrical characteristics with respect to these nodes are given for the system including the external circuitry and not for the IC alone. See also Figure 11 for the different threshold parameters. Table 9 Sensors Inputs Parameter at Tj = -40 ... 125°C, Vbb=9.6...35V, VCC=2.85...5.5V, unless otherwise specified Symbol Sink Current Limit at Saturation Edge Type 1/3 IINxsnkC13 IINxsnkC2 Sink Current Limit at Saturation Edge Type 2 Values Unit Note / Test Condition 2.3 mA VVBB=VVBBon, VINx=6.7V, VIxL=1.2V 3.3 mA VVBB=VVBBon, VINx=6.7V, VIxL=1.2V Min. Typ. Max. Sink Current Limit at Maximum Input Voltage Type 1/3 IINxsnkM13 3.4 mA VVBB=35V, VINx=30V, VIxL=2.5V Sink Current Limit at Maximum Input Voltage Type 2 IINxsnkM2 4.8 mA VVBB=35V, VINx=30V, VIxL=2.5V LED Supply Current at Maximum Input Voltage, Type 1/3 IIxLmax 2.1 3.1 mA VVBB=35V, VINx=30V, VIxL=2.5V LED Supply Current at Maximum Input Voltage, Type 2 IIxLmax 3.1 4.5 mA VVBB=35V, VINx=30V, VIxL=2.5V LED Supply Current at High Threshold Type 3 IIxL3 1.5 2.5 mA VVBB=VVBBon, VINx=11V, VIxL=2.5V LED Supply Current at High Threshold Type 2 IIxL2 2.3 3.6 mA VVBB=VVBBon, VINx=11V, VIxL=2.5V LED Supply Current at High Threshold Type 1 IIxL1 1.6 2.6 mA VVBB=VVBBon, VINx=15V, VIxL=2.5V LED Voltage recommended VFLED 1.9 3.0 V 1) Sense Voltage Switching Threshold, L→H (Type 1) VINxDset(1) 15 V VVBB=24V VIxL=2.5V 2) Sense Voltage Switching Threshold H→L (Type 1) VINxDclr(1) V VVBB=24V VIxL=2.5V 2) Hysteresis H↔L (Type 1) VINxDhys(1) Sense Voltage Switching Threshold L→H (Type 2) VINxDset(2) Sense Voltage Switching Threshold H→L (Type 2) VINxDclr(2) Hysteresis H↔L (Type 2) 1 VINxDset(3) Sense Voltage Switching Threshold H→L (Type 3) VINxDclr(3) V 11 7 VINxDhys(2) Sense Voltage Switching Threshold L→H (Type 3) Data Sheet 11 0.65 41 VVBB=24V VIxL=2.5V 2) V VVBB=24V VIxL=2.5V 2) V 11 7 V V VVBB=24V VIxL=2.5V 2) V VVBB=24V VIxL=2.5V 2) V 2.1, 2015-05-22 ISO1I813T Electrical Characteristics Table 9 Sensors Inputs (cont’d) Parameter at Tj = -40 ... 125°C, Vbb=9.6...35V, VCC=2.85...5.5V, unless otherwise specified Symbol Values Hysteresis H↔L (Type 3) VINxDhys(3) 0.7 V Input Sink Current when VVBB=0 IIxHq 300 µA VVBB=0V VIxH=30V , Ixl = open Unit Note / Test Condition Min. Typ. Unit Max. Note / Test Condition 1) not subject to production test, specified by design 2) clamped to 2.5V if “logic 1”, internally limited if logic “0” Table 10 Setting at the Configuration Pins (TS, WB) Parameter at Tj = -40 ... 125°C, Vbb=9.6...35V, VCC=2.85...5.5V, unless otherwise specified Symbol Values Min. Typ. Max. TS Pull-Down Resistance for Type RTSpd1 1 Selection 33 Ω 1) TS Pull-Down Resistance for Type RTSpd2 2 Selection 33 kΩ 1) 2) TS Pull-Down Resistance for Type RTSpd3 3 Selection 330 kΩ 1) WB pin source current IWBsource 12.5 µA RWB = 40kΩ WB pin detection current IWB 80 µA RWB = 40kΩ Wirebreak detection blanking time tWB_blank 1 µs 3) 4) tTS_blank 2 µs 3) 4) Type selection blanking time Max. WB Pin Load Capacitance CWBmax 5 pF 1) Max. TS Pin Load Capacitance CTSmax 20 pF 1) 1) 2) 3) 4) required for operation Only 4 channels can be used for this case. not subject to production test, specified by design defined for fscantyp 500kHz Data Sheet 42 V 2.1, 2015-05-22 ISO1I813T Electrical Characteristics 5.4 Electrical Characteristics Microcontroller Interface For the Parallel Mode see Table 11, Table 12, Table 14 and Table 15, For the Serial Mode see Table 11, Table 12, Table 14 and Table 16. Timing characteristics refer to CL < 50 pF and RL > 10 kΩ. Table 11 Sensor Scanning and Averaging 1) Parameter at Tj = -40 ... 125°C, Vbb=9.6...35V, VCC=2.85...5.5V, unless otherwise specified Symbol Typical Scan Frequency fscantyp 440 Scan Frequency Range fscanrge 50 Input Scan Propagation Delay Filter Bypass delay Values Min. Typ. Unit Note / Test Condition 510 kHz ROSC = 22.1 kΩ without tolerance 500 kHz 2) Max. refer to Figure 8 tctdelay 8 µs 1) tbypass 2 µs 1) 1.2 µs including maximum channel jitter 1) Minimal Filter Output valid time tcsrdy (until Readout i.e. CS falling edge) applies equally to all channels Channel Jitter3) tchnjitter 0 2 µs for tFILT00 and tFILT01 1) Channel Jitter tchnjitter 0 1.5 % for tFILT02 to tFILT07 1) Default Digital Filter Monitoring Time tFILTdef 4 us bypass1)) Digital Filter Monitoring Time tFILT00 0.050 ms FT=00H 1) Digital Filter Monitoring Time tFILT01 0.100 ms FT=01H 1) Digital Filter Monitoring Time tFILT02 0.400 ms FT=02H 1) Digital Filter Monitoring Time tFILT03 0.800 ms FT=03H 1) Digital Filter Monitoring Time tFILT04 1.600 ms FT=04H,prescaler used1) Digital Filter Monitoring Time tFILT05 3.200 ms FT=05H, prescaler used1) Digital Filter Monitoring Time tFILT06 10.000 ms FT=06H, prescaler used1) Digital Filter Monitoring Time tFILT07 20.000 ms FT=07H, prescaler used1) Digital Filter Monitoring Time tFILToff 4.0 µs FT=08H..0FH 1) 1) valid for fscantyp = 500kHz 2) not subject to production test, specified by design 3) the channel jitter is defined in Figure 18 Data Sheet 43 V 2.1, 2015-05-22 ISO1I813T Electrical Characteristics Table 12 Setting at the Configuration Pin (Rosc) see also Figure 8 Parameter at Tj = -40 ... 125°C, Vbb=9.6...35V, VCC=2.85...5.5V, unless otherwise specified Symbol Rosc Pin Source Current IRoscsrc Rosc Resistance to GND RRosc Rosc Pin Regulated Voltage VRoscreg Values Min. Typ. 22.1 221 1.2 Max. Rosc Pin Load Capacitance CRoscmax Note / Test Condition µA ROSC = 22.1 kΩ kΩ E96 resistor Max. 50 18.4 Unit V 5 pF 1) Unit Note / Test Condition 1) required for operation Table 13 Error Pins (ERR, CRCERR) Parameter at Tj = -40 ... 125°C, Vbb=9.6...35V, VCC=2.85...5.5V, unless otherwise specified Symbol Error Pin Pull-Up Resistance (ERR=1) RERRpu Maximum Switching Frequency (ERR, CRCERR) fSW Error Pin Low voltage VERROL Values Min. Typ. Max. 50 10 kΩ 500 kHz 1) 0.25·VVC V IERROL = 5mA C 1) not subject to production test, specified by design Table 14 Logical Pins (RD, WR, ALE, MS0/1, CS, AD7:AD0, SCLK, SDO, SSO, SDI, SSI, SEL) Parameter at Tj = -40 ... 125°C, Vbb=9.6...35V, VCC=2.85...5.5V, unless otherwise specified Symbol Input Voltage High Level VIH 0.7·VVCC VVCC+0.3 V Input Voltage Low Level VIL -0.3 0.3·VVCC V Input Voltage Hysteresis VIhys Output Voltage High Level VOH 0.75·VVCC 1·VVCC V IOH = 5mA Output Voltage Low Level VOL 0 0.25·VVCC V IOL = 5mA Output Voltage High Level VOH 2.75 VOL 0.1 Output Voltage Low Level Values Min. Typ. Unit Max. 100 Note / Test Condition mV V VVCC = 2,85 V, IOH = 1mA1) V VVCC = 2,85 V - 5,5 V, IOL = 1mA 1) Typical values over temperature derived with IOH = 5 mA and IOL = 5 mA ; extrapolated to IOH = 1mA and IOL = 1mA according to simulation results, voltage drop scales with a factor of 1/5 with the change of 5 mA to 1 mA, not subject to production test Data Sheet 44 V 2.1, 2015-05-22 ISO1I813T Electrical Characteristics Table 15 Parallel Interface Parameter at Tj = -40 ... 125°C, Vbb=9.6...35V, VCC=2.85...5.5V, unless otherwise specified Symbol Values Input Pull Up Resistance (RD, WR, CS) RPU 50 kΩ Input Pull Down Resistance (ALE) RPD 50 kΩ Min. Typ. Unit Max. Note / Test Condition Read Request Frequency fRD 0.06 5 MHz repeated read access during CS = 0 Read Request Period (1/fRD) tRD 200 15000 ns repeated read access during CS = 0 CS Disable time (CS high time between two read accesses on different registers)1) tCSD 100 ns Read-Period for two read accesses on the same register (especially for DIAG, GLERR,INTERR)2) tRD_PER 2300 ns defined for fscantyp 4800 ns defined for fscantyp tCSD_WRRD CS Disable time (CS high time between a write access and a read access for reading back the written value) AD0-7 Output valid by read tADvalid /RD setup time tRD_su 55 ns /WR setup time tWR_su 55 ns /RD Low duration tRDlow 100 ns /WR Low duration tWRlow 100 ns /RD hold time tRD_hd 0 20 ns /WR hold time tWR_hd 0 20 ns tlat 600 /RD Pad to DIAG, GLERR and INTERR Registers Update (Bits Clearing) tclrrdy 4 /WR latency time 55 ns ns 6.2 µs 80 ns AD0-7 Output disable time tfloat AD0-7 Data bus setup time tAD_su 40 ns AD0-7 Data bus hold time tAD_hd 50 ns 1) not subject to production test, specified by design, verified on subset of ICs,over temperature and supply voltage, read of COEFIL-registers alternatively (Figure 30) 2) not subject to production test, specified by design, verified on subset of ICs,over temperature and supply voltage, permanent read of DIAG-register with a frequency of 500 kHz, supervision of setting of wirebreak-signal and clearing by read (Figure 30) Data Sheet 45 V 2.1, 2015-05-22 ISO1I813T Electrical Characteristics Table 16 Serial Interface Parameter at Tj = -40 ... 125°C, Vbb=9.6...35V, VCC=2.85...5.5V, unless otherwise specified Input Pull Up Resistance ( CS) Symbol Values Min. Typ. Unit Max. RPU 50 kΩ Input Pull Down Resistance (SCLK, RPD SDI) 50 kΩ Note / Test Condition Serial Clock Frequency fSCLK Serial Clock Period (1/fSCLK) tSCLK 200 ns Serial Clock High Period tSCLKH 100 ns Serial Clock Low Period tSCLKL 100 ns Minimum CS Hold time (rising edge tCSH of SCLK to rising edge of CS) 40 ns CS Disable time (CS high time between two read accesses on different registers)1) 100 ns 2300 ns defined for fscantyp tCSD_WRRD 4800 CS Disable time (CS high time between a write access and a read access for reading back the written value) ns defined for fscantyp Minimum Data setup time (required tSU time SDI to rising edge of SCLK) 5 ns Minimum Data hold time (rising edge of SCLK to SDI) 15 ns Minimum CS to SDO/SSO - Output tCS_valid valid time 50 ns /CS falling edge to first rising SCLK tSCLK_su edge 80 ns tCSD Read-Period for two read accesses tRD_PER on the same register (especially for DIAG, GLERR,INTERR)2) tHD 5 MHz Minimum SCLK to SDO/SSO Output valid time tSCLK_valid 80 ns Minimum SDO/SSO - Output disable time tfloat 65 ns New serial mode activation time (MS0/MS1 change to earliest interface access) tMS_rdy 4 µs no µController access allowed during the change3) )4) 1) not subject to production test, specified by design, verified on subset of ICs,over temperature and supply voltage, read of COEFIL-registers alternatively (Figure 30) 2) not subject to production test, specified by design, verified on subset of ICs,over temperature and supply voltage, permanent read of DIAG-register with a frequency of 500 kHz, supervision of setting of wirebreak-signal and clearing by read (Figure 30) 3) not subject to production test, specified by design 4) valid for fscantyp = 500kHz Data Sheet 46 V 2.1, 2015-05-22 ISO1I813T Electrical Characteristics Table 17 Sync and Coefficient Update Timing Parameter at Tj = -40 ... 125°C, Vbb=9.6...35V, VCC=2.85...5.5V, unless otherwise specified Symbol Minimum time interval for µCRead-Access after falling edge of SYNC-signal tsyncmin Values Min. Typ. 500 Unit Max. Note / Test Condition ns tsynccon Minimum time interval for switching from sync mode into the continuous mode 3 µs Minimum width of SYNC-signal tsyncw 200 ns SYNC-period tsyncper 500 ns Minimal time interval between 2 write cycles for filter time programming tfilwr 4 µs 1) Minimal time interval between a write cycle and a read back cycle for filter time programming tfilrd 4 µs 1) 4 µs 1) tfilrdy Minimal time interval between a filter time write cycle and updated filter data freeze 1) valid for fscantyp = 500kHz Data Sheet 47 V 2.1, 2015-05-22 ISO1I813T Registers of Microcontroller-Interface-Chip 6 Registers of Microcontroller-Interface-Chip This chapter describes the µController Chip registers. Table 6-1 Register Bit Type Definition Type Symbol Description Read r The bit can be read Read only, updated by hardware h The bit is updated by the device itself (for instance: sticky bit) Write w The bit can be written 6.1 µController Chip Registers Overview The Table 6-2 gives an overview of the µController Chip registers and their address. Table 6-2 Registers Summary Short Name Description Access Rights1) Address A7-A0 DIAG Collective Diagnostics Register (Wire-Break Detection) rh 00H INPDATA Input Data Register (Input Channel Data) rh 02H GLERR Global Error Register rh 04H COEFIL0 (COEFIL0-7) Filter Time for the Data and the Diagnostics of Channel 0 rw 06H, 86H COEFIL1 Filter Time for the Data and the Diagnostics of Channel 1 rw 08H, 88H COEFIL2 Filter Time for the Data and the Diagnostics of Channel 2 rw 0AH, 8AH COEFIL3 Filter Time for the Data and the Diagnostics of Channel 3 rw 0CH, 8CH COEFIL4 Filter Time for the Data and the Diagnostics of Channel 4 rw 0EH, 8EH COEFIL5 Filter Time for the Data and the Diagnostics of Channel 5 rw 10H, 90H COEFIL6 Filter Time for the Data and the Diagnostics of Channel 6 rw 12H, 92H COEFIL7 Filter Time for the Data and the Diagnostics of Channel 7 rw 14H, 94H INTERR Internal Error Register rh 16H GLCFG Global Configuration Register rw 18H , 98H Reserved n.a. other 1) r=read-only, rw=read-write (timing restrictions apply), rh=read update by hardware Data Sheet 48 V 2.1, 2015-05-22 ISO1I813T Registers of Microcontroller-Interface-Chip 6.2 Presentation of the Registers The µController side chip provides several 8-bit registers which can be accessed by the µController over the serial or parallel interface. Since those registers are located in the chip internal clock domain, the access is controlled by an internal arbiter processing the read / write requests as well as the synchronization requirements especially to freeze the internal registers when the isochronous mode is used (pin SYNC). Some timing requirements apply to guarantee the data consistency provided to the µController (see Electrical Characterisitcs). 6.2.1 Sensor Registers The sensor data and status (Wire-Break) detected at the channel inputs IxH/L by the sensor side chip are available in the INPDATA and DIAG registers respectively. The bits of the DIAG register have a sticky property i.e.once a wire-break condition has been detected (after the filter time), the respective bits remain set. A read access resets the sticky bits under the condition, that no wirebreak is detected anymore and no wirebreak information is pending at the filter outputs anymore. In the serial modes, both registers are per default driven out at the SDO/SSO outputs. 6.2.2 Status Registers The GLERR and INTERR registers contains the status of the IC. GLERR monitors the application relevant parameters: undervoltage (UV), missing voltage (MV) and collective fault (CF) whereas INTERR indicates the status of internal signals important for the proper operation of the IC: wait for sense chip (W4S), transmission error (TE) and DC-DC error (DC_ERR) in case of self powered mode. Those registers can be read over the serial or parallel interface especially to identify the fault causing the error pin (ERR) to be pulled down. There are different options to read those registers: either through direct addressing (e.g. parallel mode) or through the telegram mode when the serial interface is selected where the bits are shifted out during the transaction. The bits of the GLERR and INTERR registers have a sticky property and remains set as long as they are not cleared by a read access and the fault condition is not detected anymore. The Table 6-3 presents which bits are cleared depending on the serial mode and the SPI channel. In the case of the parallel interface, the bits cleared are the ones whose address is contained in the internal ALE register. Only the bits having been read can be cleared. Since the bits are frozen when a read access is detected, it is guaranted that only these bits read over the serial or parallel interface can be cleared: if the status of the bits changes during the transaction, they will not be cleared. Table 6-3 Clear of the Sticky Bits by Serial Interface Mode 0 Mode 1 Mode 2 Mode 3 Read / Write Read Read Write Read Write Read Write SPI channel-0 n.a. RDREG1) DIAG RDREG1) DIAG RDREG 1) UV, MV, W4S, DC_ERR 2) DIAG UV, MV, W4S, DC_ERR 2) SPI channel-1 DIAG DIAG RDREG1) DIAG UV, MV, W4S, TE, DC_ERR DIAG RDREG1) DIAG UV, MV, W4S, TE, DC_ERR DIAG RDREG1) DIAG UV, MV, W4S, TE, DC_ERR 1) The bits of register which is being read (Direct addressing) 2) depends on setting of DC_ENA Data Sheet 49 V 2.1, 2015-05-22 ISO1I813T Registers of Microcontroller-Interface-Chip 6.2.3 Configuration Registers The filter times of each channel can be programmed with the COEFIL0-7 registers. Since the write access requires some time to update the internal registers, specific timing requirements apply especially between 2 successive programming operations. The COEFIL0-7 registers define as well if the wire break detection should be masked or not in the DIAG register. Only one of the COEFILx registers can be written at the same time (in serial mode only one SPI channel can be used). It is possible to program a filter time and simultaneously to read out another register e.g. another channel filter time. Furthermore, the behaviour of the IC can be customized with the GLCFG register: • • • The ratio of the switching frequency of the DC-DC ouput stage over the internal clock frequency set at the pin CLKADJ can be changed from 1:1 (default) to 2:1. A soft reset can be generated to clear the filter stages and reinitialize the data transmission between Sense side and µController side chips. The automatical clearing of the DIAG register can be disabled, when the register is read without direct addressing. Data Sheet 50 V 2.1, 2015-05-22 ISO1I813T Registers of Microcontroller-Interface-Chip 6.3 µController Registers Description 6.3.1 Collective Diagnostics Register This register contains the filtered values of the Wire-Break detection of the channels 0 to 7. This register can be read by the µController. The WB[x] are set with the occurence of a wire break at input line x and can only be cleared by a read operation of this register if the wire break is not detected anymore (sticky bits). As soon as one of those bits is set, the CF-bit of the GLERR is set as well.The Chapter 6.2.2 explains the way the sticky bits are cleared. DIAG Collective Diagnostics Register (Address : 00H) 7 6 5 4 3 2 1 0 WB7 WB6 WB5 WB4 WB3 WB2 WB1 WB0 Reset Value: 00H rh Field Bits Type Description WB[x] 7-0 rh 6.3.2 Channel Wire-Break Detected This bit indicates if a Wire-Break has been detected at the channel x. 0B No wire-break signal detected at channel x. 1B A wire-break condition has been detected at channel x. Input Channel Data Register This register contains the filtered values of the input data detected at the channels 0 to 7. This register can be read by the µController. When the parallel interface is selected, the default address contained in the internal ALE register is the address of this register. INPDATA Input Data Register (Address : 02H ) 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Reset Value: 00H rh Field Bits Type Description D[x] 7-0 rh Data Sheet Input Channel Data This bit represents the input data detected at the pins IxH of the channel x depending on the sensor type selected. 0B Input Data below the input threshold. 1B Input Data above the input threshold. 51 V 2.1, 2015-05-22 ISO1I813T Registers of Microcontroller-Interface-Chip 6.3.3 Global Error Register This register contains the status of the IC parameters monitored during operation. This register can only be read by the µController. The CF-bit is the OR-combination of all the bits of the DIAG register. The bits of this register are sticky and can only be cleared when the bits are read out and the faults are not detected anymore (refer to Chapter 6.2.2 for more details). The UV and MV bits are reset to 1 when the VBB voltage is below the UVLO threshold or during transmission error between the sensor side and µController side. The bits of the GLERR register are used in the generation of the signal of the error pin (ERR) and shifted out in some of the serial modes when the SPI interface is selected. GLERR Global Error Register (Address : 04H) 7 6 5 4 0 3 2 1 0 UV MV CF r Reset Value: 06H rh Field Bits Type Description CF 0 rh Channel Fault This bit indicates that at least one wire-break condition has been detected at the channel inputs. 0B No wire-break condition has been detected at the channels . 1B At least one channel shows a wire-break condition . MV 1 rh VBB Missing Voltage This bit indicates if a missing voltage condition has been detected at the VBB pin. 0B No missing voltage detected at VBB. 1B A missing voltage condition has been detected at VBB. UV 2 rh VBB Under Voltage This bit indicates if an undervoltage condition has been detected at the VBB pin. 0B No undervoltage detected at VBB. 1B An undervoltage has been detected at VBB. 0 [7:3] r Reserved returns 0 if read. Data Sheet 52 V 2.1, 2015-05-22 ISO1I813T Registers of Microcontroller-Interface-Chip 6.3.4 Filter Time of Channel 0-7 Register These registers define the filter time for both the data and diagnostics for each channel IN0-7. The wirebreak bit can additionally be masked in the DIAG register. These registers can be modified and read by the µController. COEFIL0-7 Channel 0-7 Filter Time Register (Address : 06H - 14H for read access, 86H - 94H for write access, ) 7 6 5 4 0 0 0 MWB FT rw rw r 3 2 1 Reset Value: 1FH 0 Field Bits Type Description FT [3:0] rw Filter Time This bit field configures the filter time for averaging the Data and the Wire-Break signals detected at channels IN0-7. 00H 50 µs 01H 100 µs 02H 400 µs 03H 800 µs 04H 1,6 ms 05H 3,2 ms 06H 10 ms 07H 20 ms 08H - 0FHbypassed (default) MWB 4 rw Mask Wire-Break Detection This bit masks the filtered signal of the Wire-Break detection. 0B The wire-break signal is masked and is not visible in the DIAG register. 1B The wire-break signal is not masked and appears in the DIAG register. (default). 0 [7:5] r Reserved returns 0 if read; should be written with 0. Data Sheet 53 V 2.1, 2015-05-22 ISO1I813T Registers of Microcontroller-Interface-Chip 6.3.5 Internal Error Register This register contains the status of the internal errors monitored for safe IC operation. The bits are sticky and remain set once the fault condition is detected until a read operation occurs and the faults are resolved. The bits of the INTERR register are used in the generation of the signal of the error pin (ERR) and shifted out in some of the serial modes when the SPI interface is selected. On power up (UVLO), the bits W4S and TE are preset to High and will have to be cleared by a read access during the startup phase. INTERR IC Status Register (Address : 16H) 7 6 5 4 0 3 2 1 0 W4S TE DC_ ERR r Reset Value: 06H rh Field Bits Type Description DC_ERR 0 rh DC-DC Converter Error This bit indicates if overload condition has been detected at the SW1 or SW2 switches. 0B No overload detected. 1B Overload detected. TE 1 rh Transmission Error This bit indicates if a transmission error has been detected over the Coreless Transformer between the Sense side chip and the µController side chip. 0B No transmission error. 1B Transmission error. W4S 2 rh Wait for Sense Chip This bit indicates the Sense side chip is correctly supplied and ready for transmission. 0B Sense Side is ready. 1B Sense Side is not ready because of insufficient supply or long transmission error. 0 [7:3] r Reserved returns 0 if read. Data Sheet 54 V 2.1, 2015-05-22 ISO1I813T Registers of Microcontroller-Interface-Chip 6.3.6 Global Configuration Register This register contains configuration parameters for the sensor type selection as well as the DC-DC driver. GLCFG Global Configuration Register (Address : 18H for read access, 98H for write access, ) 7 6 5 4 3 2 DIAG SW_R DCK ACLR ST 0 r rw rw rw 1 Reset Value: 00H 0 0 r Field Bits Type Description 0 1:0 rw Reserved returns 0 if read; should be written with 0. DCK 2 rw DC-DC Driver Switching Frequency Ratio This bit indicates the ratio between the sampling clock frequency set at Rosc and the switching frequency of the DC-DC driver (pins SW1/2). 0B DC-DC switching frequency is equal to the sampling frequency (1:1) (default). 1B DC-DC switching frequency is half to the sampling frequency (2:1). SW_RST 3 rw Soft-Reset for the Filtering Stage This bit triggers the reset of the Filter registers 0B No Reset 1B Reset is generated for the Filter stage DIAG_ACLR 4 rw Diagnostics Automatical Clear This bit selects if the DIAG register is automatically cleared after any access to the DIAG register (especially for the second SPI channel at the SSO pin, see Table 6-3). The diagnostics remain in both case sticky. 0B Automatical clear after any access to the DIAG register (default) Automatical clear disabled 1B 0 [7:5] r Reserved returns 0 if read; should be written with 0. Data Sheet 55 V 2.1, 2015-05-22 ISO1I813T Package Outline Package Outline A2 7 A C A1 c O 0.10 L C D D B 0.20 C A-B D F3 F4 F2 E E1 Footprint F1 1 b 0.08 M C A-B D e A DOCUMENT NO. Z8B00158954 1) DOES NOT INCLUDE MOLD FLASH OR PROTRUSIONS. DIM A A1 A2 b c D E E1 e N L Θ F1 F2 F3 F4 Figure 7-1 INCHES MILLIMETERS MAX 1.10 0.15 1.05 0.27 0.16 12.60 MIN 0.05 0.80 0.17 0.09 12.40 MIN 0.002 0.031 0.007 0.004 0.488 8.10 BSC 6.00 0.319 BSC 6.20 0.244 0.236 0.50 BSC 48 0.50 0° MAX 0.043 0.006 0.041 0.011 0.006 0.496 SCALE 0 1.0 0 1.0 2mm EUROPEAN PROJECTION 0.020 BSC 48 0.75 8° 0.020 0° 7.80 0.29 1.30 0.50 0.030 8° 0.307 0.011 0.051 0.020 ISSUE DATE 14.06.2011 REVISION 03 Package Outline TSSOP-48 (tie bar not drawn in outline) Notes 1. You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Packages”: http://www.infineon.com/packages 2. Dimensions in mm. Data Sheet 56 V 2.1, 2015-05-22 w w w . i n f i n e o n . c o m Published by Infineon Technologies AG